Analog hardware fault diagnosis

Institution:

Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6

Location:

Paris, France

When:

Starting between October 2017 and January 2018

Funding:

3 year PhD grant, ~1700€ monthly gross salary

Thesis supervisors:

Haralampos-G. Stratigopoulos, Marie-Minerve Louërat, Hassan Aboushady

Context:

The Internet of Things (IoT) concept will have an unprecedented impact on the automotive industry in the next decade. It will connect drivers and vehicles into a flow of information enabling real-time decisions and enhancing automotive experiences. IoT relies heavily on electronic systems that are capable of sensing, processing, and exchanging information. Apart from satisfying the application objectives, such electronic systems will have strong requirements in terms of on-line self-testing, reliability, and maintainability. Failures in such electronic systems may result in catastrophic consequences, placing in danger human lives, causing environmental accidents, jeopardizing the trustworthiness and integrity of data communication, causing non-repairable damages, etc.

The scientific and technological objectives of this thesis are to develop meaningful and comprehensive diagnosis methodologies and tools for heterogeneous, mixed analog-digital Systems-on-Chip (SoCs) employed in automotive IoT applications. Diagnosis refers to the in-depth and meticulous analysis performed to identify the root cause of a failure that occurred either during manufacturing or in the field during normal operation. In particular, diagnosis aims at identifying the type of the defect that led to failure, including its localization and quantification. Automotive IoT applications demand zero defective parts per million, thus putting in place an effective diagnosis flow is essential for achieving this high reliability. Given a SoC that has failed, the objective is to develop a unified diagnosis flow that first pinpoints the IP block or interconnection that has failed (i.e. system-level diagnosis) and secondly, if the failure is attributed to an IP block, then it outputs a list of probable defects within the IP block and ranks these defects according to their probability of occurrence (i.e. IP block-level diagnosis). This thesis will focus on IP block-level diagnosis specifically for analog and mixed-signal IPs.

To demonstrate the proposed concepts and quantify their impact, we will use as case study a SoC designed by STMicroelectronics in the 28nm FDSOI technology.

Short Bibliography:

[1]	K. Huang, H.-G. Stratigopoulos, S. Mir, C. Hora, Y. Xing, and B. Kruseman, “Diagnosis of local spot defects in analog circuits,” IEEE Transactions on Instrumentation and Measurement, vol. 61, no. 10, pp. 2701–2712, 2012.

[2]	P. Mukherjee and P. Li, “Leveraging pre-silicon data to diagnose out-of-specification failures in mixed- signal circuits,” Design Automation Conference, 2014.

[3]	S. Jin, F. Ye, Z. Zhang, K. Chakrabarty, X. Gu, “Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 6, pp. 985-998, 2016.

[4]	Q. Luo, Y. He, Y. Sun, “Real-Time Fault Detection and Diagnosis System for Analog and Mixed-Signal Circuits of Acousto–Magnetic EAS Devices,” IEEE Design & Test, vol. 33, no. 3, pp. 77-90, 201.

[5]	R. D. S. Blanton, F. Wang, C. Xue, P. K. Nag, Y. Xue; X. Li, “DFM Evaluation Using IC Diagnosis Data,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 3, pp. 463-474, 2017.

Expected skills

The prospective student should be highly motivated and should have good background knowledge on analog and mixed-signal integrated circuit design, computer-aided integrated circuit design tools (e.g. Cadence), and technical computing languages (e.g. MATLAB).

About the institution:

The PhD will be conducted at the Laboratoire d’Informatique de Paris 6 (LIP6). LIP6 has as parent institutions the Centre National de la Recherche Scientific (CNRS) and the Université Pierre et Marie Curie (UPMC) which is part of Sorbonne Universités. Specifically, the student will be integrated in the Circuits Intégrés Analogiques et Numériques (CIAN) team of the Systems-on-Chip (SoC) department of LIP6. The main focuses of LIP6 are (a) safety, security, and reliability; (b) data science, intelligence, and optimization; and (c) smart devices. The CIAN team addresses specifically challenges resulting from the increasing miniaturization and heterogeneity of SoCs, the demand for trusted and reliable hardware, and the advent of emerging technologies, such as the Internet of Things (IoTs), 3D ICs, and Cyber Physical Systems (CPS).

How to apply:

Send by e-mail a detailed CV to Haralampos-G. Stratigopoulos (e-mail: haralampos.stratigopoulos AT lip6 DOT fr). At a later stage you will be requested to provide academic transcripts and recommendation letters.