Institution:

Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6

Location:

Paris, France

When:

Starting in October 2017

Funding:

3 year PhD grant, ~1700€ monthly gross salary

Thesis supervisors:

Haralampos-G. Stratigopoulos, Hassan Aboushady, Marie-Minerve Louërat

Context:

The new era of Internet of Things (IoTs) calls for ubiquitous wireless connectivity. From a design point of view, this demand imposes stringent requirements on the functionality of radio frequency (RF) transceivers, including higher data rates, more bandwidth, lower power consumption, higher re-configurability, etc. To achieve such stringent requirements, RF transceivers are designed more “aggressively” in more advance technology nodes (e.g. 65nm and below) and are integrated together with the digital processor and memory so as to achieve smaller form factors and overall lower costs. Aggressive designs in advance technology nodes become very susceptible to process variations and failures in the field of operation. This has to be seriously taken into consideration given that RF transceivers are deployed in safety-critical (e.g. avionics, space) and remote- controlled applications (e.g. sensor networks) and are operated very often in harsh environments.

This thesis envisages rethinking the design of RF transceivers towards equipping them with self-adaptation capabilities. In this context, self-adaptation refers to self-calibration in post-manufacturing to recover yield loss and self-healing to compensate for aging effects and permanent failures induced in the field of operation. This thesis envisions a holistic approach that adds value to the built-in test infrastructure that is put in place already to detect fabrication defects and excessive process variations. The built-in test infrastructure will be enhanced and combined with a feedback loop to achieve the self-calibration and self-healing objectives. The self- adaptation loop may also reuse the power control circuitry and the embedded configurability features.

The case study in this thesis will be a novel low-power RF transceiver architecture dedicated to cognitive radio applications that has been under development during the past years at LIP6.

Short Bibliography:

Expected skills:

The prospective student should be highly motivated and should have good background knowledge on analog and mixed-signal integrated circuit design, computer-aided integrated circuit design tools (e.g. Cadence), and technical computing languages (e.g. MATLAB). Knowledge on RF circuit design and analog test techniques is definitely a plus.

About the institution:

The PhD will be conducted at the Laboratoire d’Informatique de Paris 6 (LIP6). LIP6 has as parent institutions the Centre National de la Recherche Scientific (CNRS) and the Université Pierre et Marie Curie (UPMC) which is part of Sorbonne Universités. Specifically, the student will be integrated in the Circuits Intégrés Analogiques et Numériques (CIAN) team of the Systems-on-Chip (SoC) department of LIP6. The main focuses of LIP6 are (a) safety, security, and reliability; (b) data science, intelligence, and optimization; and (c) smart devices. The CIAN team addresses specifically challenges resulting from the increasing miniaturization and heterogeneity of SoCs, the demand for trusted and reliable hardware, and the advent of emerging technologies, such as the Internet of Things (IoTs), 3D ICs, and Cyber Physical Systems (CPS).

How to apply:

Send by e-mail a detailed CV to Haralampos-G. Stratigopoulos (e-mail: haralampos.stratigopoulos AT lip6 DOT fr). At a later stage you will be requested to provide academic transcripts and recommendation letters.