11 | | As all Wiki pages, this page is editable, this means that you can |
12 | | modify the contents of this page simply by using your |
13 | | web-browser. Simply click on the "Edit this page" link at the bottom |
14 | | of the page. WikiFormatting will give you a detailed description of |
15 | | available Wiki formatting commands. |
| 12 | * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC). |
| 13 | * The core of the platform is a library of SystemC simulation models for virtual components (IP cores), with a guaranteed path to silicon. |
| 14 | * The project is funded by the french ''Agence Nationale pour la Recherche''. |
| 15 | * 6 industrial companies and 11 laboratories are working together to build this platform |
| 16 | * [http://www.magillem.com/ Magillem Design Services] |
| 17 | * [http://www.silicomp.fr/ SILICOMP] |
| 18 | * [http://www.st.com/stonline/fr/index.htm STMicrelectronics] |
| 19 | * [http://www.thalesonline.com/ Thales Communications] |
| 20 | * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France] |
| 21 | * [http://www.turboconcept.com/index.php TurboConcept] |
| 22 | * [http://www-list.cea.fr/ CEA-LIST] Saclay |
| 23 | * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble |
| 24 | * [http://www.citi.insa-lyon.fr/ CITI] Lyon |
| 25 | * [http://www.enst.fr/ ENST] Paris |
| 26 | * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay |
| 27 | * [http://www.irisa.fr/home_html IRISA] Rennes |
| 28 | * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient |
| 29 | * [http://www.lip6.fr/fr/index.php LIP6] Paris |
| 30 | * [http://www.lis.inpg.fr/ LIS] Grenoble |
| 31 | * [http://www.lisif.jussieu.fr/ LISIF] Paris |
| 32 | * [http://tima.imag.fr/ TIMA] Grenoble |
22 | | You can use [wiki:TracAdmin trac-admin] to configure |
23 | | [http://trac.edgewall.org/ Trac] to better fit your project, especially in |
24 | | regard to ''components'', ''versions'' and ''milestones''. |
| 36 | The main concern is true interoperability between the SoCLib IP cores : |
| 37 | * All simulation models are written in SystemC |
| 38 | * All !SoCLib components respect the VCI /OCP communication protocol. |
| 39 | * Two types of models are available for each IPcore : CABA (Cycle Accurate / Bit Accurate), and TLM-T (Transaction Level Modeling with Time) |
| 40 | |
| 41 | = Availability = |
| 42 | |
| 43 | * All simulation models and most associated tools are distributed as free software. |
| 44 | * The !SoClib documentation can be accessed [https://www.soclib.fr/trac/dev/wiki/Start here] |
| 45 | * To actually download one or several !SoClib tools or component, you must register below. |
| 46 | * For each SoCLib component, a synthesizable RTL model is available, in order to guarantee a path to silicon, but this RTL model is NOT part of the SoCLib library, in order to preserve the IP providers business. |
| 47 | |
| 48 | ---- |