Changes between Version 2 and Version 3 of WikiStart


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Timestamp:
Jun 16, 2008, 12:52:16 PM (16 years ago)
Author:
fpecheux
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  • WikiStart

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    44
    55<div id="mainnav" class="nav"><ul><center>
     6  <li class="active first"><a accesskey="1" href="https://www.soclib.fr/trac/dev/wiki/Start">Enter technical part</a></li>
     7<!-- <li><a accesskey="2" href="https://www.soclib.fr/trac/anr">Go to ANR page</a></li> -->
    68</center></ul></div>
    79}}}
    810----
    911
    10 = What is ADAM =
     12= What is ADAM ? =
    1113
    12  * SoCLib is an open platform for virtual prototyping of multi-processors system on chip (MP-SoC).
    13  * The core of the platform is a library of SystemC simulation models for virtual components (IP cores), with a guaranteed path to silicon.
    14  * The project is funded by the french ''Agence Nationale pour la Recherche''.
    15  * 6 industrial companies and 11 laboratories are working together to build this platform
    16    * [http://www.magillem.com/ Magillem Design Services]
    17    * [http://www.silicomp.fr/ SILICOMP]
    18    * [http://www.st.com/stonline/fr/index.htm STMicrelectronics]
    19    * [http://www.thalesonline.com/ Thales Communications]
    20    * [http://www.thomson.net/GlobalEnglish/Pages/default.aspx Thomson R&D France]
    21    * [http://www.turboconcept.com/index.php TurboConcept]
    22    * [http://www-list.cea.fr/ CEA-LIST] Saclay
    23    * [http://www-leti.cea.fr/scripts/home/publigen/content/templates/show.asp?P=235&L=FR&MASTER=MASTER_WWWLETIHOME CEA-LETI] Grenoble
    24    * [http://www.citi.insa-lyon.fr/ CITI] Lyon
    25    * [http://www.enst.fr/ ENST] Paris
    26    * [http://www.inria.fr/saclay/ INRIA Futurs] Saclay
    27    * [http://www.irisa.fr/home_html IRISA] Rennes
    28    * [http://web.univ-ubs.fr/lester/www-lester/Index.php Lester] Lorient
    29    * [http://www.lip6.fr/fr/index.php LIP6] Paris
    30    * [http://www.lis.inpg.fr/ LIS] Grenoble
    31    * [http://www.lisif.jussieu.fr/ LISIF] Paris
    32    * [http://tima.imag.fr/ TIMA] Grenoble
     14ADAM stands for "Adaptive Dynamic Architecture for MP2SoCs". It is  a prospective research project
     15that directly addresses the hot topic of MPSoC self-adaptability to altered operating
     16conditions, like loss of performance, appearance of faulty hardware resources, and
     17temperature overhead. The architectures targeted by ADAM are MP2SoC, Massively
     18Parallel MultiProcessor systems on chip (more than one hundred of processing elements)
     19containing homogeneous functional blocks (all blocks can perform the work requested by
     20the application), but structurally heterogeneous (with different and process dependant
     21performances, electrical and timing characteristics and reliability). Taking simultaneously
     22these problems into account is mandatory to ensure the reliability and competitiveness of
     23embedded systems to come.
    3324
    34 = Technical features =
     25Three French laboratories with international reputation have joined their effort
     26to propose a unified approach to the self-adaptability in MP2SoC issue. Considering a standard
     272D mesh hardware architecture with a Network on Chip interconnecting clusters containing
     28processing elements and local memories, the proposal can be summarized as a three steps
     29process : non-intrusive online monitoring, online diagnosis/test, and online remapping.
     30The main contribution of the ADAM project is to make these three steps finely interact
     31through the use of onchip dynamic event databases: local databases of formatted/historized
     32events and a global database of architecture instant maps, or architecture audited views
     33classified by event types.
    3534
    36 The main concern is true interoperability between the SoCLib IP cores :
    37  * All simulation models are written in SystemC
    38  * All !SoCLib components respect the VCI /OCP communication protocol.
    39  * Two types of models are available for each IPcore : CABA (Cycle Accurate / Bit Accurate), and TLM-T (Transaction Level Modeling with Time)
    4035
    41 = Availability =
     36 * LETI (Laboratory for Electronics & Information Technology) is operated by the Technology
     37 Department of CEA (DRT "Direction de la Recherche Technologique"), the French Atomic Energy
     38 Commission. LETI is one of the largest European applied research laboratories in the field
     39 of electronics: permanent staff is approximately 1200 people. The main activities of CEA/LETI
     40 are dealing with electronics, microelectronics, microsystems and IC design.
    4241
    43  * All simulation models and most associated tools are distributed as free software.
    44  * The !SoClib documentation can be accessed [https://www.soclib.fr/trac/dev/wiki/Start here]
    45  * To actually download one or several !SoClib tools or component, you must register below.
    46  * For each SoCLib component, a synthesizable RTL model is available, in order to guarantee a path to silicon, but this RTL model is  NOT part of the SoCLib library, in order to preserve the IP providers business.
     42Its corporate goal is to bring technological innovation to the European industry, and to create
     43added value through an active Intellectual Property policy based on the management of strong patent
     44portfolio (> 500 active patents, and more than 140 filings/year) and the licensing of its technologies.
     45For more than ten years, LETI has been working on wireless systems for several applications fields:
     46medical (indoor), military (outdoor), robotics, mobiles phones and communications with mobiles
     47(cars, trains, underground, etc.). LETI is currently involved in several R&D telecom project
     48of the 6th Framework.
     49
     50The DCIS Department (DCIS: "Conception et Intégration des Systèmes") at LETI is in charge of
     51the IC design activities, and is currently addressing the following topics:
     52-       digital and mixed chip design for telecom, smart cards, RFID, image processing, smart devices, etc.
     53-       architecture exploration (HW/SW partitioning, performance evaluation, etc.)
     54-       design flow methodology (SystemC/TLM methodology, XML/Spirit, Matlab/Simulink co simulation, etc).
     55
     56An important concern at LETI is the design of mixed signal, multi-physics systems with
     57sensors/activators (MEMS, MOEMS, etc.), RF front-end and complex SOC design and architecture.
     58
     59LETI is now reference as a world wide key actor in the field of network on chip (NOC) architecture:
     60refer to LETI papers at the ISSCC'07 conference. An innovative Software Defined Radio platform based
     61on fully distributed communication and control system has been designed. This architecture framework
     62is targeting complex data flow applications. The backbone of the architecture is a layered asynchronous
     63NOC that brings scalability at architecture level and flexibility at the application level.
     64Silicon proves these concepts, and is currently used for complex Radio Access technology experimentation.
    4765
    4866----
    4967
    5068
    51 = Get your own copy =
    52 
    53 If you haven’t already done it, please register to create your account !
    54 
    55 {{{
    56 #!html
    57 <form method="post" action="http://www.soclib.fr/cgi-bin/soclib_register">
    58   <table border="0" cellpadding="5" cellspacing="0">
    59     <tr>
    60       <td align="right" valign="center"><font face="Verdana, Arial, Helvetica, sans-serif" size="2">E-mail:</font></td>
    61   <td>
    62     <input type="text" name="email" size="45" maxlength="255">
    63   </td>
    64 <td height="32">&nbsp;</td>
    65 <td height="32"> <input type=submit name="register" value="Submit request"></td>
    66 </tr>
    67 </table>
    68 </form>
    69 }}}
    70 
    71 Please note that this e-mail will be your login ID!
     69If you need write access or for any other problem please [mailto:francois.pecheux@lip6.fr?subject=ADAM%20Request contact].
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