1 | /* |
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2 | * hal_context.c - implementation of Thread Context API for TSAR-MIPS32 |
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3 | * |
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4 | * Author Alain Greiner (2016) |
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5 | * |
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6 | * Copyright (c) UPMC Sorbonne Universites |
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7 | * |
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8 | * This file is part of ALMOS-MKH. |
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9 | * |
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10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License as published by |
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12 | * the Free Software Foundation; version 2.0 of the License. |
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13 | * |
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14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU General Public License |
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20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 | */ |
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23 | |
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24 | #include <hal_types.h> |
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25 | #include <memcpy.h> |
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26 | #include <thread.h> |
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27 | #include <string.h> |
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28 | #include <process.h> |
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29 | #include <printk.h> |
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30 | #include <vmm.h> |
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31 | #include <core.h> |
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32 | #include <cluster.h> |
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33 | |
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34 | #include <hal_context.h> |
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35 | |
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36 | ///////////////////////////////////////////////////////////////////////////////////////// |
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37 | // Define various SR values for TSAR-MIPS32 |
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38 | ///////////////////////////////////////////////////////////////////////////////////////// |
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39 | |
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40 | #define SR_USR_MODE 0xFC11 |
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41 | #define SR_USR_MODE_FPU 0x2000FC11 |
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42 | #define SR_SYS_MODE 0xFC00 |
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43 | |
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44 | ///////////////////////////////////////////////////////////////////////////////////////// |
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45 | // This structure defines the cpu_context for TSAR MIPS32. |
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46 | // These registers are saved/restored at each context switch. |
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47 | // WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore() |
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48 | // functions when modifying this structure. |
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49 | ///////////////////////////////////////////////////////////////////////////////////////// |
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50 | |
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51 | typedef struct hal_cpu_context_s |
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52 | { |
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53 | uint32_t s0_16; // slot 0 |
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54 | uint32_t s1_17; // slot 1 |
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55 | uint32_t s2_18; // slot 2 |
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56 | uint32_t s3_19; // slot 3 |
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57 | uint32_t s4_20; // slot 4 |
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58 | uint32_t s5_21; // slot 5 |
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59 | uint32_t s6_22; // slot 6 |
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60 | uint32_t s7_23; // slot 7 |
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61 | uint32_t sp_29; // slot 8 |
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62 | uint32_t fp_30; // slot 9 |
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63 | uint32_t ra_31; // slot 10 |
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64 | uint32_t c0_sr; // slot 11 |
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65 | uint32_t c0_th; // slot 12 |
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66 | uint32_t c2_ptpr; // slot 13 |
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67 | uint32_t c2_mode; // slot 14 |
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68 | } |
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69 | hal_cpu_context_t; |
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70 | |
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71 | ///////////////////////////////////////////////////////////////////////////////////////// |
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72 | // This structure defines the fpu_context for TSAR MIPS32. |
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73 | ///////////////////////////////////////////////////////////////////////////////////////// |
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74 | |
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75 | typedef struct hal_fpu_context_s |
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76 | { |
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77 | uint32_t fpu_regs[32]; |
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78 | } |
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79 | hal_fpu_context_t; |
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80 | |
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81 | ////////////////////////////////////////////////////////// |
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82 | error_t hal_cpu_context_create( struct thread_s * thread ) |
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83 | { |
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84 | kmem_req_t req; |
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85 | |
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86 | context_dmsg("\n[INFO] %s : enters for thread %x in process %x\n", |
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87 | __FUNCTION__ , thread->trdid , thread->process->pid ); |
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88 | |
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89 | // allocate memory for cpu_context |
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90 | req.type = KMEM_CPU_CTX; |
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91 | req.size = sizeof(hal_cpu_context_t); |
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92 | req.flags = AF_KERNEL | AF_ZERO; |
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93 | |
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94 | hal_cpu_context_t * context = (hal_cpu_context_t *)kmem_alloc( &req ); |
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95 | if( context == NULL ) return ENOMEM; |
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96 | |
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97 | // set cpu context pointer in thread |
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98 | thread->cpu_context = (void*)context; |
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99 | |
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100 | // stack pointer, status register and mmu_mode depends on thread type |
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101 | uint32_t sp_29; |
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102 | uint32_t c0_sr; |
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103 | uint32_t c2_mode; |
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104 | if( thread->type == THREAD_USER ) |
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105 | { |
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106 | sp_29 = ((uint32_t)thread->u_stack_base) + thread->u_stack_size; |
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107 | c0_sr = SR_USR_MODE; |
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108 | c2_mode = 0xF; |
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109 | } |
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110 | else |
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111 | { |
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112 | sp_29 = ((uint32_t)thread->k_stack_base) + thread->k_stack_size; |
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113 | c0_sr = SR_SYS_MODE; |
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114 | c2_mode = 0x3; |
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115 | } |
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116 | |
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117 | // align stack pointer on a double word boundary |
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118 | sp_29 = (sp_29 - 8) & (~ 0x7); |
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119 | |
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120 | // initialise context |
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121 | context->sp_29 = sp_29; |
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122 | context->fp_30 = sp_29; // TODO check this [AG] |
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123 | context->ra_31 = (uint32_t)thread->entry_func; |
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124 | context->c0_sr = c0_sr; |
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125 | context->c0_th = (uint32_t)thread; |
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126 | context->c2_ptpr = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1); |
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127 | context->c2_mode = c2_mode; |
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128 | |
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129 | context_dmsg("\n[INFO] %s : exit for thread %x in process %x\n", |
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130 | __FUNCTION__ , thread->trdid , thread->process->pid ); |
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131 | |
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132 | return 0; |
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133 | } // end hal_cpu_context_create() |
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134 | |
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135 | ///////////////////////////////////////////// |
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136 | error_t hal_cpu_context_copy( thread_t * dst, |
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137 | thread_t * src ) |
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138 | { |
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139 | kmem_req_t req; |
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140 | |
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141 | // allocate memory for dst cpu_context |
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142 | req.type = KMEM_CPU_CTX; |
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143 | req.size = sizeof(hal_cpu_context_t); |
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144 | req.flags = AF_KERNEL | AF_ZERO; |
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145 | |
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146 | hal_cpu_context_t * dst_context = (hal_cpu_context_t *)kmem_alloc( &req ); |
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147 | if( dst_context == NULL ) return ENOMEM; |
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148 | |
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149 | // set cpu context pointer in dst thread |
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150 | dst->cpu_context = dst_context; |
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151 | |
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152 | // get cpu context pointer from src thread |
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153 | hal_cpu_context_t * src_context = src->cpu_context; |
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154 | |
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155 | // copy CPU context from src to dst |
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156 | memcpy( dst_context , src_context , sizeof(hal_cpu_context_t) ); |
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157 | |
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158 | return 0; |
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159 | } // end hal_cpu_context_copy() |
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160 | |
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161 | ///////////////////////////////////////////////// |
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162 | void hal_cpu_context_destroy( thread_t * thread ) |
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163 | { |
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164 | kmem_req_t req; |
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165 | |
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166 | req.type = KMEM_CPU_CTX; |
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167 | req.ptr = thread->cpu_context; |
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168 | kmem_free( &req ); |
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169 | |
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170 | } // end hal_cpu_context_destroy() |
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171 | |
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172 | /////////////////////////////////////////////////// |
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173 | error_t hal_fpu_context_create( thread_t * thread ) |
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174 | { |
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175 | kmem_req_t req; |
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176 | |
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177 | // allocate memory for uzone |
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178 | req.type = KMEM_FPU_CTX; |
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179 | req.size = sizeof(hal_fpu_context_t); |
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180 | req.flags = AF_KERNEL | AF_ZERO; |
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181 | |
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182 | hal_fpu_context_t * context = (hal_fpu_context_t *)kmem_alloc( &req ); |
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183 | if( context == NULL ) return ENOMEM; |
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184 | |
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185 | // set fpu context pointer in thread |
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186 | thread->fpu_context = (void*)context; |
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187 | |
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188 | return 0; |
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189 | } // hal_fpu_context_create() |
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190 | |
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191 | ///////////////////////////////////////////// |
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192 | error_t hal_fpu_context_copy( thread_t * dst, |
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193 | thread_t * src ) |
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194 | { |
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195 | kmem_req_t req; |
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196 | |
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197 | // allocate memory for dst fpu_context |
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198 | req.type = KMEM_FPU_CTX; |
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199 | req.size = sizeof(hal_fpu_context_t); |
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200 | req.flags = AF_KERNEL | AF_ZERO; |
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201 | |
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202 | hal_fpu_context_t * dst_context = (hal_fpu_context_t *)kmem_alloc( &req ); |
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203 | if( dst_context == NULL ) return ENOMEM; |
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204 | |
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205 | // set fpu context pointer in dst thread |
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206 | dst->fpu_context = (void*)dst_context; |
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207 | |
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208 | // get fpu context pointer from src thread |
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209 | hal_fpu_context_t * src_context = src->fpu_context; |
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210 | |
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211 | // copy CPU context from src to dst |
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212 | memcpy( dst_context , src_context , sizeof(hal_fpu_context_t) ); |
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213 | |
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214 | return 0; |
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215 | } // end hal_fpu_context_copy() |
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216 | |
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217 | ///////////////////////////////////////////////// |
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218 | void hal_fpu_context_destroy( thread_t * thread ) |
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219 | { |
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220 | kmem_req_t req; |
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221 | |
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222 | req.type = KMEM_FPU_CTX; |
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223 | req.ptr = thread->fpu_context; |
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224 | kmem_free( &req ); |
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225 | |
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226 | } // end hal_fpu_context_destroy() |
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227 | |
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228 | ////////////////////////////////////////////// |
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229 | void hal_cpu_context_save( thread_t * thread ) |
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230 | { |
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231 | uint32_t ctx = (uint32_t)thread->cpu_context; |
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232 | |
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233 | asm volatile( |
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234 | ".set noreorder \n" |
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235 | "sw $16, 0*4(%0) \n" /* save s0 to slot 0 */ |
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236 | "sw $17, 1*4(%0) \n" /* save s1 to slot 1 */ |
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237 | "sw $18, 2*4(%0) \n" /* save s2 to slot 2 */ |
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238 | "sw $19, 3*4(%0) \n" /* save s3 to slot 3 */ |
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239 | "sw $20, 4*4(%0) \n" /* save s4 to slot 4 */ |
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240 | "sw $21, 5*4(%0) \n" /* save s5 to slot 5 */ |
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241 | "sw $22, 6*4(%0) \n" /* save s6 to slot 6 */ |
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242 | "sw $23, 7*4(%0) \n" /* save s7 to slot 7 */ |
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243 | "sw $29, 8*4(%0) \n" /* save sp to slot 8 */ |
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244 | "sw $30, 9*4(%0) \n" /* save fp to slot 9 */ |
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245 | "sw $31, 10*4(%0) \n" /* save ra to slot 10 */ |
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246 | "mfc0 $26, $4, 2 \n" /* get c0_th from CP0 */ |
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247 | "sw $26, 12*4(%0) \n" /* save c0_th to slot 12 */ |
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248 | "mfc2 $26, $0 \n" /* get c2_ptpr from CP2 */ |
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249 | "sw $26, 13*4(%0) \n" /* save c2_ptpr to slot 13 */ |
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250 | "mfc2 $26, $1 \n" /* get c2_mod from CP2 */ |
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251 | "sw $26, 14*4(%0) \n" /* save c2_mode to slot 14 */ |
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252 | "sync \n" |
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253 | ".set reorder \n" |
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254 | : : "r"( ctx ) : "$26" , "memory" ); |
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255 | } |
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256 | |
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257 | ///////////////////////////////////////////////// |
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258 | void hal_cpu_context_restore( thread_t * thread ) |
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259 | { |
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260 | uint32_t ctx = (uint32_t)thread->cpu_context; |
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261 | |
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262 | asm volatile( |
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263 | ".set noreorder \n" |
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264 | "nop \n" |
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265 | "lw $16, 0*4(%0) \n" /* restore s0_16 */ |
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266 | "lw $17, 1*4(%0) \n" /* restore s1_17 */ |
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267 | "lw $18, 2*4(%0) \n" /* restore s2_18 */ |
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268 | "lw $19, 3*4(%0) \n" /* restore s3_19 */ |
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269 | "lw $20, 4*4(%0) \n" /* restore s4_20 */ |
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270 | "lw $21, 5*4(%0) \n" /* restore s5_21 */ |
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271 | "lw $22, 6*4(%0) \n" /* restore s6_22 */ |
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272 | "lw $23, 7*4(%0) \n" /* restore s7_23 */ |
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273 | "lw $29, 8*4(%0) \n" /* restore sp_29 */ |
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274 | "lw $30, 9*4(%0) \n" /* restore fp_30 */ |
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275 | "lw $31, 10*4(%0) \n" /* restore ra_31 */ |
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276 | "lw $26, 12*4(%0) \n" /* get c0_th from slot 12 */ |
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277 | "mtc0 $26, $4, 2 \n" /* restore c0_th */ |
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278 | "lw $26, 13*4(%0) \n" /* get c2_ptpr from slot 13 */ |
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279 | "mtc2 $26, $0 \n" /* restore c2_ptpr */ |
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280 | "lw $26, 14*4(%0) \n" /* get c2_mode from slot 14 */ |
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281 | "mtc2 $26, $1 \n" /* restore c2_mode */ |
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282 | ".set reorder \n" |
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283 | : : "r"(ctx) |
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284 | : "$16","$17","$18","$19","$20","$21","$22","$23","$26","$29","$30","$31" ); |
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285 | } |
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286 | |
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287 | ////////////////////////////////////////////// |
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288 | void hal_cpu_context_load( thread_t * thread ) |
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289 | { |
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290 | // get relevant values from thread context |
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291 | hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; |
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292 | uint32_t sp_29 = ctx->sp_29; |
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293 | uint32_t fp_30 = ctx->fp_30; |
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294 | uint32_t c0_th = ctx->c0_th; |
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295 | uint32_t c0_sr = ctx->c0_sr; |
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296 | uint32_t c2_ptpr = ctx->c2_ptpr; |
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297 | uint32_t c2_mode = ctx->c2_mode; |
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298 | |
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299 | // get pointer on entry function & argument from thread attributes |
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300 | uint32_t func = (uint32_t)thread->entry_func; |
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301 | uint32_t args = (uint32_t)thread->entry_args; |
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302 | |
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303 | // reset loadable field in thread descriptor |
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304 | thread->flags &= ~THREAD_FLAG_LOADABLE; |
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305 | |
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306 | // load registers |
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307 | asm volatile( |
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308 | ".set noreorder \n" |
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309 | "or $26, %0, $0 \n" /* $26 <= stack pointer */ |
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310 | "or $27, %2, $0 \n" /* $27 <= status register */ |
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311 | "addiu $26, $26, -4 \n" /* decrement stack pointer */ |
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312 | "or $4, %7, $0 \n" /* load a0 */ |
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313 | "sw $4, ($26) \n" /* set entry_args in stack */ |
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314 | "ori $27, $27, 0x2 \n" /* set EXL flag in status register */ |
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315 | "mtc0 $27, $12 \n" /* load c0_sr */ |
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316 | "mtc0 %3, $4, 2 \n" /* load c0_th */ |
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317 | "mtc2 %4, $0 \n" /* load c2 ptpr */ |
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318 | "mtc0 %6, $14 \n" /* load c0_epc */ |
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319 | "or $29, $16, $0 \n" /* load sp_29 */ |
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320 | "or $30, %1, $0 \n" /* load fp_30 */ |
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321 | "mtc2 %5, $1 \n" /* load c2_mode */ |
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322 | "nop \n" |
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323 | "eret \n" /* jump to user code */ |
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324 | "nop \n" |
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325 | ".set reorder \n" |
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326 | : |
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327 | : "r"(sp_29),"r"(fp_30),"r"(c0_sr),"r"(c0_th), |
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328 | "r"(c2_ptpr),"r"(c2_mode),"r"(func),"r"(args) |
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329 | : "$4","$26","$27","$29","$30" ); |
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330 | |
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331 | } // end hal_cpu_context_load() |
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332 | |
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333 | |
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334 | ////////////////////////////////////////////// |
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335 | void hal_fpu_context_save( thread_t * thread ) |
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336 | { |
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337 | uint32_t ctx = (uint32_t)thread->fpu_context; |
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338 | |
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339 | asm volatile( |
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340 | ".set noreorder \n" |
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341 | "swc1 $f0, 0*4(%0) \n" |
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342 | "swc1 $f1, 1*4(%0) \n" |
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343 | "swc1 $f2, 2*4(%0) \n" |
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344 | "swc1 $f3, 3*4(%0) \n" |
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345 | "swc1 $f4, 4*4(%0) \n" |
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346 | "swc1 $f5, 5*4(%0) \n" |
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347 | "swc1 $f6, 6*4(%0) \n" |
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348 | "swc1 $f7, 7*4(%0) \n" |
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349 | "swc1 $f8, 8*4(%0) \n" |
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350 | "swc1 $f9, 9*4(%0) \n" |
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351 | "swc1 $f10, 10*4(%0) \n" |
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352 | "swc1 $f11, 11*4(%0) \n" |
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353 | "swc1 $f12, 12*4(%0) \n" |
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354 | "swc1 $f13, 13*4(%0) \n" |
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355 | "swc1 $f14, 14*4(%0) \n" |
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356 | "swc1 $f15, 15*4(%0) \n" |
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357 | "swc1 $f16, 16*4(%0) \n" |
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358 | "swc1 $f17, 17*4(%0) \n" |
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359 | "swc1 $f18, 18*4(%0) \n" |
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360 | "swc1 $f19, 19*4(%0) \n" |
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361 | "swc1 $f20, 20*4(%0) \n" |
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362 | "swc1 $f21, 21*4(%0) \n" |
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363 | "swc1 $f22, 22*4(%0) \n" |
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364 | "swc1 $f23, 23*4(%0) \n" |
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365 | "swc1 $f24, 24*4(%0) \n" |
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366 | "swc1 $f25, 25*4(%0) \n" |
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367 | "swc1 $f26, 26*4(%0) \n" |
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368 | "swc1 $f27, 27*4(%0) \n" |
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369 | "swc1 $f28, 28*4(%0) \n" |
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370 | "swc1 $f29, 29*4(%0) \n" |
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371 | "swc1 $f30, 30*4(%0) \n" |
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372 | "swc1 $f31, 31*4(%0) \n" |
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373 | ".set reorder \n" |
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374 | : : "r"(ctx) ); |
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375 | |
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376 | } // end hal_cpu_context_save() |
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377 | |
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378 | ///////////////////////////////////////////////// |
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379 | void hal_fpu_context_restore( thread_t * thread ) |
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380 | { |
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381 | uint32_t ctx = (uint32_t)thread->fpu_context; |
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382 | |
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383 | asm volatile( |
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384 | ".set noreorder \n" |
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385 | "lwc1 $f0, 0*4(%0) \n" |
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386 | "lwc1 $f1, 1*4(%0) \n" |
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387 | "lwc1 $f2, 2*4(%0) \n" |
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388 | "lwc1 $f3, 3*4(%0) \n" |
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389 | "lwc1 $f4, 4*4(%0) \n" |
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390 | "lwc1 $f5, 5*4(%0) \n" |
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391 | "lwc1 $f6, 6*4(%0) \n" |
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392 | "lwc1 $f7, 7*4(%0) \n" |
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393 | "lwc1 $f8, 8*4(%0) \n" |
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394 | "lwc1 $f9, 9*4(%0) \n" |
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395 | "lwc1 $f10, 10*4(%0) \n" |
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396 | "lwc1 $f11, 11*4(%0) \n" |
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397 | "lwc1 $f12, 12*4(%0) \n" |
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398 | "lwc1 $f13, 13*4(%0) \n" |
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399 | "lwc1 $f14, 14*4(%0) \n" |
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400 | "lwc1 $f15, 15*4(%0) \n" |
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401 | "lwc1 $f16, 16*4(%0) \n" |
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402 | "lwc1 $f17, 17*4(%0) \n" |
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403 | "lwc1 $f18, 18*4(%0) \n" |
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404 | "lwc1 $f19, 19*4(%0) \n" |
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405 | "lwc1 $f20, 20*4(%0) \n" |
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406 | "lwc1 $f21, 21*4(%0) \n" |
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407 | "lwc1 $f22, 22*4(%0) \n" |
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408 | "lwc1 $f23, 23*4(%0) \n" |
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409 | "lwc1 $f24, 24*4(%0) \n" |
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410 | "lwc1 $f25, 25*4(%0) \n" |
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411 | "lwc1 $f26, 26*4(%0) \n" |
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412 | "lwc1 $f27, 27*4(%0) \n" |
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413 | "lwc1 $f28, 28*4(%0) \n" |
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414 | "lwc1 $f29, 29*4(%0) \n" |
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415 | "lwc1 $f30, 30*4(%0) \n" |
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416 | "lwc1 $f31, 31*4(%0) \n" |
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417 | ".set reorder \n" |
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418 | : : "r"(ctx) ); |
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419 | |
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420 | } // end hal_cpu_context_restore() |
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421 | |
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422 | ///////////////////////////////////// |
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423 | void hal_fpu_context_dup( xptr_t dst, |
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424 | xptr_t src ) |
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425 | { |
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426 | hal_remote_memcpy( dst , src , sizeof(hal_fpu_context_t) ); |
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427 | } |
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428 | |
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