1 | /* |
---|
2 | * hal_context.c - implementation of Thread Context API for TSAR-MIPS32 |
---|
3 | * |
---|
4 | * Author Alain Greiner (2016) |
---|
5 | * |
---|
6 | * Copyright (c) UPMC Sorbonne Universites |
---|
7 | * |
---|
8 | * This file is part of ALMOS-MKH. |
---|
9 | * |
---|
10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
---|
11 | * under the terms of the GNU General Public License as published by |
---|
12 | * the Free Software Foundation; version 2.0 of the License. |
---|
13 | * |
---|
14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
---|
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
17 | * General Public License for more details. |
---|
18 | * |
---|
19 | * You should have received a copy of the GNU General Public License |
---|
20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
---|
21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
---|
22 | */ |
---|
23 | |
---|
24 | #include <hal_types.h> |
---|
25 | #include <hal_switch.h> |
---|
26 | #include <memcpy.h> |
---|
27 | #include <thread.h> |
---|
28 | #include <string.h> |
---|
29 | #include <process.h> |
---|
30 | #include <printk.h> |
---|
31 | #include <vmm.h> |
---|
32 | #include <core.h> |
---|
33 | #include <cluster.h> |
---|
34 | #include <hal_context.h> |
---|
35 | #include <hal_kentry.h> |
---|
36 | |
---|
37 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
38 | // Define various SR values for TSAR-MIPS32 |
---|
39 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
40 | |
---|
41 | #define SR_USR_MODE 0x0000FC13 |
---|
42 | #define SR_USR_MODE_FPU 0x2000FC13 |
---|
43 | #define SR_SYS_MODE 0x0000FC00 |
---|
44 | |
---|
45 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
46 | // This structuree defines the cpu_context for TSAR MIPS32. |
---|
47 | // These registers are saved/restored at each context switch. |
---|
48 | // WARNING : check the two CONFIG_CPU_CTX_SIZE & CONFIG_FPU_CTX_SIZE configuration |
---|
49 | // parameterss when modifying this structure. |
---|
50 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
51 | |
---|
52 | typedef struct hal_cpu_context_s |
---|
53 | { |
---|
54 | uint32_t c0_epc; // slot 0 |
---|
55 | uint32_t at_01; // slot 1 |
---|
56 | uint32_t v0_02; // slot 2 |
---|
57 | uint32_t v1_03; // slot 3 |
---|
58 | uint32_t a0_04; // slot 4 |
---|
59 | uint32_t a1_05; // slot 5 |
---|
60 | uint32_t a2_06; // slot 6 |
---|
61 | uint32_t a3_07; // slot 7 |
---|
62 | |
---|
63 | uint32_t t0_08; // slot 8 |
---|
64 | uint32_t t1_09; // slot 9 |
---|
65 | uint32_t t2_10; // slot 10 |
---|
66 | uint32_t t3_11; // slot 11 |
---|
67 | uint32_t t4_12; // slot 12 |
---|
68 | uint32_t t5_13; // slot 13 |
---|
69 | uint32_t t6_14; // slot 14 |
---|
70 | uint32_t t7_15; // slot 15 |
---|
71 | |
---|
72 | uint32_t s0_16; // slot 16 |
---|
73 | uint32_t s1_17; // slot 17 |
---|
74 | uint32_t s2_18; // slot 18 |
---|
75 | uint32_t s3_19; // slot 19 |
---|
76 | uint32_t s4_20; // slot 20 |
---|
77 | uint32_t s5_21; // slot 21 |
---|
78 | uint32_t s6_22; // slot 22 |
---|
79 | uint32_t s7_23; // slot 23 |
---|
80 | |
---|
81 | uint32_t t8_24; // slot 24 |
---|
82 | uint32_t t9_25; // slot 25 |
---|
83 | uint32_t hi_26; // slot 26 |
---|
84 | uint32_t lo_27; // slot 27 |
---|
85 | uint32_t gp_28; // slot 28 |
---|
86 | uint32_t sp_29; // slot 29 |
---|
87 | uint32_t fp_30; // slot 30 |
---|
88 | uint32_t ra_31; // slot 31 |
---|
89 | |
---|
90 | uint32_t c2_ptpr; // slot 32 |
---|
91 | uint32_t c2_mode; // slot 33 |
---|
92 | |
---|
93 | uint32_t c0_sr; // slot 34 |
---|
94 | uint32_t c0_th; // slot 35 |
---|
95 | } |
---|
96 | hal_cpu_context_t; |
---|
97 | |
---|
98 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
99 | // This structure defines the fpu_context for TSAR MIPS32. |
---|
100 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
101 | |
---|
102 | typedef struct hal_fpu_context_s |
---|
103 | { |
---|
104 | uint32_t fpu_regs[32]; |
---|
105 | } |
---|
106 | hal_fpu_context_t; |
---|
107 | |
---|
108 | |
---|
109 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
110 | // CPU context access functions |
---|
111 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
112 | |
---|
113 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
114 | // This function allocates and initializes the cpu_context stucture in thread descriptor. |
---|
115 | // The following context slots are initialised by this function: |
---|
116 | // GPR : a0_04 / sp_29 / fp_30 / ra_31 |
---|
117 | // CP0 : c0_sr / c0_th / c0_epc |
---|
118 | // CP2 : c2_ptpr / c2_mode |
---|
119 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
120 | error_t hal_cpu_context_create( thread_t * thread ) |
---|
121 | { |
---|
122 | kmem_req_t req; |
---|
123 | |
---|
124 | assert( (sizeof(hal_cpu_context_t) <= CONFIG_CPU_CTX_SIZE) , __FUNCTION__ , |
---|
125 | "inconsistent CPU context size" ); |
---|
126 | |
---|
127 | context_dmsg("\n[DMSG] %s : enters for thread %x in process %x\n", |
---|
128 | __FUNCTION__ , thread->trdid , thread->process->pid ); |
---|
129 | |
---|
130 | // allocate memory for cpu_context |
---|
131 | req.type = KMEM_CPU_CTX; |
---|
132 | req.flags = AF_KERNEL | AF_ZERO; |
---|
133 | |
---|
134 | hal_cpu_context_t * context = (hal_cpu_context_t *)kmem_alloc( &req ); |
---|
135 | if( context == NULL ) return ENOMEM; |
---|
136 | |
---|
137 | // set cpu context pointer in thread |
---|
138 | thread->cpu_context = (void*)context; |
---|
139 | |
---|
140 | // stack pointer, status register and mmu_mode depends on thread type |
---|
141 | uint32_t sp_29; |
---|
142 | uint32_t c0_sr; |
---|
143 | uint32_t c2_mode; |
---|
144 | if( thread->type == THREAD_USER ) |
---|
145 | { |
---|
146 | sp_29 = ((uint32_t)thread->u_stack_base) + thread->u_stack_size; |
---|
147 | c0_sr = SR_USR_MODE; |
---|
148 | c2_mode = 0xF; |
---|
149 | } |
---|
150 | else |
---|
151 | { |
---|
152 | sp_29 = ((uint32_t)thread->k_stack_base) + thread->k_stack_size; |
---|
153 | c0_sr = SR_SYS_MODE; |
---|
154 | c2_mode = 0x3; |
---|
155 | } |
---|
156 | |
---|
157 | // align stack pointer on a double word boundary |
---|
158 | sp_29 = (sp_29 - 8) & (~ 0x7); |
---|
159 | |
---|
160 | // initialise context |
---|
161 | context->a0_04 = (uint32_t)thread->entry_args; |
---|
162 | context->sp_29 = sp_29; |
---|
163 | context->fp_30 = sp_29; // TODO check this [AG] |
---|
164 | context->ra_31 = (uint32_t)&hal_kentry_eret; |
---|
165 | context->c0_epc = (uint32_t)thread->entry_func; |
---|
166 | context->c0_sr = c0_sr; |
---|
167 | context->c0_th = (uint32_t)thread; |
---|
168 | context->c2_ptpr = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1); |
---|
169 | context->c2_mode = c2_mode; |
---|
170 | |
---|
171 | context_dmsg("\n[DMSG] %s : exit for thread %x in process %x\n" |
---|
172 | " - a0 = %x\n" |
---|
173 | " - sp = %x\n" |
---|
174 | " - fp = %x\n" |
---|
175 | " - ra = %x\n" |
---|
176 | " - sr = %x\n" |
---|
177 | " - th = %x\n" |
---|
178 | " - epc = %x\n" |
---|
179 | " - ptpr = %x\n" |
---|
180 | " - mode = %x\n", |
---|
181 | __FUNCTION__ , thread->trdid , thread->process->pid, |
---|
182 | context->a0_04, context->sp_29, context->fp_30, context->ra_31, |
---|
183 | context->c0_sr, context->c0_th, context->c0_epc, |
---|
184 | context->c2_ptpr, context->c2_mode ); |
---|
185 | return 0; |
---|
186 | |
---|
187 | } // end hal_cpu_context_create() |
---|
188 | |
---|
189 | ///////////////////////////////////////////////// |
---|
190 | void hal_cpu_context_display( thread_t * thread ) |
---|
191 | { |
---|
192 | hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; |
---|
193 | |
---|
194 | printk("\n***** CPU context for thread %x in process %x / cycle %d\n" |
---|
195 | " gp_28 = %X sp_29 = %X ra_31 = %X\n" |
---|
196 | " c0_sr = %X c0_epc = %X c0_th = %X\n" |
---|
197 | " c2_ptpr = %X c2_mode = %X\n", |
---|
198 | thread->trdid, thread->process->pid, hal_time_stamp(), |
---|
199 | ctx->gp_28 , ctx->sp_29 , ctx->ra_31, |
---|
200 | ctx->c0_sr , ctx->c0_epc , ctx->c0_th, |
---|
201 | ctx->c2_ptpr , ctx->c2_mode ); |
---|
202 | |
---|
203 | } // end hal_context_display() |
---|
204 | |
---|
205 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
206 | // These registers are saved/restored to/from CPU context defined by <ctx> argument. |
---|
207 | // - GPR : all, but (zero, k0, k1), plus (hi, lo) |
---|
208 | // - CP0 : c0_th , c0_sr , C0_epc |
---|
209 | // - CP2 : c2_ptpr , C2_mode |
---|
210 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
211 | // old_thread : pointer on current thread descriptor |
---|
212 | // new_thread : pointer on new thread descriptor |
---|
213 | ///////////////////////////////////////////////////////////////////////////////////////// |
---|
214 | void hal_cpu_context_switch( thread_t * old_thread, |
---|
215 | thread_t * new_thread ) |
---|
216 | { |
---|
217 | hal_cpu_context_t * ctx_old = old_thread->cpu_context; |
---|
218 | hal_cpu_context_t * ctx_new = new_thread->cpu_context; |
---|
219 | |
---|
220 | #if CONFIG_CONTEXT_DEBUG |
---|
221 | hal_cpu_context_display( old_thread ); |
---|
222 | hal_cpu_context_display( new_thread ); |
---|
223 | #endif |
---|
224 | |
---|
225 | // reset loadable field in new thread descriptor |
---|
226 | new_thread->flags &= ~THREAD_FLAG_LOADABLE; |
---|
227 | |
---|
228 | hal_do_switch( ctx_old , ctx_new ); |
---|
229 | } |
---|
230 | |
---|
231 | ///////////////////////////////////////////// |
---|
232 | error_t hal_cpu_context_copy( thread_t * dst, |
---|
233 | thread_t * src ) |
---|
234 | { |
---|
235 | kmem_req_t req; |
---|
236 | |
---|
237 | // allocate memory for dst cpu_context |
---|
238 | req.type = KMEM_CPU_CTX; |
---|
239 | req.size = sizeof(hal_cpu_context_t); |
---|
240 | req.flags = AF_KERNEL | AF_ZERO; |
---|
241 | |
---|
242 | hal_cpu_context_t * dst_context = (hal_cpu_context_t *)kmem_alloc( &req ); |
---|
243 | if( dst_context == NULL ) return ENOMEM; |
---|
244 | |
---|
245 | // set cpu context pointer in dst thread |
---|
246 | dst->cpu_context = dst_context; |
---|
247 | |
---|
248 | // get cpu context pointer from src thread |
---|
249 | hal_cpu_context_t * src_context = src->cpu_context; |
---|
250 | |
---|
251 | // copy CPU context from src to dst |
---|
252 | memcpy( dst_context , src_context , sizeof(hal_cpu_context_t) ); |
---|
253 | |
---|
254 | return 0; |
---|
255 | |
---|
256 | } // end hal_cpu_context_copy() |
---|
257 | |
---|
258 | ///////////////////////////////////////////////// |
---|
259 | void hal_cpu_context_destroy( thread_t * thread ) |
---|
260 | { |
---|
261 | kmem_req_t req; |
---|
262 | |
---|
263 | req.type = KMEM_CPU_CTX; |
---|
264 | req.ptr = thread->cpu_context; |
---|
265 | kmem_free( &req ); |
---|
266 | |
---|
267 | } // end hal_cpu_context_destroy() |
---|
268 | |
---|
269 | |
---|
270 | /////////////////////////////////////////////////// |
---|
271 | error_t hal_fpu_context_create( thread_t * thread ) |
---|
272 | { |
---|
273 | kmem_req_t req; |
---|
274 | |
---|
275 | assert( (sizeof(hal_fpu_context_t) <= CONFIG_FPU_CTX_SIZE) , __FUNCTION__ , |
---|
276 | "inconsistent FPU context size" ); |
---|
277 | |
---|
278 | // allocate memory for uzone |
---|
279 | req.type = KMEM_FPU_CTX; |
---|
280 | req.flags = AF_KERNEL | AF_ZERO; |
---|
281 | |
---|
282 | hal_fpu_context_t * context = (hal_fpu_context_t *)kmem_alloc( &req ); |
---|
283 | if( context == NULL ) return ENOMEM; |
---|
284 | |
---|
285 | // set fpu context pointer in thread |
---|
286 | thread->fpu_context = (void*)context; |
---|
287 | |
---|
288 | return 0; |
---|
289 | } // hal_fpu_context_create() |
---|
290 | |
---|
291 | ///////////////////////////////////////////// |
---|
292 | error_t hal_fpu_context_copy( thread_t * dst, |
---|
293 | thread_t * src ) |
---|
294 | { |
---|
295 | kmem_req_t req; |
---|
296 | |
---|
297 | // allocate memory for dst fpu_context |
---|
298 | req.type = KMEM_FPU_CTX; |
---|
299 | req.flags = AF_KERNEL | AF_ZERO; |
---|
300 | |
---|
301 | hal_fpu_context_t * dst_context = (hal_fpu_context_t *)kmem_alloc( &req ); |
---|
302 | if( dst_context == NULL ) return ENOMEM; |
---|
303 | |
---|
304 | // set fpu context pointer in dst thread |
---|
305 | dst->fpu_context = (void*)dst_context; |
---|
306 | |
---|
307 | // get fpu context pointer from src thread |
---|
308 | hal_fpu_context_t * src_context = src->fpu_context; |
---|
309 | |
---|
310 | // copy CPU context from src to dst |
---|
311 | memcpy( dst_context , src_context , sizeof(hal_fpu_context_t) ); |
---|
312 | |
---|
313 | return 0; |
---|
314 | } // end hal_fpu_context_copy() |
---|
315 | |
---|
316 | ///////////////////////////////////////////////// |
---|
317 | void hal_fpu_context_destroy( thread_t * thread ) |
---|
318 | { |
---|
319 | kmem_req_t req; |
---|
320 | |
---|
321 | req.type = KMEM_FPU_CTX; |
---|
322 | req.ptr = thread->fpu_context; |
---|
323 | kmem_free( &req ); |
---|
324 | |
---|
325 | } // end hal_fpu_context_destroy() |
---|
326 | |
---|
327 | ////////////////////////////////////////////// |
---|
328 | void hal_fpu_context_save( thread_t * thread ) |
---|
329 | { |
---|
330 | uint32_t ctx = (uint32_t)thread->fpu_context; |
---|
331 | |
---|
332 | asm volatile( |
---|
333 | ".set noreorder \n" |
---|
334 | "swc1 $f0, 0*4(%0) \n" |
---|
335 | "swc1 $f1, 1*4(%0) \n" |
---|
336 | "swc1 $f2, 2*4(%0) \n" |
---|
337 | "swc1 $f3, 3*4(%0) \n" |
---|
338 | "swc1 $f4, 4*4(%0) \n" |
---|
339 | "swc1 $f5, 5*4(%0) \n" |
---|
340 | "swc1 $f6, 6*4(%0) \n" |
---|
341 | "swc1 $f7, 7*4(%0) \n" |
---|
342 | "swc1 $f8, 8*4(%0) \n" |
---|
343 | "swc1 $f9, 9*4(%0) \n" |
---|
344 | "swc1 $f10, 10*4(%0) \n" |
---|
345 | "swc1 $f11, 11*4(%0) \n" |
---|
346 | "swc1 $f12, 12*4(%0) \n" |
---|
347 | "swc1 $f13, 13*4(%0) \n" |
---|
348 | "swc1 $f14, 14*4(%0) \n" |
---|
349 | "swc1 $f15, 15*4(%0) \n" |
---|
350 | "swc1 $f16, 16*4(%0) \n" |
---|
351 | "swc1 $f17, 17*4(%0) \n" |
---|
352 | "swc1 $f18, 18*4(%0) \n" |
---|
353 | "swc1 $f19, 19*4(%0) \n" |
---|
354 | "swc1 $f20, 20*4(%0) \n" |
---|
355 | "swc1 $f21, 21*4(%0) \n" |
---|
356 | "swc1 $f22, 22*4(%0) \n" |
---|
357 | "swc1 $f23, 23*4(%0) \n" |
---|
358 | "swc1 $f24, 24*4(%0) \n" |
---|
359 | "swc1 $f25, 25*4(%0) \n" |
---|
360 | "swc1 $f26, 26*4(%0) \n" |
---|
361 | "swc1 $f27, 27*4(%0) \n" |
---|
362 | "swc1 $f28, 28*4(%0) \n" |
---|
363 | "swc1 $f29, 29*4(%0) \n" |
---|
364 | "swc1 $f30, 30*4(%0) \n" |
---|
365 | "swc1 $f31, 31*4(%0) \n" |
---|
366 | ".set reorder \n" |
---|
367 | : : "r"(ctx) ); |
---|
368 | |
---|
369 | } // end hal_cpu_context_save() |
---|
370 | |
---|
371 | ///////////////////////////////////////////////// |
---|
372 | void hal_fpu_context_restore( thread_t * thread ) |
---|
373 | { |
---|
374 | uint32_t ctx = (uint32_t)thread->fpu_context; |
---|
375 | |
---|
376 | asm volatile( |
---|
377 | ".set noreorder \n" |
---|
378 | "lwc1 $f0, 0*4(%0) \n" |
---|
379 | "lwc1 $f1, 1*4(%0) \n" |
---|
380 | "lwc1 $f2, 2*4(%0) \n" |
---|
381 | "lwc1 $f3, 3*4(%0) \n" |
---|
382 | "lwc1 $f4, 4*4(%0) \n" |
---|
383 | "lwc1 $f5, 5*4(%0) \n" |
---|
384 | "lwc1 $f6, 6*4(%0) \n" |
---|
385 | "lwc1 $f7, 7*4(%0) \n" |
---|
386 | "lwc1 $f8, 8*4(%0) \n" |
---|
387 | "lwc1 $f9, 9*4(%0) \n" |
---|
388 | "lwc1 $f10, 10*4(%0) \n" |
---|
389 | "lwc1 $f11, 11*4(%0) \n" |
---|
390 | "lwc1 $f12, 12*4(%0) \n" |
---|
391 | "lwc1 $f13, 13*4(%0) \n" |
---|
392 | "lwc1 $f14, 14*4(%0) \n" |
---|
393 | "lwc1 $f15, 15*4(%0) \n" |
---|
394 | "lwc1 $f16, 16*4(%0) \n" |
---|
395 | "lwc1 $f17, 17*4(%0) \n" |
---|
396 | "lwc1 $f18, 18*4(%0) \n" |
---|
397 | "lwc1 $f19, 19*4(%0) \n" |
---|
398 | "lwc1 $f20, 20*4(%0) \n" |
---|
399 | "lwc1 $f21, 21*4(%0) \n" |
---|
400 | "lwc1 $f22, 22*4(%0) \n" |
---|
401 | "lwc1 $f23, 23*4(%0) \n" |
---|
402 | "lwc1 $f24, 24*4(%0) \n" |
---|
403 | "lwc1 $f25, 25*4(%0) \n" |
---|
404 | "lwc1 $f26, 26*4(%0) \n" |
---|
405 | "lwc1 $f27, 27*4(%0) \n" |
---|
406 | "lwc1 $f28, 28*4(%0) \n" |
---|
407 | "lwc1 $f29, 29*4(%0) \n" |
---|
408 | "lwc1 $f30, 30*4(%0) \n" |
---|
409 | "lwc1 $f31, 31*4(%0) \n" |
---|
410 | ".set reorder \n" |
---|
411 | : : "r"(ctx) ); |
---|
412 | |
---|
413 | } // end hal_cpu_context_restore() |
---|
414 | |
---|
415 | ///////////////////////////////////// |
---|
416 | void hal_fpu_context_dup( xptr_t dst, |
---|
417 | xptr_t src ) |
---|
418 | { |
---|
419 | hal_remote_memcpy( dst , src , sizeof(hal_fpu_context_t) ); |
---|
420 | } |
---|
421 | |
---|