[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #include <hal_types.h> |
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| 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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| 27 | #include <printk.h> |
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| 28 | #include <bits.h> |
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| 29 | #include <process.h> |
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| 30 | #include <kmem.h> |
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| 31 | #include <thread.h> |
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| 32 | #include <cluster.h> |
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| 33 | #include <ppm.h> |
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| 34 | #include <page.h> |
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| 35 | |
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| 36 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 37 | // This define the masks for the TSAR MMU PTE attributes. (from TSAR MMU specification) |
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| 38 | // the GPT masks are derived from the TSAR MMU PTE attributes |
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| 39 | // in the TSAR specific hal_gpt_create() function. |
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| 40 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 41 | |
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| 42 | #define TSAR_MMU_PRESENT 0x80000000 |
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| 43 | #define TSAR_MMU_PTD1 0x40000000 |
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| 44 | #define TSAR_MMU_LOCAL 0x20000000 |
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| 45 | #define TSAR_MMU_REMOTE 0x10000000 |
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| 46 | #define TSAR_MMU_CACHABLE 0x08000000 |
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| 47 | #define TSAR_MMU_WRITABLE 0x04000000 |
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| 48 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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| 49 | #define TSAR_MMU_USER 0x01000000 |
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| 50 | #define TSAR_MMU_GLOBAL 0x00800000 |
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| 51 | #define TSAR_MMU_DIRTY 0x00400000 |
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| 52 | |
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| 53 | #define TSAR_MMU_COW 0x00000001 |
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| 54 | #define TSAR_MMU_SWAP 0x00000004 |
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| 55 | #define TSAR_MMU_LOCKED 0x00000008 |
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| 56 | |
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| 57 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 58 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 59 | // - IX1 on 11 bits |
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| 60 | // - IX2 on 9 bits |
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| 61 | // - PPN on 28 bits |
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| 62 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 63 | |
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| 64 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 65 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 66 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 67 | |
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| 68 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 69 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 70 | |
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[315] | 71 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 72 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 73 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 74 | |
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| 75 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 76 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 77 | |
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| 78 | /**************************************************************************************** |
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| 79 | * These global variables defines the masks for the Generic Page Table Entry attributes, |
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| 80 | * and must be defined in all GPT implementation. |
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| 81 | ***************************************************************************************/ |
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| 82 | |
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| 83 | uint32_t GPT_MAPPED; |
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| 84 | uint32_t GPT_SMALL; |
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| 85 | uint32_t GPT_READABLE; |
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| 86 | uint32_t GPT_WRITABLE; |
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| 87 | uint32_t GPT_EXECUTABLE; |
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| 88 | uint32_t GPT_CACHABLE; |
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| 89 | uint32_t GPT_USER; |
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| 90 | uint32_t GPT_DIRTY; |
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| 91 | uint32_t GPT_ACCESSED; |
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| 92 | uint32_t GPT_GLOBAL; |
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| 93 | uint32_t GPT_COW; |
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| 94 | uint32_t GPT_SWAP; |
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| 95 | uint32_t GPT_LOCKED; |
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| 96 | |
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| 97 | ///////////////////////////////////// |
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| 98 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 99 | { |
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| 100 | page_t * page; |
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[315] | 101 | xptr_t page_xp; |
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[1] | 102 | |
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| 103 | // check page size |
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[50] | 104 | if( CONFIG_PPM_PAGE_SIZE != 4096 ) |
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[1] | 105 | { |
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| 106 | printk("\n[PANIC] in %s : For TSAR, the page must be 4 Kbytes\n", __FUNCTION__ ); |
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| 107 | hal_core_sleep(); |
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| 108 | } |
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| 109 | |
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| 110 | // allocates 2 physical pages for PT1 |
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| 111 | kmem_req_t req; |
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| 112 | req.type = KMEM_PAGE; |
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| 113 | req.size = 1; // 2 small pages |
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| 114 | req.flags = AF_KERNEL | AF_ZERO; |
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| 115 | page = (page_t *)kmem_alloc( &req ); |
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| 116 | |
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| 117 | if( page == NULL ) |
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| 118 | { |
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| 119 | printk("\n[ERROR] in %s : cannot allocate physical memory for PT1\n", __FUNCTION__ ); |
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| 120 | return ENOMEM; |
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| 121 | } |
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| 122 | |
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| 123 | // initialize generic page table descriptor |
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[315] | 124 | page_xp = XPTR( local_cxy , page ); |
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[1] | 125 | |
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[315] | 126 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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| 127 | gpt->ppn = ppm_page2ppn( page_xp ); |
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| 128 | gpt->page = GET_PTR( page_xp ); |
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| 129 | |
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[1] | 130 | // initialize PTE entries attributes masks |
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| 131 | GPT_MAPPED = TSAR_MMU_PRESENT; |
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| 132 | GPT_SMALL = TSAR_MMU_PTD1; |
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| 133 | GPT_READABLE = TSAR_MMU_PRESENT; |
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| 134 | GPT_WRITABLE = TSAR_MMU_WRITABLE; |
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| 135 | GPT_EXECUTABLE = TSAR_MMU_EXECUTABLE; |
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| 136 | GPT_CACHABLE = TSAR_MMU_CACHABLE; |
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| 137 | GPT_USER = TSAR_MMU_USER; |
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| 138 | GPT_DIRTY = TSAR_MMU_DIRTY; |
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| 139 | GPT_ACCESSED = TSAR_MMU_LOCAL | TSAR_MMU_REMOTE; |
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| 140 | GPT_GLOBAL = TSAR_MMU_GLOBAL; |
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| 141 | GPT_COW = TSAR_MMU_COW; |
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| 142 | GPT_SWAP = TSAR_MMU_SWAP; |
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| 143 | GPT_LOCKED = TSAR_MMU_LOCKED; |
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| 144 | |
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| 145 | return 0; |
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| 146 | } // end hal_gpt_create() |
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| 147 | |
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| 148 | |
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| 149 | /////////////////////////////////// |
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| 150 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 151 | { |
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| 152 | uint32_t ix1; |
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| 153 | uint32_t ix2; |
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| 154 | uint32_t * pt1; |
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| 155 | uint32_t pte1; |
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| 156 | ppn_t pt2_ppn; |
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| 157 | uint32_t * pt2; |
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| 158 | uint32_t attr; |
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| 159 | vpn_t vpn; |
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| 160 | kmem_req_t req; |
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| 161 | bool_t is_ref; |
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| 162 | |
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| 163 | // get pointer on calling process |
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| 164 | process_t * process = CURRENT_THREAD->process; |
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| 165 | |
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| 166 | // compute is_ref |
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[23] | 167 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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[1] | 168 | |
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| 169 | // get pointer on PT1 |
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| 170 | pt1 = (uint32_t *)gpt->ptr; |
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| 171 | |
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| 172 | // scan the PT1 |
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| 173 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 174 | { |
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| 175 | pte1 = pt1[ix1]; |
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| 176 | if( (pte1 & GPT_MAPPED) != 0 ) // PTE1 valid |
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| 177 | { |
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| 178 | if( (pte1 & GPT_SMALL) == 0 ) // BIG page |
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| 179 | { |
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| 180 | if( (pte1 & GPT_USER) != 0 ) |
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| 181 | { |
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| 182 | // warning message |
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| 183 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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| 184 | __FUNCTION__ , ix1 ); |
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| 185 | |
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| 186 | // release the big physical page if reference cluster |
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| 187 | if( is_ref ) |
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| 188 | { |
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| 189 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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| 190 | hal_gpt_reset_pte( gpt , vpn ); |
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| 191 | } |
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| 192 | } |
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| 193 | } |
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| 194 | else // SMALL page |
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| 195 | { |
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[315] | 196 | // get local pointer on PT2 |
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[1] | 197 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 198 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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| 199 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[1] | 200 | |
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| 201 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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| 202 | if( is_ref ) |
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| 203 | { |
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| 204 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 205 | { |
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| 206 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 207 | if( ((attr & GPT_MAPPED) != 0 ) && ((attr & GPT_USER) != 0) ) |
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| 208 | { |
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| 209 | // release the physical page |
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| 210 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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| 211 | hal_gpt_reset_pte( gpt , vpn ); |
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| 212 | } |
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| 213 | } |
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| 214 | } |
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| 215 | |
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| 216 | // release the PT2 |
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| 217 | req.type = KMEM_PAGE; |
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[315] | 218 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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[1] | 219 | kmem_free( &req ); |
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| 220 | } |
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| 221 | } |
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| 222 | } |
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| 223 | |
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| 224 | // release the PT1 |
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| 225 | req.type = KMEM_PAGE; |
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[315] | 226 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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[1] | 227 | kmem_free( &req ); |
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| 228 | |
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| 229 | } // end hal_gpt_destroy() |
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| 230 | |
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| 231 | ///////////////////////////////// |
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| 232 | void hal_gpt_print( gpt_t * gpt ) |
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| 233 | { |
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| 234 | uint32_t ix1; |
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| 235 | uint32_t ix2; |
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| 236 | uint32_t * pt1; |
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| 237 | uint32_t pte1; |
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| 238 | ppn_t pt2_ppn; |
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| 239 | uint32_t * pt2; |
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| 240 | uint32_t pte2_attr; |
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| 241 | ppn_t pte2_ppn; |
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| 242 | |
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| 243 | printk("*** Page Table for process %x in cluster %x ***\n", |
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[23] | 244 | CURRENT_THREAD->process->pid , local_cxy ); |
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[1] | 245 | |
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| 246 | pt1 = (uint32_t *)gpt->ptr; |
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| 247 | |
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| 248 | // scan the PT1 |
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| 249 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 250 | { |
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| 251 | pte1 = pt1[ix1]; |
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| 252 | if( (pte1 & GPT_MAPPED) != 0 ) |
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| 253 | { |
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| 254 | if( (pte1 & GPT_SMALL) == 0 ) // BIG page |
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| 255 | { |
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| 256 | printk(" - BIG : pt1[%d] = %x\n", ix1 , pte1 ); |
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| 257 | } |
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| 258 | else // SMALL pages |
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| 259 | { |
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| 260 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 261 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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| 262 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[1] | 263 | |
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| 264 | // scan the PT2 |
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| 265 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 266 | { |
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| 267 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 268 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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| 269 | if( (pte2_attr & GPT_MAPPED) != 0 ) |
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| 270 | { |
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| 271 | printk(" - SMALL : pt1[%d] = %x / pt2[%d] / pt2[%d]\n", |
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| 272 | ix1 , pt1[ix1] , 2*ix2 , pte2_attr , 2*ix2+1 , pte2_ppn ); |
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| 273 | } |
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| 274 | } |
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| 275 | } |
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| 276 | } |
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| 277 | } |
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| 278 | } // end hal_gpt_print() |
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| 279 | |
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| 280 | |
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| 281 | /////////////////////////////////////// |
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| 282 | error_t hal_gpt_set_pte( gpt_t * gpt, |
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| 283 | vpn_t vpn, |
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| 284 | ppn_t ppn, |
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| 285 | uint32_t attr ) |
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| 286 | { |
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| 287 | uint32_t * pt1; // virtual base addres of PT1 |
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| 288 | volatile uint32_t * pte1_ptr; // pointer on PT1 entry |
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| 289 | uint32_t pte1; // PT1 entry value |
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| 290 | |
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| 291 | ppn_t pt2_ppn; // PPN of PT2 |
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| 292 | uint32_t * pt2; // virtual base address of PT2 |
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| 293 | |
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| 294 | uint32_t small; // requested PTE is for a small page |
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[315] | 295 | bool_t atomic; |
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| 296 | |
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[1] | 297 | page_t * page; // pointer on new physical page descriptor |
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[315] | 298 | xptr_t page_xp; // extended pointer on new page descriptor |
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[1] | 299 | |
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| 300 | uint32_t ix1; // index in PT1 |
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| 301 | uint32_t ix2; // index in PT2 |
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| 302 | |
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| 303 | // compute indexes in PT1 and PT2 |
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| 304 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 305 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 306 | |
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| 307 | pt1 = gpt->ptr; |
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| 308 | small = (attr & GPT_SMALL); |
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| 309 | |
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| 310 | // get PT1 entry value |
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| 311 | pte1_ptr = &pt1[ix1]; |
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| 312 | pte1 = *pte1_ptr; |
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| 313 | |
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| 314 | // Big pages (PTE1) are only set for the kernel vsegs, in the kernel init phase. |
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| 315 | // There is no risk of concurrent access. |
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| 316 | if( small == 0 ) |
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| 317 | { |
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| 318 | if( (pte1 != 0) || (attr & GPT_COW) ) |
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| 319 | { |
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| 320 | printk("\n[ERROR] in %s : set a big page in a mapped PT1 entry / PT1[%d] = %x\n", |
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| 321 | __FUNCTION__ , ix1 , pte1 ); |
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| 322 | return EINVAL; |
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| 323 | } |
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| 324 | |
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| 325 | // set the PTE1 |
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| 326 | *pte1_ptr = attr | (ppn >> 9); |
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[124] | 327 | hal_fence(); |
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[1] | 328 | return 0; |
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| 329 | } |
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| 330 | |
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| 331 | // From this point, the requested PTE is a PTE2 (small page) |
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| 332 | |
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| 333 | if( (pte1 & GPT_MAPPED) == 0 ) // the PT1 entry is not valid |
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| 334 | { |
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| 335 | // allocate one physical page for the PT2 |
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| 336 | kmem_req_t req; |
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| 337 | req.type = KMEM_PAGE; |
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| 338 | req.size = 0; // 1 small page |
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| 339 | req.flags = AF_KERNEL | AF_ZERO; |
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| 340 | page = (page_t *)kmem_alloc( &req ); |
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| 341 | if( page == NULL ) |
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| 342 | { |
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| 343 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
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| 344 | __FUNCTION__ ); |
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| 345 | return ENOMEM; |
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| 346 | } |
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| 347 | |
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[315] | 348 | page_xp = XPTR( local_cxy , page ); |
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| 349 | pt2_ppn = ppm_page2ppn( page_xp ); |
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| 350 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
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| 351 | |
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[1] | 352 | // try to atomicaly set a PTD1 in the PT1 entry |
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| 353 | do |
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| 354 | { |
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| 355 | atomic = hal_atomic_cas( (void*)pte1, 0 , |
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| 356 | TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | pt2_ppn ); |
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| 357 | } |
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| 358 | while( (atomic == false) && (*pte1_ptr == 0) ); |
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| 359 | |
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| 360 | if( atomic == false ) // the mapping has been done by another thread !!! |
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| 361 | { |
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| 362 | // release the allocated page |
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| 363 | ppm_free_pages( page ); |
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| 364 | |
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| 365 | // read PT1 entry again |
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| 366 | pte1 = *pte1_ptr; |
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| 367 | |
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| 368 | // compute PPN of PT2 base |
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| 369 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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| 370 | |
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| 371 | // compute pointer on PT2 base |
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[315] | 372 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 373 | } |
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| 374 | } |
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| 375 | else // The PT1 entry is valid |
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| 376 | { |
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| 377 | // This valid entry must be a PTD1 |
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| 378 | if( (pte1 & GPT_SMALL) == 0 ) |
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| 379 | { |
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| 380 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
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| 381 | __FUNCTION__ , ix1 , pte1 ); |
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| 382 | return EINVAL; |
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| 383 | } |
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| 384 | |
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| 385 | // compute PPN of PT2 base |
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| 386 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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| 387 | |
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| 388 | // compute pointer on PT2 base |
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[315] | 389 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 390 | } |
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| 391 | |
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| 392 | // set PTE2 in this order |
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| 393 | pt2[2 * ix2 + 1] = ppn; |
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[124] | 394 | hal_fence(); |
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[1] | 395 | pt2[2 * ix2] = attr; |
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[124] | 396 | hal_fence(); |
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[1] | 397 | |
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| 398 | return 0; |
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| 399 | } // end of hal_gpt_set_pte() |
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| 400 | |
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| 401 | ///////////////////////////////////// |
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| 402 | void hal_gpt_get_pte( gpt_t * gpt, |
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| 403 | vpn_t vpn, |
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| 404 | uint32_t * attr, |
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| 405 | ppn_t * ppn ) |
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| 406 | { |
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| 407 | uint32_t * pt1; |
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| 408 | uint32_t pte1; |
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| 409 | |
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| 410 | uint32_t * pt2; |
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| 411 | ppn_t pt2_ppn; |
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| 412 | |
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| 413 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 414 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 415 | |
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| 416 | // get PTE1 value |
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| 417 | pt1 = gpt->ptr; |
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| 418 | pte1 = pt1[ix1]; |
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| 419 | |
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| 420 | if( (pte1 & GPT_MAPPED) == 0 ) // PT1 entry not present |
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| 421 | { |
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| 422 | *attr = 0; |
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| 423 | *ppn = 0; |
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| 424 | } |
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| 425 | |
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| 426 | if( (pte1 & GPT_SMALL) == 0 ) // it's a PTE1 |
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| 427 | { |
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| 428 | *attr = TSAR_MMU_ATTR_FROM_PTE1( pte1 ); |
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| 429 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
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| 430 | } |
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| 431 | else // it's a PTD1 |
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| 432 | { |
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| 433 | // compute PT2 base address |
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| 434 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 435 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 436 | |
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| 437 | *ppn = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
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| 438 | *attr = pt2[2*ix2]; |
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| 439 | } |
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| 440 | } // end hal_gpt_get_pte() |
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| 441 | |
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| 442 | //////////////////////////////////// |
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| 443 | void hal_gpt_reset_pte( gpt_t * gpt, |
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| 444 | vpn_t vpn ) |
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| 445 | { |
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| 446 | uint32_t * pt1; // PT1 base address |
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| 447 | uint32_t pte1; // PT1 entry value |
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| 448 | |
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| 449 | ppn_t pt2_ppn; // PPN of PT2 |
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| 450 | uint32_t * pt2; // PT2 base address |
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| 451 | |
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| 452 | ppn_t ppn; // PPN of page to be released |
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| 453 | |
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| 454 | kmem_req_t req; |
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| 455 | |
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| 456 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 457 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 458 | |
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| 459 | // get PTE1 value |
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| 460 | pt1 = gpt->ptr; |
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| 461 | pte1 = pt1[ix1]; |
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| 462 | |
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| 463 | if( (pte1 & GPT_MAPPED) == 0 ) // PT1 entry not present |
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| 464 | { |
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| 465 | return; |
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| 466 | } |
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| 467 | |
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| 468 | if( (pte1 & GPT_SMALL) == 0 ) // it's a PTE1 |
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| 469 | { |
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| 470 | // get PPN |
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| 471 | ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
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| 472 | |
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| 473 | // unmap the big page |
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| 474 | pt1[ix1] = 0; |
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[124] | 475 | hal_fence(); |
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[1] | 476 | |
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| 477 | // releases the big page |
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| 478 | req.type = KMEM_PAGE; |
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| 479 | req.size = 9; |
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| 480 | req.ptr = (void*)(ppn << CONFIG_PPM_PAGE_SHIFT); |
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| 481 | kmem_free( &req ); |
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| 482 | |
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| 483 | return; |
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| 484 | } |
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| 485 | else // it's a PTD1 |
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| 486 | { |
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| 487 | // compute PT2 base address |
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| 488 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 489 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 490 | |
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| 491 | // get PPN |
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| 492 | ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] ); |
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| 493 | |
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| 494 | // unmap the small page |
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| 495 | pt2[2*ix2] = 0; |
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[124] | 496 | hal_fence(); |
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[1] | 497 | pt2[2*ix2+1] = 0; |
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[124] | 498 | hal_fence(); |
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[1] | 499 | |
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| 500 | // releases the small page |
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| 501 | req.type = KMEM_PAGE; |
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| 502 | req.size = 0; |
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| 503 | req.ptr = (void*)(ppn << CONFIG_PPM_PAGE_SHIFT); |
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| 504 | kmem_free( &req ); |
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| 505 | |
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| 506 | return; |
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| 507 | } |
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| 508 | } // end hal_gpt_reset_pte() |
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| 509 | |
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| 510 | ////////////////////////////////////// |
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| 511 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
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| 512 | vpn_t vpn ) |
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| 513 | { |
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| 514 | uint32_t * pt1; // PT1 base address |
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| 515 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
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| 516 | uint32_t pte1; // value of PT1 entry |
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| 517 | |
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| 518 | uint32_t * pt2; // PT2 base address |
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| 519 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
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| 520 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
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| 521 | |
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| 522 | uint32_t attr; |
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| 523 | bool_t atomic; |
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| 524 | page_t * page; |
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[315] | 525 | xptr_t page_xp; |
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[1] | 526 | |
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| 527 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
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| 528 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
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| 529 | |
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| 530 | // get the PTE1 value |
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| 531 | pt1 = gpt->ptr; |
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| 532 | pte1_ptr = &pt1[ix1]; |
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| 533 | pte1 = *pte1_ptr; |
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| 534 | |
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| 535 | // If present, the page must be small |
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| 536 | if( ((pte1 & GPT_MAPPED) != 0) && ((pte1 & GPT_SMALL) == 0) ) |
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| 537 | { |
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| 538 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
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| 539 | __FUNCTION__ , ix1 , pte1 ); |
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| 540 | return EINVAL; |
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| 541 | } |
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| 542 | |
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| 543 | if( (pte1 & GPT_MAPPED) == 0 ) // missing PT1 entry |
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| 544 | { |
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| 545 | // allocate one physical page for PT2 |
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| 546 | kmem_req_t req; |
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| 547 | req.type = KMEM_PAGE; |
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| 548 | req.size = 0; // 1 small page |
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| 549 | req.flags = AF_KERNEL | AF_ZERO; |
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| 550 | page = (page_t *)kmem_alloc( &req ); |
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[23] | 551 | |
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[1] | 552 | if( page == NULL ) |
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| 553 | { |
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| 554 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
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| 555 | __FUNCTION__ ); |
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| 556 | return ENOMEM; |
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| 557 | } |
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[23] | 558 | |
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[315] | 559 | page_xp = XPTR( local_cxy , page ); |
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| 560 | pt2_ppn = ppm_page2ppn( page_xp ); |
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| 561 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
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[1] | 562 | |
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| 563 | // try to set the PT1 entry |
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| 564 | do |
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| 565 | { |
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| 566 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
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| 567 | TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | pt2_ppn ); |
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| 568 | } |
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| 569 | while( (atomic == false) && (*pte1_ptr == 0) ); |
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| 570 | |
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| 571 | if( atomic == false ) // missing PT2 has been allocate by another core |
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| 572 | { |
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| 573 | // release the allocated page |
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| 574 | ppm_free_pages( page ); |
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| 575 | |
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| 576 | // read again the PTE1 |
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| 577 | pte1 = *pte1_ptr; |
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| 578 | |
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| 579 | // get the PT2 base address |
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| 580 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
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[315] | 581 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 582 | } |
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| 583 | } |
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| 584 | else |
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| 585 | { |
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| 586 | // This valid entry must be a PTD1 |
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| 587 | if( (pte1 & GPT_SMALL) == 0 ) |
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| 588 | { |
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| 589 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
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| 590 | __FUNCTION__ , ix1 , pte1 ); |
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| 591 | return EINVAL; |
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| 592 | } |
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| 593 | |
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| 594 | // compute PPN of PT2 base |
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| 595 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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| 596 | |
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| 597 | // compute pointer on PT2 base |
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[315] | 598 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 599 | } |
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| 600 | |
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| 601 | // from here we have the PT2 pointer |
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| 602 | |
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| 603 | // compute pointer on PTE2 |
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| 604 | pte2_ptr = &pt2[2 * ix2]; |
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| 605 | |
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| 606 | // try to atomically lock the PTE2 until success |
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| 607 | do |
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| 608 | { |
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| 609 | // busy waiting until GPT_LOCK == 0 |
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| 610 | do |
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| 611 | { |
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| 612 | attr = *pte2_ptr; |
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| 613 | hal_rdbar(); |
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| 614 | } |
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| 615 | while( (attr & GPT_LOCKED) != 0 ); |
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| 616 | |
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| 617 | // try to set the GPT_LOCK wit a CAS |
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| 618 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | GPT_LOCKED) ); |
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| 619 | } |
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| 620 | while( atomic == 0 ); |
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| 621 | |
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| 622 | return 0; |
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| 623 | } // end hal_gpt_lock_pte() |
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| 624 | |
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| 625 | //////////////////////////////////////// |
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| 626 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
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| 627 | vpn_t vpn ) |
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| 628 | { |
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| 629 | uint32_t * pt1; // PT1 base address |
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| 630 | uint32_t pte1; // value of PT1 entry |
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| 631 | |
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| 632 | uint32_t * pt2; // PT2 base address |
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| 633 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
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| 634 | uint32_t * pte2_ptr; // address of PT2 entry |
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| 635 | |
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| 636 | uint32_t attr; // PTE2 attribute |
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| 637 | |
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| 638 | // compute indexes in P1 and PT2 |
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| 639 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
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| 640 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
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| 641 | |
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| 642 | // get pointer on PT1 base |
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| 643 | pt1 = (uint32_t*)gpt->ptr; |
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| 644 | |
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| 645 | // get PTE1 |
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| 646 | pte1 = pt1[ix1]; |
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| 647 | |
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| 648 | // check PTE1 present and small page |
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| 649 | if( ((pte1 & GPT_MAPPED) == 0) || ((pte1 & GPT_SMALL) == 0) ) |
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| 650 | { |
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| 651 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
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| 652 | __FUNCTION__ , ix1 , pte1 ); |
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| 653 | return EINVAL; |
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| 654 | } |
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| 655 | |
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| 656 | // get pointer on PT2 base |
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| 657 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
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[315] | 658 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 659 | |
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| 660 | // get pointer on PTE2 |
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| 661 | pte2_ptr = &pt2[2 * ix2]; |
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| 662 | |
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| 663 | // get PTE2_ATTR |
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| 664 | attr = *pte2_ptr; |
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| 665 | |
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| 666 | // check PTE2 present and locked |
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| 667 | if( ((attr & GPT_MAPPED) == 0) || ((attr & GPT_LOCKED) == 0) ); |
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| 668 | { |
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| 669 | printk("\n[ERROR] in %s : try to unlock an undefined page / PT1[%d] = %x\n", |
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| 670 | __FUNCTION__ , ix1 , pte1 ); |
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| 671 | return EINVAL; |
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| 672 | } |
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| 673 | |
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| 674 | // reset GPT_LOCK |
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| 675 | *pte2_ptr = attr & !GPT_LOCKED; |
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| 676 | |
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| 677 | return 0; |
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| 678 | } // end hal_gpt_unlock_pte() |
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| 679 | |
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[23] | 680 | /////////////////////////////////////// |
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| 681 | error_t hal_gpt_copy( gpt_t * dst_gpt, |
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| 682 | gpt_t * src_gpt, |
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| 683 | bool_t cow ) |
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| 684 | { |
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| 685 | uint32_t ix1; // index in PT1 |
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| 686 | uint32_t ix2; // index in PT2 |
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[1] | 687 | |
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[23] | 688 | uint32_t * src_pt1; // local pointer on PT1 for SRC_GPT |
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| 689 | uint32_t * dst_pt1; // local pointer on PT1 for DST_GPT |
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| 690 | uint32_t * dst_pt2; // local pointer on PT2 for DST_GPT |
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| 691 | uint32_t * src_pt2; // local pointer on PT2 for SRC_GPT |
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[1] | 692 | |
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[23] | 693 | uint32_t pte1; |
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| 694 | uint32_t pte2_attr; |
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| 695 | uint32_t pte2_ppn; |
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| 696 | uint32_t pte2_writable; |
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[1] | 697 | |
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[23] | 698 | page_t * page; |
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[315] | 699 | xptr_t page_xp; |
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[1] | 700 | |
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[23] | 701 | ppn_t src_pt2_ppn; |
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| 702 | ppn_t dst_pt2_ppn; |
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[1] | 703 | |
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[23] | 704 | // get pointers on PT1 for src_gpt & dst_gpt |
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| 705 | src_pt1 = (uint32_t *)src_gpt->ptr; |
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| 706 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
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[1] | 707 | |
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[23] | 708 | // scan the SRC_PT1 |
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| 709 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 710 | { |
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| 711 | pte1 = src_pt1[ix1]; |
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| 712 | if( (pte1 & GPT_MAPPED) != 0 ) |
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| 713 | { |
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| 714 | if( (pte1 & GPT_SMALL) == 0 ) // PTE1 => big kernel page |
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| 715 | { |
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| 716 | // big kernel pages are shared by all processes => copy it |
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| 717 | dst_pt1[ix1] = pte1; |
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| 718 | } |
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| 719 | else // PTD1 => smal pages |
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| 720 | { |
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| 721 | // allocate one physical page for a PT2 in DST_GPT |
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| 722 | kmem_req_t req; |
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| 723 | req.type = KMEM_PAGE; |
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| 724 | req.size = 0; // 1 small page |
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| 725 | req.flags = AF_KERNEL | AF_ZERO; |
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| 726 | page = (page_t *)kmem_alloc( &req ); |
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[1] | 727 | |
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[23] | 728 | if( page == NULL ) |
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| 729 | { |
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| 730 | // TODO release all memory allocated to DST_GPT |
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| 731 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
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| 732 | return ENOMEM; |
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| 733 | } |
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| 734 | |
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[315] | 735 | // get extended pointer on page descriptor |
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| 736 | page_xp = XPTR( local_cxy , page ); |
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| 737 | |
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[23] | 738 | // get pointer on new PT2 in DST_GPT |
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[315] | 739 | xptr_t base_xp = ppm_page2base( page_xp ); |
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| 740 | dst_pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[23] | 741 | |
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| 742 | // set a new PTD1 in DST_GPT |
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[315] | 743 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
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[23] | 744 | dst_pt1[ix1] = TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | dst_pt2_ppn; |
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| 745 | |
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| 746 | // get pointer on PT2 in SRC_GPT |
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| 747 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 748 | src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
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[23] | 749 | |
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| 750 | // scan the SRC_PT2 |
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| 751 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 752 | { |
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| 753 | // get attr & ppn from PTE2 |
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| 754 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] ); |
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| 755 | |
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| 756 | if( (pte2_attr & GPT_MAPPED) != 0 ) // valid PTE2 in SRC_GPT |
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| 757 | { |
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| 758 | // get GPT_WRITABLE & PPN |
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| 759 | pte2_writable = pte2_attr & GPT_WRITABLE; |
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| 760 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] ); |
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| 761 | |
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| 762 | // set a new PTE2 in DST_GPT |
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| 763 | dst_pt2[2*ix2] = pte2_attr; |
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| 764 | dst_pt2[2*ix2 + 1] = pte2_ppn; |
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| 765 | |
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| 766 | // handle Copy-On-Write |
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| 767 | if( cow && pte2_writable ) |
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| 768 | { |
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| 769 | // reset GPT_WRITABLE in both SRC_GPT and DST_GPT |
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| 770 | hal_atomic_and( &dst_pt2[2*ix2] , ~GPT_WRITABLE ); |
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| 771 | hal_atomic_and( &src_pt2[2*ix2] , ~GPT_WRITABLE ); |
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| 772 | |
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| 773 | // register PG_COW in page descriptor |
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[315] | 774 | page = (page_t *)GET_PTR( ppm_ppn2page( pte2_ppn ) ); |
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[23] | 775 | hal_atomic_or( &page->flags , PG_COW ); |
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| 776 | hal_atomic_add( &page->fork_nr , 1 ); |
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| 777 | } |
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| 778 | } |
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| 779 | } // end loop on ix2 |
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| 780 | } |
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| 781 | } |
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| 782 | } // end loop ix1 |
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| 783 | |
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[124] | 784 | hal_fence(); |
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[23] | 785 | |
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| 786 | return 0; |
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| 787 | |
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| 788 | } // end hal_gpt_copy() |
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| 789 | |
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