[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #include <hal_types.h> |
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| 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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| 27 | #include <printk.h> |
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| 28 | #include <bits.h> |
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| 29 | #include <process.h> |
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| 30 | #include <kmem.h> |
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| 31 | #include <thread.h> |
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| 32 | #include <cluster.h> |
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| 33 | #include <ppm.h> |
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| 34 | #include <page.h> |
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| 35 | |
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| 36 | //////////////////////////////////////////////////////////////////////////////////////// |
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[401] | 37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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[1] | 38 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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[401] | 40 | #define TSAR_MMU_MAPPED 0x80000000 |
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| 41 | #define TSAR_MMU_SMALL 0x40000000 |
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[1] | 42 | #define TSAR_MMU_LOCAL 0x20000000 |
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| 43 | #define TSAR_MMU_REMOTE 0x10000000 |
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| 44 | #define TSAR_MMU_CACHABLE 0x08000000 |
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| 45 | #define TSAR_MMU_WRITABLE 0x04000000 |
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| 46 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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| 47 | #define TSAR_MMU_USER 0x01000000 |
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| 48 | #define TSAR_MMU_GLOBAL 0x00800000 |
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| 49 | #define TSAR_MMU_DIRTY 0x00400000 |
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| 50 | |
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[401] | 51 | #define TSAR_MMU_COW 0x00000001 // only for small pages |
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| 52 | #define TSAR_MMU_SWAP 0x00000004 // only for small pages |
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| 53 | #define TSAR_MMU_LOCKED 0x00000008 // only for small pages |
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[1] | 54 | |
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| 55 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 57 | // - IX1 on 11 bits |
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| 58 | // - IX2 on 9 bits |
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| 59 | // - PPN on 28 bits |
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| 60 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 63 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 64 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 65 | |
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[401] | 66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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| 67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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| 68 | |
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[1] | 69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 71 | |
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[315] | 72 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 73 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 75 | |
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| 76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 78 | |
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[401] | 79 | |
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| 80 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 81 | // This static function translates the GPT attributes to the TSAR attributes |
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| 82 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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| 84 | { |
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| 85 | uint32_t tsar_attr = 0; |
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| 86 | |
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| 87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_MMU_MAPPED; |
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| 88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_MMU_SMALL; |
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| 89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_MMU_WRITABLE; |
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| 90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_MMU_EXECUTABLE; |
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| 91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_MMU_CACHABLE; |
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| 92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_MMU_USER; |
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| 93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_MMU_DIRTY; |
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| 94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_MMU_LOCAL; |
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| 95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_MMU_GLOBAL; |
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| 96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_MMU_COW; |
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| 97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_MMU_SWAP; |
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| 98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_MMU_LOCKED; |
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| 99 | |
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| 100 | return tsar_attr; |
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| 101 | } |
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| 102 | |
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| 103 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 104 | // This static function translates the TSAR attributes to the GPT attributes |
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| 105 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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| 107 | { |
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| 108 | uint32_t gpt_attr = 0; |
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| 109 | |
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| 110 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_MAPPED; |
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| 111 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_READABLE; |
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| 112 | if( tsar_attr & TSAR_MMU_SMALL ) gpt_attr |= GPT_SMALL; |
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| 113 | if( tsar_attr & TSAR_MMU_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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| 114 | if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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| 115 | if( tsar_attr & TSAR_MMU_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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| 116 | if( tsar_attr & TSAR_MMU_USER ) gpt_attr |= GPT_USER; |
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| 117 | if( tsar_attr & TSAR_MMU_DIRTY ) gpt_attr |= GPT_DIRTY; |
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| 118 | if( tsar_attr & TSAR_MMU_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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| 119 | if( tsar_attr & TSAR_MMU_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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| 120 | if( tsar_attr & TSAR_MMU_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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| 121 | if( tsar_attr & TSAR_MMU_COW ) gpt_attr |= GPT_COW; |
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| 122 | if( tsar_attr & TSAR_MMU_SWAP ) gpt_attr |= GPT_SWAP; |
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| 123 | if( tsar_attr & TSAR_MMU_LOCKED ) gpt_attr |= GPT_LOCKED; |
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| 124 | |
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| 125 | return gpt_attr; |
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| 126 | } |
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| 127 | |
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[1] | 128 | ///////////////////////////////////// |
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| 129 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 130 | { |
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| 131 | page_t * page; |
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[315] | 132 | xptr_t page_xp; |
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[1] | 133 | |
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[407] | 134 | gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n", |
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| 135 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid ); |
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[406] | 136 | |
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[1] | 137 | // check page size |
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[406] | 138 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , __FUNCTION__ , |
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| 139 | "for TSAR, the page must be 4 Kbytes\n" ); |
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[1] | 140 | |
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| 141 | // allocates 2 physical pages for PT1 |
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| 142 | kmem_req_t req; |
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| 143 | req.type = KMEM_PAGE; |
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| 144 | req.size = 1; // 2 small pages |
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| 145 | req.flags = AF_KERNEL | AF_ZERO; |
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| 146 | page = (page_t *)kmem_alloc( &req ); |
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| 147 | |
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[406] | 148 | if( page == NULL ) |
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[1] | 149 | { |
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[406] | 150 | printk("\n[ERROR] in %s : cannot allocate memory for PT1\n", __FUNCTION__ ); |
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[1] | 151 | return ENOMEM; |
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[406] | 152 | } |
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[1] | 153 | |
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| 154 | // initialize generic page table descriptor |
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[315] | 155 | page_xp = XPTR( local_cxy , page ); |
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| 156 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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| 157 | gpt->ppn = ppm_page2ppn( page_xp ); |
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| 158 | |
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[407] | 159 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n", |
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| 160 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid ); |
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[406] | 161 | |
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[1] | 162 | return 0; |
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[406] | 163 | |
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[1] | 164 | } // end hal_gpt_create() |
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| 165 | |
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| 166 | |
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| 167 | /////////////////////////////////// |
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| 168 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 169 | { |
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| 170 | uint32_t ix1; |
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| 171 | uint32_t ix2; |
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| 172 | uint32_t * pt1; |
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| 173 | uint32_t pte1; |
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| 174 | ppn_t pt2_ppn; |
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| 175 | uint32_t * pt2; |
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| 176 | uint32_t attr; |
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| 177 | vpn_t vpn; |
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| 178 | kmem_req_t req; |
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| 179 | bool_t is_ref; |
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| 180 | |
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| 181 | // get pointer on calling process |
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| 182 | process_t * process = CURRENT_THREAD->process; |
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| 183 | |
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| 184 | // compute is_ref |
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[23] | 185 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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[1] | 186 | |
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| 187 | // get pointer on PT1 |
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| 188 | pt1 = (uint32_t *)gpt->ptr; |
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| 189 | |
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| 190 | // scan the PT1 |
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| 191 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 192 | { |
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| 193 | pte1 = pt1[ix1]; |
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[401] | 194 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) // PTE1 valid |
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[1] | 195 | { |
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[401] | 196 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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[1] | 197 | { |
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[391] | 198 | if( (pte1 & TSAR_MMU_USER) != 0 ) |
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[1] | 199 | { |
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| 200 | // warning message |
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| 201 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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[391] | 202 | __FUNCTION__ , ix1 ); |
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[1] | 203 | |
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| 204 | // release the big physical page if reference cluster |
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| 205 | if( is_ref ) |
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| 206 | { |
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| 207 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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| 208 | hal_gpt_reset_pte( gpt , vpn ); |
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| 209 | } |
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| 210 | } |
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| 211 | } |
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[391] | 212 | else // SMALL page |
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[1] | 213 | { |
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[315] | 214 | // get local pointer on PT2 |
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[1] | 215 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 216 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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| 217 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[1] | 218 | |
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| 219 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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| 220 | if( is_ref ) |
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| 221 | { |
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| 222 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 223 | { |
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| 224 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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[401] | 225 | if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) ) |
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[1] | 226 | { |
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| 227 | // release the physical page |
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| 228 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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| 229 | hal_gpt_reset_pte( gpt , vpn ); |
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| 230 | } |
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| 231 | } |
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| 232 | } |
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| 233 | |
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| 234 | // release the PT2 |
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| 235 | req.type = KMEM_PAGE; |
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[315] | 236 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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[1] | 237 | kmem_free( &req ); |
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| 238 | } |
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| 239 | } |
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| 240 | } |
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| 241 | |
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| 242 | // release the PT1 |
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| 243 | req.type = KMEM_PAGE; |
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[315] | 244 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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[1] | 245 | kmem_free( &req ); |
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| 246 | |
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| 247 | } // end hal_gpt_destroy() |
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| 248 | |
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[407] | 249 | /////////////////////////////////////////// |
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| 250 | void hal_gpt_display( process_t * process ) |
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[1] | 251 | { |
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[407] | 252 | gpt_t * gpt; |
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[1] | 253 | uint32_t ix1; |
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| 254 | uint32_t ix2; |
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| 255 | uint32_t * pt1; |
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| 256 | uint32_t pte1; |
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| 257 | ppn_t pt2_ppn; |
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| 258 | uint32_t * pt2; |
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| 259 | uint32_t pte2_attr; |
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| 260 | ppn_t pte2_ppn; |
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[406] | 261 | vpn_t vpn; |
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[1] | 262 | |
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[407] | 263 | assert( (process != NULL) , __FUNCTION__ , "NULL process pointer\n"); |
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[1] | 264 | |
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[407] | 265 | // get pointer on gpt |
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| 266 | gpt = &(process->vmm.gpt); |
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| 267 | |
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| 268 | // get pointer on PT1 |
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[1] | 269 | pt1 = (uint32_t *)gpt->ptr; |
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| 270 | |
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[406] | 271 | printk("\n***** Generic Page Table for process %x : &gpt = %x / &pt1 = %x\n\n", |
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[407] | 272 | process->pid , gpt , pt1 ); |
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[406] | 273 | |
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[1] | 274 | // scan the PT1 |
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| 275 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 276 | { |
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| 277 | pte1 = pt1[ix1]; |
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[401] | 278 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
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[1] | 279 | { |
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[401] | 280 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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[1] | 281 | { |
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[406] | 282 | vpn = ix1 << 9; |
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| 283 | printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 ); |
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[1] | 284 | } |
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| 285 | else // SMALL pages |
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| 286 | { |
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| 287 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 288 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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| 289 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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[1] | 290 | |
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| 291 | // scan the PT2 |
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| 292 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 293 | { |
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| 294 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 295 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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[406] | 296 | |
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[401] | 297 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
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[1] | 298 | { |
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[406] | 299 | vpn = (ix1 << 9) | ix2; |
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[408] | 300 | printk(" - SMALL : vpn %X / ppn %X / attr %X\n", |
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| 301 | vpn , pte2_ppn , tsar2gpt(pte2_attr) ); |
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[1] | 302 | } |
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| 303 | } |
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| 304 | } |
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| 305 | } |
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| 306 | } |
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[407] | 307 | } // end hal_gpt_display() |
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[1] | 308 | |
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| 309 | |
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| 310 | /////////////////////////////////////// |
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| 311 | error_t hal_gpt_set_pte( gpt_t * gpt, |
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| 312 | vpn_t vpn, |
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[408] | 313 | uint32_t attr, // generic GPT attributes |
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| 314 | ppn_t ppn ) |
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[1] | 315 | { |
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[406] | 316 | uint32_t * pt1; // PT1 base addres |
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| 317 | uint32_t * pte1_ptr; // pointer on PT1 entry |
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[401] | 318 | uint32_t pte1; // PT1 entry value |
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[1] | 319 | |
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[401] | 320 | ppn_t pt2_ppn; // PPN of PT2 |
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[406] | 321 | uint32_t * pt2; // PT2 base address |
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[1] | 322 | |
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[401] | 323 | uint32_t small; // requested PTE is for a small page |
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[406] | 324 | bool_t success; // exit condition for while loop below |
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[315] | 325 | |
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[401] | 326 | page_t * page; // pointer on new physical page descriptor |
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| 327 | xptr_t page_xp; // extended pointer on new page descriptor |
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[1] | 328 | |
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[401] | 329 | uint32_t ix1; // index in PT1 |
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| 330 | uint32_t ix2; // index in PT2 |
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[1] | 331 | |
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[401] | 332 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
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| 333 | |
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[408] | 334 | gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n", |
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| 335 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , ppn , attr ); |
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[406] | 336 | |
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[1] | 337 | // compute indexes in PT1 and PT2 |
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| 338 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 339 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 340 | |
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| 341 | pt1 = gpt->ptr; |
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[401] | 342 | small = attr & GPT_SMALL; |
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[1] | 343 | |
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[401] | 344 | // compute tsar_attr from generic attributes |
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| 345 | tsar_attr = gpt2tsar( attr ); |
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| 346 | |
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[408] | 347 | gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n", |
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| 348 | __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pt1 , tsar_attr ); |
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[406] | 349 | |
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| 350 | // get pointer on PT1[ix1] |
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[1] | 351 | pte1_ptr = &pt1[ix1]; |
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| 352 | |
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[406] | 353 | // PTE1 (big page) are only set for the kernel vsegs, in the kernel init phase. |
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[1] | 354 | // There is no risk of concurrent access. |
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[401] | 355 | if( small == 0 ) |
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| 356 | { |
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[406] | 357 | // get current pte1 value |
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| 358 | pte1 = *pte1_ptr; |
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| 359 | |
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| 360 | assert( (pte1 == 0) , __FUNCTION__ , |
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| 361 | "try to set a big page in a mapped PT1 entry / PT1[%d] = %x\n", ix1 , pte1 ); |
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[1] | 362 | |
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| 363 | // set the PTE1 |
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[401] | 364 | *pte1_ptr = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | |
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| 365 | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
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[124] | 366 | hal_fence(); |
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[1] | 367 | return 0; |
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| 368 | } |
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| 369 | |
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| 370 | // From this point, the requested PTE is a PTE2 (small page) |
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| 371 | |
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[406] | 372 | // loop to access PTE1 and get pointer on PT2 |
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| 373 | success = false; |
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| 374 | do |
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| 375 | { |
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| 376 | // get current pte1 value |
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| 377 | pte1 = *pte1_ptr; |
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| 378 | |
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[408] | 379 | gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n", |
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| 380 | __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 ); |
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[406] | 381 | |
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| 382 | // allocate a PT2 if PT1 entry not valid |
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| 383 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not valid |
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| 384 | { |
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| 385 | // allocate one physical page for the PT2 |
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| 386 | kmem_req_t req; |
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| 387 | req.type = KMEM_PAGE; |
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| 388 | req.size = 0; // 1 small page |
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| 389 | req.flags = AF_KERNEL | AF_ZERO; |
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| 390 | page = (page_t *)kmem_alloc( &req ); |
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| 391 | if( page == NULL ) |
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| 392 | { |
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| 393 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
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| 394 | return ENOMEM; |
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| 395 | } |
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[1] | 396 | |
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[406] | 397 | // get the PT2 PPN |
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| 398 | page_xp = XPTR( local_cxy , page ); |
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| 399 | pt2_ppn = ppm_page2ppn( page_xp ); |
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[315] | 400 | |
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[406] | 401 | // try to atomicaly set the PT1 entry |
---|
| 402 | pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn; |
---|
| 403 | success = hal_atomic_cas( pte1_ptr , 0 , pte1 ); |
---|
[1] | 404 | |
---|
[406] | 405 | // release allocated PT2 if PT1 entry modified by another thread |
---|
| 406 | if( success == false ) ppm_free_pages( page ); |
---|
| 407 | } |
---|
| 408 | else // PT1 entry is valid |
---|
[1] | 409 | { |
---|
[406] | 410 | // This valid entry must be a PTD1 |
---|
| 411 | assert( (pte1 & TSAR_MMU_SMALL) , __FUNCTION__ , |
---|
| 412 | "try to set a small page in a big PT1 entry / PT1[%d] = %x\n", ix1 , pte1 ); |
---|
[1] | 413 | |
---|
[406] | 414 | success = true; |
---|
[1] | 415 | } |
---|
| 416 | |
---|
[406] | 417 | // get PT2 base from pte1 |
---|
| 418 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 419 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 420 | |
---|
[408] | 421 | gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n", |
---|
| 422 | __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 , pt2 ); |
---|
[406] | 423 | |
---|
| 424 | } |
---|
| 425 | while (success == false); |
---|
[1] | 426 | |
---|
| 427 | // set PTE2 in this order |
---|
| 428 | pt2[2 * ix2 + 1] = ppn; |
---|
[124] | 429 | hal_fence(); |
---|
[401] | 430 | pt2[2 * ix2] = tsar_attr; |
---|
[124] | 431 | hal_fence(); |
---|
[1] | 432 | |
---|
[408] | 433 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n", |
---|
| 434 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , |
---|
| 435 | pt2[2 * ix2] , pt2[2 * ix2 + 1] ); |
---|
[406] | 436 | |
---|
[1] | 437 | return 0; |
---|
[401] | 438 | |
---|
[1] | 439 | } // end of hal_gpt_set_pte() |
---|
| 440 | |
---|
[406] | 441 | |
---|
[1] | 442 | ///////////////////////////////////// |
---|
| 443 | void hal_gpt_get_pte( gpt_t * gpt, |
---|
| 444 | vpn_t vpn, |
---|
| 445 | uint32_t * attr, |
---|
| 446 | ppn_t * ppn ) |
---|
| 447 | { |
---|
| 448 | uint32_t * pt1; |
---|
| 449 | uint32_t pte1; |
---|
| 450 | |
---|
| 451 | uint32_t * pt2; |
---|
| 452 | ppn_t pt2_ppn; |
---|
| 453 | |
---|
| 454 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 455 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 456 | |
---|
| 457 | // get PTE1 value |
---|
| 458 | pt1 = gpt->ptr; |
---|
| 459 | pte1 = pt1[ix1]; |
---|
| 460 | |
---|
[401] | 461 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
[1] | 462 | { |
---|
| 463 | *attr = 0; |
---|
| 464 | *ppn = 0; |
---|
| 465 | } |
---|
| 466 | |
---|
[401] | 467 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
[1] | 468 | { |
---|
[401] | 469 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
[1] | 470 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
| 471 | } |
---|
| 472 | else // it's a PTD1 |
---|
| 473 | { |
---|
| 474 | // compute PT2 base address |
---|
| 475 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[315] | 476 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 477 | |
---|
| 478 | *ppn = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
[401] | 479 | *attr = tsar2gpt( pt2[2*ix2] ); |
---|
[1] | 480 | } |
---|
| 481 | } // end hal_gpt_get_pte() |
---|
| 482 | |
---|
| 483 | //////////////////////////////////// |
---|
| 484 | void hal_gpt_reset_pte( gpt_t * gpt, |
---|
| 485 | vpn_t vpn ) |
---|
| 486 | { |
---|
| 487 | uint32_t * pt1; // PT1 base address |
---|
| 488 | uint32_t pte1; // PT1 entry value |
---|
| 489 | |
---|
| 490 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 491 | uint32_t * pt2; // PT2 base address |
---|
| 492 | |
---|
| 493 | ppn_t ppn; // PPN of page to be released |
---|
| 494 | |
---|
[391] | 495 | // get ix1 & ix2 indexes |
---|
[1] | 496 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 497 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 498 | |
---|
| 499 | // get PTE1 value |
---|
| 500 | pt1 = gpt->ptr; |
---|
| 501 | pte1 = pt1[ix1]; |
---|
| 502 | |
---|
[401] | 503 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
[1] | 504 | { |
---|
| 505 | return; |
---|
| 506 | } |
---|
| 507 | |
---|
[401] | 508 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
[1] | 509 | { |
---|
| 510 | // get PPN |
---|
| 511 | ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
| 512 | |
---|
| 513 | // unmap the big page |
---|
| 514 | pt1[ix1] = 0; |
---|
[124] | 515 | hal_fence(); |
---|
[1] | 516 | |
---|
| 517 | return; |
---|
| 518 | } |
---|
[391] | 519 | else // it's a PTD1 |
---|
[1] | 520 | { |
---|
| 521 | // compute PT2 base address |
---|
| 522 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[315] | 523 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 524 | |
---|
| 525 | // get PPN |
---|
| 526 | ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] ); |
---|
| 527 | |
---|
| 528 | // unmap the small page |
---|
[391] | 529 | pt2[2*ix2] = 0; // only attr is reset |
---|
| 530 | hal_fence(); |
---|
[1] | 531 | |
---|
| 532 | return; |
---|
| 533 | } |
---|
| 534 | } // end hal_gpt_reset_pte() |
---|
| 535 | |
---|
| 536 | ////////////////////////////////////// |
---|
| 537 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
---|
| 538 | vpn_t vpn ) |
---|
| 539 | { |
---|
| 540 | uint32_t * pt1; // PT1 base address |
---|
| 541 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
---|
| 542 | uint32_t pte1; // value of PT1 entry |
---|
| 543 | |
---|
| 544 | uint32_t * pt2; // PT2 base address |
---|
| 545 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 546 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 547 | |
---|
| 548 | uint32_t attr; |
---|
| 549 | bool_t atomic; |
---|
| 550 | page_t * page; |
---|
[315] | 551 | xptr_t page_xp; |
---|
[1] | 552 | |
---|
| 553 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 554 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 555 | |
---|
| 556 | // get the PTE1 value |
---|
| 557 | pt1 = gpt->ptr; |
---|
| 558 | pte1_ptr = &pt1[ix1]; |
---|
| 559 | pte1 = *pte1_ptr; |
---|
| 560 | |
---|
| 561 | // If present, the page must be small |
---|
[401] | 562 | if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
[1] | 563 | { |
---|
| 564 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
---|
| 565 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 566 | return EINVAL; |
---|
| 567 | } |
---|
| 568 | |
---|
[401] | 569 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // missing PT1 entry |
---|
[1] | 570 | { |
---|
| 571 | // allocate one physical page for PT2 |
---|
| 572 | kmem_req_t req; |
---|
| 573 | req.type = KMEM_PAGE; |
---|
| 574 | req.size = 0; // 1 small page |
---|
| 575 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 576 | page = (page_t *)kmem_alloc( &req ); |
---|
[23] | 577 | |
---|
[1] | 578 | if( page == NULL ) |
---|
| 579 | { |
---|
| 580 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
---|
| 581 | __FUNCTION__ ); |
---|
| 582 | return ENOMEM; |
---|
| 583 | } |
---|
[23] | 584 | |
---|
[315] | 585 | page_xp = XPTR( local_cxy , page ); |
---|
| 586 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
| 587 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
---|
[1] | 588 | |
---|
| 589 | // try to set the PT1 entry |
---|
| 590 | do |
---|
| 591 | { |
---|
| 592 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
---|
[401] | 593 | TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn ); |
---|
[1] | 594 | } |
---|
| 595 | while( (atomic == false) && (*pte1_ptr == 0) ); |
---|
| 596 | |
---|
| 597 | if( atomic == false ) // missing PT2 has been allocate by another core |
---|
| 598 | { |
---|
| 599 | // release the allocated page |
---|
| 600 | ppm_free_pages( page ); |
---|
| 601 | |
---|
| 602 | // read again the PTE1 |
---|
| 603 | pte1 = *pte1_ptr; |
---|
| 604 | |
---|
| 605 | // get the PT2 base address |
---|
| 606 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[315] | 607 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 608 | } |
---|
| 609 | } |
---|
| 610 | else |
---|
| 611 | { |
---|
| 612 | // This valid entry must be a PTD1 |
---|
[401] | 613 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) |
---|
[1] | 614 | { |
---|
| 615 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
---|
| 616 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 617 | return EINVAL; |
---|
| 618 | } |
---|
| 619 | |
---|
| 620 | // compute PPN of PT2 base |
---|
| 621 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 622 | |
---|
| 623 | // compute pointer on PT2 base |
---|
[315] | 624 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 625 | } |
---|
| 626 | |
---|
| 627 | // from here we have the PT2 pointer |
---|
| 628 | |
---|
| 629 | // compute pointer on PTE2 |
---|
| 630 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 631 | |
---|
| 632 | // try to atomically lock the PTE2 until success |
---|
| 633 | do |
---|
| 634 | { |
---|
[401] | 635 | // busy waiting until TSAR_MMU_LOCK == 0 |
---|
[1] | 636 | do |
---|
| 637 | { |
---|
| 638 | attr = *pte2_ptr; |
---|
| 639 | hal_rdbar(); |
---|
| 640 | } |
---|
[401] | 641 | while( (attr & TSAR_MMU_LOCKED) != 0 ); |
---|
[1] | 642 | |
---|
[401] | 643 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | TSAR_MMU_LOCKED) ); |
---|
[1] | 644 | } |
---|
| 645 | while( atomic == 0 ); |
---|
| 646 | |
---|
| 647 | return 0; |
---|
[401] | 648 | |
---|
[1] | 649 | } // end hal_gpt_lock_pte() |
---|
| 650 | |
---|
| 651 | //////////////////////////////////////// |
---|
| 652 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
---|
| 653 | vpn_t vpn ) |
---|
| 654 | { |
---|
| 655 | uint32_t * pt1; // PT1 base address |
---|
| 656 | uint32_t pte1; // value of PT1 entry |
---|
| 657 | |
---|
| 658 | uint32_t * pt2; // PT2 base address |
---|
| 659 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 660 | uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 661 | |
---|
| 662 | uint32_t attr; // PTE2 attribute |
---|
| 663 | |
---|
| 664 | // compute indexes in P1 and PT2 |
---|
| 665 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 666 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 667 | |
---|
| 668 | // get pointer on PT1 base |
---|
| 669 | pt1 = (uint32_t*)gpt->ptr; |
---|
| 670 | |
---|
| 671 | // get PTE1 |
---|
| 672 | pte1 = pt1[ix1]; |
---|
| 673 | |
---|
| 674 | // check PTE1 present and small page |
---|
[401] | 675 | if( ((pte1 & TSAR_MMU_MAPPED) == 0) || ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
[1] | 676 | { |
---|
| 677 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
---|
| 678 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 679 | return EINVAL; |
---|
| 680 | } |
---|
| 681 | |
---|
| 682 | // get pointer on PT2 base |
---|
| 683 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[315] | 684 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 685 | |
---|
| 686 | // get pointer on PTE2 |
---|
| 687 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 688 | |
---|
| 689 | // get PTE2_ATTR |
---|
| 690 | attr = *pte2_ptr; |
---|
| 691 | |
---|
| 692 | // check PTE2 present and locked |
---|
[401] | 693 | if( ((attr & TSAR_MMU_MAPPED) == 0) || ((attr & TSAR_MMU_LOCKED) == 0) ); |
---|
[1] | 694 | { |
---|
[401] | 695 | printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n", |
---|
[1] | 696 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 697 | return EINVAL; |
---|
| 698 | } |
---|
| 699 | |
---|
| 700 | // reset GPT_LOCK |
---|
[401] | 701 | *pte2_ptr = attr & ~TSAR_MMU_LOCKED; |
---|
[1] | 702 | |
---|
| 703 | return 0; |
---|
[401] | 704 | |
---|
[1] | 705 | } // end hal_gpt_unlock_pte() |
---|
| 706 | |
---|
[408] | 707 | /////////////////////////////////////////// |
---|
| 708 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
| 709 | xptr_t src_gpt_xp, |
---|
| 710 | vpn_t vpn, |
---|
| 711 | bool_t cow, |
---|
| 712 | ppn_t * ppn, |
---|
| 713 | bool_t * mapped ) |
---|
[23] | 714 | { |
---|
| 715 | uint32_t ix1; // index in PT1 |
---|
| 716 | uint32_t ix2; // index in PT2 |
---|
[1] | 717 | |
---|
[408] | 718 | cxy_t src_cxy; // SRC GPT cluster |
---|
| 719 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
[1] | 720 | |
---|
[408] | 721 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
| 722 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
| 723 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
| 724 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
| 725 | |
---|
[407] | 726 | kmem_req_t req; // for dynamic PT2 allocation |
---|
| 727 | |
---|
| 728 | uint32_t src_pte1; |
---|
| 729 | uint32_t dst_pte1; |
---|
| 730 | |
---|
[408] | 731 | uint32_t src_pte2_attr; |
---|
| 732 | uint32_t src_pte2_ppn; |
---|
[1] | 733 | |
---|
[23] | 734 | page_t * page; |
---|
[315] | 735 | xptr_t page_xp; |
---|
[1] | 736 | |
---|
[23] | 737 | ppn_t src_pt2_ppn; |
---|
| 738 | ppn_t dst_pt2_ppn; |
---|
[1] | 739 | |
---|
[408] | 740 | gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn %x\n", |
---|
| 741 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn ); |
---|
[407] | 742 | |
---|
[408] | 743 | // get remote src_gpt cluster and local pointer |
---|
| 744 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
| 745 | src_gpt = (gpt_t *)GET_PTR( src_gpt_xp ); |
---|
[407] | 746 | |
---|
[408] | 747 | // get remote src_pt1 and local dst_pt1 |
---|
| 748 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
[23] | 749 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 750 | |
---|
[408] | 751 | // check src_pt1 and dst_pt1 existence |
---|
| 752 | assert( (src_pt1 != NULL) , __FUNCTION__ , "src_pt1 does not exist\n"); |
---|
| 753 | assert( (dst_pt1 != NULL) , __FUNCTION__ , "dst_pt1 does not exist\n"); |
---|
[407] | 754 | |
---|
[408] | 755 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 756 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[407] | 757 | |
---|
[408] | 758 | // get src_pte1 |
---|
| 759 | src_pte1 = hal_remote_lw( XPTR( src_cxy , &src_pt1[ix1] ) ); |
---|
[407] | 760 | |
---|
[408] | 761 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
| 762 | if( (src_pte1 & TSAR_MMU_MAPPED) && (src_pte1 & TSAR_MMU_SMALL) ) |
---|
| 763 | { |
---|
| 764 | // get dst_pt1 entry |
---|
| 765 | dst_pte1 = dst_pt1[ix1]; |
---|
[407] | 766 | |
---|
[408] | 767 | // map dst_pte1 if required |
---|
| 768 | if( (dst_pte1 & TSAR_MMU_MAPPED) == 0 ) |
---|
| 769 | { |
---|
| 770 | // allocate one physical page for a new PT2 |
---|
| 771 | req.type = KMEM_PAGE; |
---|
| 772 | req.size = 0; // 1 small page |
---|
| 773 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 774 | page = (page_t *)kmem_alloc( &req ); |
---|
[407] | 775 | |
---|
[408] | 776 | if( page == NULL ) |
---|
| 777 | { |
---|
| 778 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 779 | return -1; |
---|
| 780 | } |
---|
[407] | 781 | |
---|
[408] | 782 | // build extended pointer on page descriptor |
---|
| 783 | page_xp = XPTR( local_cxy , page ); |
---|
[407] | 784 | |
---|
[408] | 785 | // get PPN for this new PT2 |
---|
| 786 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
[407] | 787 | |
---|
[408] | 788 | // build the new dst_pte1 |
---|
| 789 | dst_pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn; |
---|
[407] | 790 | |
---|
[408] | 791 | // register it in DST_GPT |
---|
| 792 | dst_pt1[ix1] = dst_pte1; |
---|
| 793 | } |
---|
[407] | 794 | |
---|
[408] | 795 | // get pointer on src_pt2 |
---|
| 796 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 ); |
---|
| 797 | src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[407] | 798 | |
---|
[408] | 799 | // get pointer on dst_pt2 |
---|
| 800 | dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 ); |
---|
| 801 | dst_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
[407] | 802 | |
---|
[408] | 803 | // get attr and ppn from SRC_PT2 |
---|
| 804 | src_pte2_attr = hal_remote_lw( XPTR( src_cxy , &src_pt2[2 * ix2] ) ); |
---|
| 805 | src_pte2_ppn = hal_remote_lw( XPTR( src_cxy , &src_pt2[2 * ix2 + 1] ) ); |
---|
[407] | 806 | |
---|
[408] | 807 | // do nothing if src_pte2 not MAPPED |
---|
| 808 | if( (src_pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
---|
| 809 | { |
---|
| 810 | // set PPN in DST PTE2 |
---|
| 811 | dst_pt2[2*ix2+1] = src_pte2_ppn; |
---|
| 812 | |
---|
| 813 | // set attributes in DST PTE2 |
---|
| 814 | if( cow && (src_pte2_attr & TSAR_MMU_WRITABLE) ) |
---|
[407] | 815 | { |
---|
[408] | 816 | dst_pt2[2*ix2] = (src_pte2_attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); |
---|
| 817 | } |
---|
| 818 | else |
---|
| 819 | { |
---|
| 820 | dst_pt2[2*ix2] = src_pte2_attr; |
---|
| 821 | } |
---|
[407] | 822 | |
---|
[408] | 823 | // return "successfully copied" |
---|
| 824 | *mapped = true; |
---|
| 825 | *ppn = src_pte2_ppn; |
---|
| 826 | |
---|
| 827 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit for vpn %x / copy done\n", |
---|
| 828 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn ); |
---|
[407] | 829 | |
---|
[408] | 830 | hal_fence(); |
---|
[407] | 831 | |
---|
[408] | 832 | return 0; |
---|
| 833 | } // end if PTE2 mapped |
---|
| 834 | } // end if PTE1 mapped |
---|
| 835 | |
---|
| 836 | // return "nothing done" |
---|
| 837 | *mapped = false; |
---|
| 838 | *ppn = 0; |
---|
| 839 | |
---|
| 840 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit for vpn %x / nothing done\n", |
---|
| 841 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn ); |
---|
| 842 | |
---|
[407] | 843 | hal_fence(); |
---|
| 844 | |
---|
| 845 | return 0; |
---|
| 846 | |
---|
[408] | 847 | } // end hal_gpt_pte_copy() |
---|
[407] | 848 | |
---|
[408] | 849 | ////////////////////////////////////////// |
---|
| 850 | bool_t hal_gpt_pte_is_mapped( gpt_t * gpt, |
---|
| 851 | vpn_t vpn ) |
---|
| 852 | { |
---|
| 853 | uint32_t * pt1; |
---|
| 854 | uint32_t pte1; |
---|
| 855 | uint32_t pte2_attr; |
---|
| 856 | |
---|
| 857 | uint32_t * pt2; |
---|
| 858 | ppn_t pt2_ppn; |
---|
| 859 | |
---|
| 860 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 861 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 862 | |
---|
| 863 | // get PTE1 value |
---|
| 864 | pt1 = gpt->ptr; |
---|
| 865 | pte1 = pt1[ix1]; |
---|
| 866 | |
---|
| 867 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 868 | |
---|
| 869 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) return false; |
---|
| 870 | |
---|
| 871 | // compute PT2 base address |
---|
| 872 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 873 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
| 874 | |
---|
| 875 | // get pte2_attr |
---|
| 876 | pte2_attr = pt2[2*ix2]; |
---|
| 877 | |
---|
| 878 | if( (pte2_attr & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 879 | else return true; |
---|
| 880 | |
---|
| 881 | } // end hal_gpt_pte_is_mapped() |
---|
| 882 | |
---|
[407] | 883 | /////////////////////////////////////// |
---|
| 884 | bool_t hal_gpt_pte_is_cow( gpt_t * gpt, |
---|
| 885 | vpn_t vpn ) |
---|
| 886 | { |
---|
| 887 | uint32_t * pt1; |
---|
| 888 | uint32_t pte1; |
---|
[408] | 889 | uint32_t pte2_attr; |
---|
[407] | 890 | |
---|
| 891 | uint32_t * pt2; |
---|
| 892 | ppn_t pt2_ppn; |
---|
| 893 | |
---|
| 894 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 895 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 896 | |
---|
| 897 | // get PTE1 value |
---|
| 898 | pt1 = gpt->ptr; |
---|
| 899 | pte1 = pt1[ix1]; |
---|
| 900 | |
---|
[408] | 901 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
[407] | 902 | |
---|
[408] | 903 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) return false; |
---|
[407] | 904 | |
---|
[408] | 905 | // compute PT2 base address |
---|
| 906 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 907 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
| 908 | |
---|
| 909 | // get pte2_attr |
---|
| 910 | pte2_attr = pt2[2*ix2]; |
---|
| 911 | |
---|
| 912 | if( (pte2_attr & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 913 | |
---|
| 914 | if( (pte2_attr & TSAR_MMU_COW) == 0 ) return false; |
---|
| 915 | else return true; |
---|
| 916 | |
---|
[407] | 917 | } // end hal_gpt_pte_is_cow() |
---|
| 918 | |
---|
[408] | 919 | ///////////////////////////////////////// |
---|
| 920 | void hal_gpt_flip_cow( bool_t set_cow, |
---|
| 921 | xptr_t gpt_xp, |
---|
| 922 | vpn_t vpn_base, |
---|
| 923 | vpn_t vpn_size ) |
---|
| 924 | { |
---|
| 925 | cxy_t gpt_cxy; |
---|
| 926 | gpt_t * gpt_ptr; |
---|
[407] | 927 | |
---|
[408] | 928 | vpn_t vpn; |
---|
[407] | 929 | |
---|
[408] | 930 | uint32_t ix1; |
---|
| 931 | uint32_t ix2; |
---|
[407] | 932 | |
---|
[408] | 933 | uint32_t * pt1; |
---|
| 934 | uint32_t pte1; |
---|
[407] | 935 | |
---|
[408] | 936 | uint32_t * pt2; |
---|
| 937 | ppn_t pt2_ppn; |
---|
[407] | 938 | |
---|
[408] | 939 | uint32_t old_attr; |
---|
| 940 | uint32_t new_attr; |
---|
[407] | 941 | |
---|
[408] | 942 | // get GPT cluster and local pointer |
---|
| 943 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 944 | gpt_ptr = (gpt_t *)GET_PTR( gpt_xp ); |
---|
[407] | 945 | |
---|
[408] | 946 | // get local PT1 pointer |
---|
| 947 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[407] | 948 | |
---|
[408] | 949 | // loop on pages |
---|
| 950 | for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ ) |
---|
| 951 | { |
---|
| 952 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 953 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[407] | 954 | |
---|
[408] | 955 | // get PTE1 value |
---|
| 956 | pte1 = hal_remote_lw( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[407] | 957 | |
---|
[408] | 958 | // only MAPPED & SMALL PTEs are modified |
---|
| 959 | if( (pte1 & TSAR_MMU_MAPPED) && (pte1 & TSAR_MMU_SMALL) ) |
---|
| 960 | { |
---|
| 961 | // compute PT2 base address |
---|
| 962 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 963 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[407] | 964 | |
---|
[408] | 965 | assert( (GET_CXY( ppm_ppn2base( pt2_ppn ) ) == gpt_cxy ), __FUNCTION__, |
---|
| 966 | "PT2 and PT1 must be in the same cluster\n"); |
---|
| 967 | |
---|
| 968 | // get current PTE2 attributes |
---|
| 969 | old_attr = hal_remote_lw( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
---|
| 970 | |
---|
| 971 | // only MAPPED PTEs are modified |
---|
| 972 | if( old_attr & TSAR_MMU_MAPPED ) |
---|
[23] | 973 | { |
---|
[408] | 974 | if( (set_cow != 0) && (old_attr & TSAR_MMU_WRITABLE) ) |
---|
| 975 | { |
---|
| 976 | new_attr = (old_attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); |
---|
| 977 | hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , new_attr ); |
---|
[23] | 978 | } |
---|
[408] | 979 | if( (set_cow == 0) && (old_attr & TSAR_MMU_COW ) ) |
---|
| 980 | { |
---|
| 981 | new_attr = (old_attr | TSAR_MMU_WRITABLE) & (~TSAR_MMU_COW); |
---|
| 982 | hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , new_attr ); |
---|
| 983 | } |
---|
| 984 | } // end if PTE2 mapped |
---|
| 985 | } // end if PTE1 mapped |
---|
| 986 | } // end loop on pages |
---|
[23] | 987 | |
---|
[408] | 988 | } // end hal_gpt_flip_cow() |
---|
[315] | 989 | |
---|
[408] | 990 | ////////////////////////////////////////// |
---|
| 991 | void hal_gpt_update_pte( xptr_t gpt_xp, |
---|
| 992 | vpn_t vpn, |
---|
| 993 | uint32_t attr, // generic GPT attributes |
---|
| 994 | ppn_t ppn ) |
---|
| 995 | { |
---|
| 996 | uint32_t * pt1; // PT1 base addres |
---|
| 997 | uint32_t pte1; // PT1 entry value |
---|
[23] | 998 | |
---|
[408] | 999 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 1000 | uint32_t * pt2; // PT2 base address |
---|
[23] | 1001 | |
---|
[408] | 1002 | uint32_t ix1; // index in PT1 |
---|
| 1003 | uint32_t ix2; // index in PT2 |
---|
[23] | 1004 | |
---|
[408] | 1005 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[23] | 1006 | |
---|
[408] | 1007 | // check attr argument MAPPED and SMALL |
---|
| 1008 | if( (attr & GPT_MAPPED) == 0 ) return; |
---|
| 1009 | if( (attr & GPT_SMALL ) == 0 ) return; |
---|
[23] | 1010 | |
---|
[408] | 1011 | // get cluster and local pointer on remote GPT |
---|
| 1012 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 1013 | gpt_t * gpt_ptr = (gpt_t *)GET_PTR( gpt_xp ); |
---|
[23] | 1014 | |
---|
[408] | 1015 | // compute indexes in PT1 and PT2 |
---|
| 1016 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1017 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[23] | 1018 | |
---|
[408] | 1019 | // get PT1 base |
---|
| 1020 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[23] | 1021 | |
---|
[408] | 1022 | // compute tsar_attr from generic attributes |
---|
| 1023 | tsar_attr = gpt2tsar( attr ); |
---|
[23] | 1024 | |
---|
[408] | 1025 | // get PTE1 value |
---|
| 1026 | pte1 = hal_remote_lw( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[23] | 1027 | |
---|
[408] | 1028 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return; |
---|
| 1029 | if( (pte1 & TSAR_MMU_SMALL ) == 0 ) return; |
---|
| 1030 | |
---|
| 1031 | // get PT2 base from PTE1 |
---|
| 1032 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 1033 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
| 1034 | |
---|
| 1035 | // reset PTE2 |
---|
| 1036 | hal_remote_sw( XPTR( gpt_cxy, &pt2[2 * ix2] ) , 0 ); |
---|
| 1037 | hal_fence(); |
---|
| 1038 | |
---|
| 1039 | // set PTE2 in this order |
---|
| 1040 | hal_remote_sw( XPTR( gpt_cxy, &pt2[2 * ix2 + 1] ) , ppn ); |
---|
| 1041 | hal_fence(); |
---|
| 1042 | hal_remote_sw( XPTR( gpt_cxy, &pt2[2 * ix2] ) , tsar_attr ); |
---|
| 1043 | hal_fence(); |
---|
| 1044 | |
---|
| 1045 | } // end hal_gpt_update_pte() |
---|
| 1046 | |
---|