1 | /* |
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2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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3 | * |
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4 | * Author Alain Greiner (2016) |
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5 | * |
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6 | * Copyright (c) UPMC Sorbonne Universites |
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7 | * |
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8 | * This file is part of ALMOS-MKH. |
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9 | * |
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10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License as published by |
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12 | * the Free Software Foundation; version 2.0 of the License. |
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13 | * |
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14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU General Public License |
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20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 | */ |
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23 | |
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24 | #include <hal_types.h> |
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25 | #include <hal_gpt.h> |
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26 | #include <hal_special.h> |
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27 | #include <printk.h> |
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28 | #include <bits.h> |
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29 | #include <process.h> |
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30 | #include <kmem.h> |
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31 | #include <thread.h> |
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32 | #include <cluster.h> |
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33 | #include <ppm.h> |
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34 | #include <page.h> |
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35 | |
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36 | //////////////////////////////////////////////////////////////////////////////////////// |
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37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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38 | //////////////////////////////////////////////////////////////////////////////////////// |
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39 | |
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40 | #define TSAR_MMU_MAPPED 0x80000000 |
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41 | #define TSAR_MMU_SMALL 0x40000000 |
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42 | #define TSAR_MMU_LOCAL 0x20000000 |
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43 | #define TSAR_MMU_REMOTE 0x10000000 |
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44 | #define TSAR_MMU_CACHABLE 0x08000000 |
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45 | #define TSAR_MMU_WRITABLE 0x04000000 |
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46 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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47 | #define TSAR_MMU_USER 0x01000000 |
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48 | #define TSAR_MMU_GLOBAL 0x00800000 |
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49 | #define TSAR_MMU_DIRTY 0x00400000 |
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50 | |
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51 | #define TSAR_MMU_COW 0x00000001 // only for small pages |
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52 | #define TSAR_MMU_SWAP 0x00000004 // only for small pages |
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53 | #define TSAR_MMU_LOCKED 0x00000008 // only for small pages |
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54 | |
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55 | //////////////////////////////////////////////////////////////////////////////////////// |
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56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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57 | // - IX1 on 11 bits |
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58 | // - IX2 on 9 bits |
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59 | // - PPN on 28 bits |
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60 | //////////////////////////////////////////////////////////////////////////////////////// |
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61 | |
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62 | #define TSAR_MMU_IX1_WIDTH 11 |
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63 | #define TSAR_MMU_IX2_WIDTH 9 |
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64 | #define TSAR_MMU_PPN_WIDTH 28 |
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65 | |
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66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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68 | |
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69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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71 | |
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72 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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73 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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75 | |
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76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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78 | |
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79 | |
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80 | /////////////////////////////////////////////////////////////////////////////////////// |
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81 | // This static function translates the GPT attributes to the TSAR attributes |
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82 | /////////////////////////////////////////////////////////////////////////////////////// |
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83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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84 | { |
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85 | uint32_t tsar_attr = 0; |
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86 | |
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87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_MMU_MAPPED; |
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88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_MMU_SMALL; |
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89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_MMU_WRITABLE; |
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90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_MMU_EXECUTABLE; |
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91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_MMU_CACHABLE; |
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92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_MMU_USER; |
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93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_MMU_DIRTY; |
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94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_MMU_LOCAL; |
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95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_MMU_GLOBAL; |
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96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_MMU_COW; |
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97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_MMU_SWAP; |
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98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_MMU_LOCKED; |
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99 | |
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100 | return tsar_attr; |
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101 | } |
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102 | |
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103 | /////////////////////////////////////////////////////////////////////////////////////// |
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104 | // This static function translates the TSAR attributes to the GPT attributes |
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105 | /////////////////////////////////////////////////////////////////////////////////////// |
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106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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107 | { |
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108 | uint32_t gpt_attr = 0; |
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109 | |
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110 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_MAPPED; |
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111 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_READABLE; |
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112 | if( tsar_attr & TSAR_MMU_SMALL ) gpt_attr |= GPT_SMALL; |
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113 | if( tsar_attr & TSAR_MMU_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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114 | if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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115 | if( tsar_attr & TSAR_MMU_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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116 | if( tsar_attr & TSAR_MMU_USER ) gpt_attr |= GPT_USER; |
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117 | if( tsar_attr & TSAR_MMU_DIRTY ) gpt_attr |= GPT_DIRTY; |
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118 | if( tsar_attr & TSAR_MMU_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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119 | if( tsar_attr & TSAR_MMU_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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120 | if( tsar_attr & TSAR_MMU_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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121 | if( tsar_attr & TSAR_MMU_COW ) gpt_attr |= GPT_COW; |
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122 | if( tsar_attr & TSAR_MMU_SWAP ) gpt_attr |= GPT_SWAP; |
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123 | if( tsar_attr & TSAR_MMU_LOCKED ) gpt_attr |= GPT_LOCKED; |
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124 | |
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125 | return gpt_attr; |
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126 | } |
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127 | |
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128 | ///////////////////////////////////// |
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129 | error_t hal_gpt_create( gpt_t * gpt ) |
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130 | { |
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131 | page_t * page; |
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132 | xptr_t page_xp; |
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133 | vpn_t vpn; |
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134 | error_t error; |
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135 | uint32_t attr; |
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136 | |
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137 | gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n", |
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138 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid ); |
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139 | |
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140 | // check page size |
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141 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , __FUNCTION__ , |
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142 | "for TSAR, the page must be 4 Kbytes\n" ); |
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143 | |
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144 | // allocates 2 physical pages for PT1 |
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145 | kmem_req_t req; |
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146 | req.type = KMEM_PAGE; |
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147 | req.size = 1; // 2 small pages |
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148 | req.flags = AF_KERNEL | AF_ZERO; |
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149 | page = (page_t *)kmem_alloc( &req ); |
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150 | |
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151 | if( page == NULL ) |
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152 | { |
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153 | printk("\n[ERROR] in %s : cannot allocate memory for PT1\n", __FUNCTION__ ); |
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154 | return ENOMEM; |
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155 | } |
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156 | |
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157 | // initialize generic page table descriptor |
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158 | page_xp = XPTR( local_cxy , page ); |
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159 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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160 | gpt->ppn = ppm_page2ppn( page_xp ); |
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161 | |
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162 | // identity map the kentry_vseg (must exist for all processes) |
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163 | attr = GPT_MAPPED | GPT_SMALL | GPT_EXECUTABLE | GPT_CACHABLE | GPT_GLOBAL; |
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164 | for( vpn = CONFIG_VMM_KENTRY_BASE; |
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165 | vpn < (CONFIG_VMM_KENTRY_BASE + CONFIG_VMM_KENTRY_SIZE); vpn++ ) |
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166 | { |
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167 | |
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168 | gpt_dmsg("\n[DBG] %s : identity map vpn %d\n", __FUNCTION__ , vpn ); |
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169 | |
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170 | error = hal_gpt_set_pte( gpt, |
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171 | vpn, |
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172 | (local_cxy<<20) | (vpn & 0xFFFFF), |
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173 | attr ); |
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174 | |
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175 | if( error ) |
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176 | { |
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177 | printk("\n[ERROR] in %s : cannot identity map kentry vseg\n", __FUNCTION__ ); |
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178 | return ENOMEM; |
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179 | } |
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180 | } |
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181 | |
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182 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n", |
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183 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid ); |
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184 | |
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185 | return 0; |
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186 | |
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187 | } // end hal_gpt_create() |
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188 | |
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189 | |
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190 | /////////////////////////////////// |
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191 | void hal_gpt_destroy( gpt_t * gpt ) |
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192 | { |
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193 | uint32_t ix1; |
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194 | uint32_t ix2; |
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195 | uint32_t * pt1; |
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196 | uint32_t pte1; |
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197 | ppn_t pt2_ppn; |
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198 | uint32_t * pt2; |
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199 | uint32_t attr; |
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200 | vpn_t vpn; |
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201 | kmem_req_t req; |
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202 | bool_t is_ref; |
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203 | |
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204 | // get pointer on calling process |
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205 | process_t * process = CURRENT_THREAD->process; |
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206 | |
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207 | // compute is_ref |
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208 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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209 | |
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210 | // get pointer on PT1 |
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211 | pt1 = (uint32_t *)gpt->ptr; |
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212 | |
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213 | // scan the PT1 |
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214 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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215 | { |
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216 | pte1 = pt1[ix1]; |
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217 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) // PTE1 valid |
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218 | { |
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219 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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220 | { |
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221 | if( (pte1 & TSAR_MMU_USER) != 0 ) |
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222 | { |
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223 | // warning message |
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224 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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225 | __FUNCTION__ , ix1 ); |
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226 | |
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227 | // release the big physical page if reference cluster |
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228 | if( is_ref ) |
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229 | { |
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230 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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231 | hal_gpt_reset_pte( gpt , vpn ); |
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232 | } |
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233 | } |
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234 | } |
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235 | else // SMALL page |
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236 | { |
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237 | // get local pointer on PT2 |
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238 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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239 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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240 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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241 | |
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242 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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243 | if( is_ref ) |
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244 | { |
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245 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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246 | { |
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247 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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248 | if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) ) |
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249 | { |
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250 | // release the physical page |
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251 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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252 | hal_gpt_reset_pte( gpt , vpn ); |
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253 | } |
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254 | } |
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255 | } |
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256 | |
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257 | // release the PT2 |
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258 | req.type = KMEM_PAGE; |
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259 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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260 | kmem_free( &req ); |
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261 | } |
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262 | } |
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263 | } |
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264 | |
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265 | // release the PT1 |
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266 | req.type = KMEM_PAGE; |
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267 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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268 | kmem_free( &req ); |
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269 | |
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270 | } // end hal_gpt_destroy() |
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271 | |
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272 | /////////////////////////////////////////// |
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273 | void hal_gpt_display( process_t * process ) |
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274 | { |
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275 | gpt_t * gpt; |
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276 | uint32_t ix1; |
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277 | uint32_t ix2; |
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278 | uint32_t * pt1; |
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279 | uint32_t pte1; |
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280 | ppn_t pt2_ppn; |
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281 | uint32_t * pt2; |
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282 | uint32_t pte2_attr; |
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283 | ppn_t pte2_ppn; |
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284 | vpn_t vpn; |
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285 | |
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286 | assert( (process != NULL) , __FUNCTION__ , "NULL process pointer\n"); |
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287 | |
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288 | // get pointer on gpt |
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289 | gpt = &(process->vmm.gpt); |
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290 | |
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291 | // get pointer on PT1 |
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292 | pt1 = (uint32_t *)gpt->ptr; |
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293 | |
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294 | printk("\n***** Generic Page Table for process %x : &gpt = %x / &pt1 = %x\n\n", |
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295 | process->pid , gpt , pt1 ); |
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296 | |
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297 | // scan the PT1 |
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298 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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299 | { |
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300 | pte1 = pt1[ix1]; |
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301 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
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302 | { |
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303 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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304 | { |
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305 | vpn = ix1 << 9; |
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306 | printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 ); |
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307 | } |
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308 | else // SMALL pages |
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309 | { |
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310 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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311 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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312 | pt2 = (uint32_t *)GET_PTR( base_xp ); |
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313 | |
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314 | // scan the PT2 |
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315 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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316 | { |
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317 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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318 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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319 | |
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320 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
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321 | { |
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322 | vpn = (ix1 << 9) | ix2; |
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323 | printk(" - SMALL : vpn = %x / PT2[%d] = %x / pt2[%d] = %x\n", |
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324 | vpn , 2*ix2 , pte2_attr , 2*ix2+1 , pte2_ppn ); |
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325 | } |
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326 | } |
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327 | } |
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328 | } |
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329 | } |
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330 | } // end hal_gpt_display() |
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331 | |
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332 | |
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333 | /////////////////////////////////////// |
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334 | error_t hal_gpt_set_pte( gpt_t * gpt, |
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335 | vpn_t vpn, |
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336 | ppn_t ppn, |
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337 | uint32_t attr ) // generic GPT attributes |
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338 | { |
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339 | uint32_t * pt1; // PT1 base addres |
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340 | uint32_t * pte1_ptr; // pointer on PT1 entry |
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341 | uint32_t pte1; // PT1 entry value |
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342 | |
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343 | ppn_t pt2_ppn; // PPN of PT2 |
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344 | uint32_t * pt2; // PT2 base address |
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345 | |
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346 | uint32_t small; // requested PTE is for a small page |
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347 | bool_t success; // exit condition for while loop below |
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348 | |
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349 | page_t * page; // pointer on new physical page descriptor |
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350 | xptr_t page_xp; // extended pointer on new page descriptor |
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351 | |
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352 | uint32_t ix1; // index in PT1 |
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353 | uint32_t ix2; // index in PT2 |
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354 | |
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355 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
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356 | |
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357 | gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n", |
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358 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , ppn , attr ); |
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359 | |
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360 | // compute indexes in PT1 and PT2 |
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361 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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362 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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363 | |
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364 | pt1 = gpt->ptr; |
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365 | small = attr & GPT_SMALL; |
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366 | |
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367 | // compute tsar_attr from generic attributes |
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368 | tsar_attr = gpt2tsar( attr ); |
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369 | |
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370 | gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n", |
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371 | __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pt1 , tsar_attr ); |
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372 | |
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373 | // get pointer on PT1[ix1] |
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374 | pte1_ptr = &pt1[ix1]; |
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375 | |
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376 | // PTE1 (big page) are only set for the kernel vsegs, in the kernel init phase. |
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377 | // There is no risk of concurrent access. |
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378 | if( small == 0 ) |
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379 | { |
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380 | // get current pte1 value |
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381 | pte1 = *pte1_ptr; |
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382 | |
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383 | assert( (pte1 == 0) , __FUNCTION__ , |
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384 | "try to set a big page in a mapped PT1 entry / PT1[%d] = %x\n", ix1 , pte1 ); |
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385 | |
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386 | // set the PTE1 |
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387 | *pte1_ptr = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | |
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388 | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
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389 | hal_fence(); |
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390 | return 0; |
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391 | } |
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392 | |
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393 | // From this point, the requested PTE is a PTE2 (small page) |
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394 | |
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395 | // loop to access PTE1 and get pointer on PT2 |
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396 | success = false; |
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397 | do |
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398 | { |
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399 | // get current pte1 value |
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400 | pte1 = *pte1_ptr; |
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401 | |
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402 | gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n", |
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403 | __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 ); |
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404 | |
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405 | // allocate a PT2 if PT1 entry not valid |
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406 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not valid |
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407 | { |
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408 | // allocate one physical page for the PT2 |
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409 | kmem_req_t req; |
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410 | req.type = KMEM_PAGE; |
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411 | req.size = 0; // 1 small page |
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412 | req.flags = AF_KERNEL | AF_ZERO; |
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413 | page = (page_t *)kmem_alloc( &req ); |
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414 | if( page == NULL ) |
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415 | { |
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416 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
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417 | return ENOMEM; |
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418 | } |
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419 | |
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420 | // get the PT2 PPN |
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421 | page_xp = XPTR( local_cxy , page ); |
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422 | pt2_ppn = ppm_page2ppn( page_xp ); |
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423 | |
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424 | // try to atomicaly set the PT1 entry |
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425 | pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn; |
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426 | success = hal_atomic_cas( pte1_ptr , 0 , pte1 ); |
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427 | |
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428 | // release allocated PT2 if PT1 entry modified by another thread |
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429 | if( success == false ) ppm_free_pages( page ); |
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430 | } |
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431 | else // PT1 entry is valid |
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432 | { |
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433 | // This valid entry must be a PTD1 |
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434 | assert( (pte1 & TSAR_MMU_SMALL) , __FUNCTION__ , |
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435 | "try to set a small page in a big PT1 entry / PT1[%d] = %x\n", ix1 , pte1 ); |
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436 | |
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437 | success = true; |
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438 | } |
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439 | |
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440 | // get PT2 base from pte1 |
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441 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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442 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
443 | |
---|
444 | gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n", |
---|
445 | __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 , pt2 ); |
---|
446 | |
---|
447 | } |
---|
448 | while (success == false); |
---|
449 | |
---|
450 | // set PTE2 in this order |
---|
451 | pt2[2 * ix2 + 1] = ppn; |
---|
452 | hal_fence(); |
---|
453 | pt2[2 * ix2] = tsar_attr; |
---|
454 | hal_fence(); |
---|
455 | |
---|
456 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n", |
---|
457 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , |
---|
458 | pt2[2 * ix2] , pt2[2 * ix2 + 1] ); |
---|
459 | |
---|
460 | return 0; |
---|
461 | |
---|
462 | } // end of hal_gpt_set_pte() |
---|
463 | |
---|
464 | |
---|
465 | ///////////////////////////////////// |
---|
466 | void hal_gpt_get_pte( gpt_t * gpt, |
---|
467 | vpn_t vpn, |
---|
468 | uint32_t * attr, |
---|
469 | ppn_t * ppn ) |
---|
470 | { |
---|
471 | uint32_t * pt1; |
---|
472 | uint32_t pte1; |
---|
473 | |
---|
474 | uint32_t * pt2; |
---|
475 | ppn_t pt2_ppn; |
---|
476 | |
---|
477 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
478 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
479 | |
---|
480 | // get PTE1 value |
---|
481 | pt1 = gpt->ptr; |
---|
482 | pte1 = pt1[ix1]; |
---|
483 | |
---|
484 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
485 | { |
---|
486 | *attr = 0; |
---|
487 | *ppn = 0; |
---|
488 | } |
---|
489 | |
---|
490 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
491 | { |
---|
492 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
493 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
494 | } |
---|
495 | else // it's a PTD1 |
---|
496 | { |
---|
497 | // compute PT2 base address |
---|
498 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
499 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
500 | |
---|
501 | *ppn = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
502 | *attr = tsar2gpt( pt2[2*ix2] ); |
---|
503 | } |
---|
504 | } // end hal_gpt_get_pte() |
---|
505 | |
---|
506 | //////////////////////////////////// |
---|
507 | void hal_gpt_reset_pte( gpt_t * gpt, |
---|
508 | vpn_t vpn ) |
---|
509 | { |
---|
510 | uint32_t * pt1; // PT1 base address |
---|
511 | uint32_t pte1; // PT1 entry value |
---|
512 | |
---|
513 | ppn_t pt2_ppn; // PPN of PT2 |
---|
514 | uint32_t * pt2; // PT2 base address |
---|
515 | |
---|
516 | ppn_t ppn; // PPN of page to be released |
---|
517 | |
---|
518 | // get ix1 & ix2 indexes |
---|
519 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
520 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
521 | |
---|
522 | // get PTE1 value |
---|
523 | pt1 = gpt->ptr; |
---|
524 | pte1 = pt1[ix1]; |
---|
525 | |
---|
526 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
527 | { |
---|
528 | return; |
---|
529 | } |
---|
530 | |
---|
531 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
532 | { |
---|
533 | // get PPN |
---|
534 | ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
535 | |
---|
536 | // unmap the big page |
---|
537 | pt1[ix1] = 0; |
---|
538 | hal_fence(); |
---|
539 | |
---|
540 | return; |
---|
541 | } |
---|
542 | else // it's a PTD1 |
---|
543 | { |
---|
544 | // compute PT2 base address |
---|
545 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
546 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
547 | |
---|
548 | // get PPN |
---|
549 | ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] ); |
---|
550 | |
---|
551 | // unmap the small page |
---|
552 | pt2[2*ix2] = 0; // only attr is reset |
---|
553 | hal_fence(); |
---|
554 | |
---|
555 | return; |
---|
556 | } |
---|
557 | } // end hal_gpt_reset_pte() |
---|
558 | |
---|
559 | ////////////////////////////////////// |
---|
560 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
---|
561 | vpn_t vpn ) |
---|
562 | { |
---|
563 | uint32_t * pt1; // PT1 base address |
---|
564 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
---|
565 | uint32_t pte1; // value of PT1 entry |
---|
566 | |
---|
567 | uint32_t * pt2; // PT2 base address |
---|
568 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
569 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
---|
570 | |
---|
571 | uint32_t attr; |
---|
572 | bool_t atomic; |
---|
573 | page_t * page; |
---|
574 | xptr_t page_xp; |
---|
575 | |
---|
576 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
577 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
578 | |
---|
579 | // get the PTE1 value |
---|
580 | pt1 = gpt->ptr; |
---|
581 | pte1_ptr = &pt1[ix1]; |
---|
582 | pte1 = *pte1_ptr; |
---|
583 | |
---|
584 | // If present, the page must be small |
---|
585 | if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
586 | { |
---|
587 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
---|
588 | __FUNCTION__ , ix1 , pte1 ); |
---|
589 | return EINVAL; |
---|
590 | } |
---|
591 | |
---|
592 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // missing PT1 entry |
---|
593 | { |
---|
594 | // allocate one physical page for PT2 |
---|
595 | kmem_req_t req; |
---|
596 | req.type = KMEM_PAGE; |
---|
597 | req.size = 0; // 1 small page |
---|
598 | req.flags = AF_KERNEL | AF_ZERO; |
---|
599 | page = (page_t *)kmem_alloc( &req ); |
---|
600 | |
---|
601 | if( page == NULL ) |
---|
602 | { |
---|
603 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
---|
604 | __FUNCTION__ ); |
---|
605 | return ENOMEM; |
---|
606 | } |
---|
607 | |
---|
608 | page_xp = XPTR( local_cxy , page ); |
---|
609 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
610 | pt2 = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) ); |
---|
611 | |
---|
612 | // try to set the PT1 entry |
---|
613 | do |
---|
614 | { |
---|
615 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
---|
616 | TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn ); |
---|
617 | } |
---|
618 | while( (atomic == false) && (*pte1_ptr == 0) ); |
---|
619 | |
---|
620 | if( atomic == false ) // missing PT2 has been allocate by another core |
---|
621 | { |
---|
622 | // release the allocated page |
---|
623 | ppm_free_pages( page ); |
---|
624 | |
---|
625 | // read again the PTE1 |
---|
626 | pte1 = *pte1_ptr; |
---|
627 | |
---|
628 | // get the PT2 base address |
---|
629 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
630 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
631 | } |
---|
632 | } |
---|
633 | else |
---|
634 | { |
---|
635 | // This valid entry must be a PTD1 |
---|
636 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) |
---|
637 | { |
---|
638 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
---|
639 | __FUNCTION__ , ix1 , pte1 ); |
---|
640 | return EINVAL; |
---|
641 | } |
---|
642 | |
---|
643 | // compute PPN of PT2 base |
---|
644 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
645 | |
---|
646 | // compute pointer on PT2 base |
---|
647 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
648 | } |
---|
649 | |
---|
650 | // from here we have the PT2 pointer |
---|
651 | |
---|
652 | // compute pointer on PTE2 |
---|
653 | pte2_ptr = &pt2[2 * ix2]; |
---|
654 | |
---|
655 | // try to atomically lock the PTE2 until success |
---|
656 | do |
---|
657 | { |
---|
658 | // busy waiting until TSAR_MMU_LOCK == 0 |
---|
659 | do |
---|
660 | { |
---|
661 | attr = *pte2_ptr; |
---|
662 | hal_rdbar(); |
---|
663 | } |
---|
664 | while( (attr & TSAR_MMU_LOCKED) != 0 ); |
---|
665 | |
---|
666 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | TSAR_MMU_LOCKED) ); |
---|
667 | } |
---|
668 | while( atomic == 0 ); |
---|
669 | |
---|
670 | return 0; |
---|
671 | |
---|
672 | } // end hal_gpt_lock_pte() |
---|
673 | |
---|
674 | //////////////////////////////////////// |
---|
675 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
---|
676 | vpn_t vpn ) |
---|
677 | { |
---|
678 | uint32_t * pt1; // PT1 base address |
---|
679 | uint32_t pte1; // value of PT1 entry |
---|
680 | |
---|
681 | uint32_t * pt2; // PT2 base address |
---|
682 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
683 | uint32_t * pte2_ptr; // address of PT2 entry |
---|
684 | |
---|
685 | uint32_t attr; // PTE2 attribute |
---|
686 | |
---|
687 | // compute indexes in P1 and PT2 |
---|
688 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
689 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
690 | |
---|
691 | // get pointer on PT1 base |
---|
692 | pt1 = (uint32_t*)gpt->ptr; |
---|
693 | |
---|
694 | // get PTE1 |
---|
695 | pte1 = pt1[ix1]; |
---|
696 | |
---|
697 | // check PTE1 present and small page |
---|
698 | if( ((pte1 & TSAR_MMU_MAPPED) == 0) || ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
699 | { |
---|
700 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
---|
701 | __FUNCTION__ , ix1 , pte1 ); |
---|
702 | return EINVAL; |
---|
703 | } |
---|
704 | |
---|
705 | // get pointer on PT2 base |
---|
706 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
707 | pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
708 | |
---|
709 | // get pointer on PTE2 |
---|
710 | pte2_ptr = &pt2[2 * ix2]; |
---|
711 | |
---|
712 | // get PTE2_ATTR |
---|
713 | attr = *pte2_ptr; |
---|
714 | |
---|
715 | // check PTE2 present and locked |
---|
716 | if( ((attr & TSAR_MMU_MAPPED) == 0) || ((attr & TSAR_MMU_LOCKED) == 0) ); |
---|
717 | { |
---|
718 | printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n", |
---|
719 | __FUNCTION__ , ix1 , pte1 ); |
---|
720 | return EINVAL; |
---|
721 | } |
---|
722 | |
---|
723 | // reset GPT_LOCK |
---|
724 | *pte2_ptr = attr & ~TSAR_MMU_LOCKED; |
---|
725 | |
---|
726 | return 0; |
---|
727 | |
---|
728 | } // end hal_gpt_unlock_pte() |
---|
729 | |
---|
730 | /////////////////////////////////////// |
---|
731 | error_t hal_gpt_copy( gpt_t * dst_gpt, |
---|
732 | gpt_t * src_gpt, |
---|
733 | vpn_t vpn_base, |
---|
734 | vpn_t vpn_size, |
---|
735 | bool_t cow ) |
---|
736 | { |
---|
737 | vpn_t vpn; // current vpn |
---|
738 | |
---|
739 | uint32_t ix1; // index in PT1 |
---|
740 | uint32_t ix2; // index in PT2 |
---|
741 | |
---|
742 | uint32_t * src_pt1; // local pointer on PT1 for SRC_GPT |
---|
743 | uint32_t * dst_pt1; // local pointer on PT1 for DST_GPT |
---|
744 | uint32_t * dst_pt2; // local pointer on PT2 for DST_GPT |
---|
745 | uint32_t * src_pt2; // local pointer on PT2 for SRC_GPT |
---|
746 | |
---|
747 | kmem_req_t req; // for dynamic PT2 allocation |
---|
748 | |
---|
749 | uint32_t src_pte1; |
---|
750 | uint32_t dst_pte1; |
---|
751 | |
---|
752 | uint32_t pte2_attr; |
---|
753 | uint32_t pte2_ppn; |
---|
754 | |
---|
755 | page_t * page; |
---|
756 | xptr_t page_xp; |
---|
757 | |
---|
758 | ppn_t src_pt2_ppn; |
---|
759 | ppn_t dst_pt2_ppn; |
---|
760 | |
---|
761 | gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n", |
---|
762 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid ); |
---|
763 | |
---|
764 | // check page size |
---|
765 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , __FUNCTION__ , |
---|
766 | "for TSAR, the page must be 4 Kbytes\n" ); |
---|
767 | |
---|
768 | // check SRC_PT1 and DST_PT1 existence |
---|
769 | assert( (src_gpt->ptr != NULL) , __FUNCTION__ , "SRC_PT1 does not exist\n"); |
---|
770 | assert( (dst_gpt->ptr != NULL) , __FUNCTION__ , "DST_PT1 does not exist\n"); |
---|
771 | |
---|
772 | // get pointers on SRC_PT1 and DST_PT1 |
---|
773 | src_pt1 = (uint32_t *)src_gpt->ptr; |
---|
774 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
775 | |
---|
776 | // scan pages in vseg |
---|
777 | for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ ) |
---|
778 | { |
---|
779 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
780 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
781 | |
---|
782 | // get SRC_PT1 entry |
---|
783 | src_pte1 = src_pt1[ix1]; |
---|
784 | |
---|
785 | // do nothing if SRC_PTE1 unmapped |
---|
786 | if( (src_pte1 & TSAR_MMU_MAPPED) != 0 ) // SRC_PTE1 is mapped |
---|
787 | { |
---|
788 | assert( (src_pte1 & TSAR_MMU_SMALL) , __FUNCTION__ , |
---|
789 | "no BIG page for user process in TSAR architecture\n" ); |
---|
790 | |
---|
791 | // get DST_PT1 entry |
---|
792 | dst_pte1 = dst_pt1[ix1]; |
---|
793 | |
---|
794 | // map dst_pte1 if required |
---|
795 | if( (dst_pte1 & TSAR_MMU_MAPPED) == 0 ) |
---|
796 | { |
---|
797 | // allocate one physical page for a new DST_PT2 |
---|
798 | req.type = KMEM_PAGE; |
---|
799 | req.size = 0; // 1 small page |
---|
800 | req.flags = AF_KERNEL | AF_ZERO; |
---|
801 | page = (page_t *)kmem_alloc( &req ); |
---|
802 | |
---|
803 | if( page == NULL ) |
---|
804 | { |
---|
805 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
806 | return ENOMEM; |
---|
807 | } |
---|
808 | |
---|
809 | // build extended pointer on page descriptor |
---|
810 | page_xp = XPTR( local_cxy , page ); |
---|
811 | |
---|
812 | // get PPN for this new DST_PT2 |
---|
813 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
814 | |
---|
815 | // build the new dst_pte1 |
---|
816 | dst_pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn; |
---|
817 | |
---|
818 | // register it in DST_GPT |
---|
819 | dst_pt1[ix1] = dst_pte1; |
---|
820 | } |
---|
821 | |
---|
822 | // get PPN and pointer on SRC_PT2 |
---|
823 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 ); |
---|
824 | src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
825 | |
---|
826 | // get PPN and pointer on DST_PT2 |
---|
827 | dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 ); |
---|
828 | dst_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
829 | |
---|
830 | // get attr and ppn from SRC_PT2 |
---|
831 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] ); |
---|
832 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] ); |
---|
833 | |
---|
834 | // no copy if SRC_PTE2 unmapped |
---|
835 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) // valid PTE2 in SRC_GPT |
---|
836 | { |
---|
837 | // set a new PTE2 in DST_PT2 |
---|
838 | dst_pt2[2*ix2] = pte2_attr; |
---|
839 | dst_pt2[2*ix2 + 1] = pte2_ppn; |
---|
840 | |
---|
841 | // FIXME increment page descriptor refcount for the referenced page |
---|
842 | |
---|
843 | // handle Copy-On-Write |
---|
844 | if( cow && (pte2_attr & TSAR_MMU_WRITABLE) ) |
---|
845 | { |
---|
846 | // reset WRITABLE flag in DST_GPT |
---|
847 | hal_atomic_and( &dst_pt2[2*ix2] , ~TSAR_MMU_WRITABLE ); |
---|
848 | |
---|
849 | // set COW flag in DST_GPT |
---|
850 | hal_atomic_or( &dst_pt2[2*ix2] , TSAR_MMU_COW ); |
---|
851 | } |
---|
852 | } |
---|
853 | } // end if PTE1 mapped |
---|
854 | } // end loop on vpn |
---|
855 | |
---|
856 | hal_fence(); |
---|
857 | |
---|
858 | gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n", |
---|
859 | __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid ); |
---|
860 | |
---|
861 | return 0; |
---|
862 | |
---|
863 | } // end hal_gpt_copy() |
---|
864 | |
---|
865 | /////////////////////////////////////// |
---|
866 | bool_t hal_gpt_pte_is_cow( gpt_t * gpt, |
---|
867 | vpn_t vpn ) |
---|
868 | { |
---|
869 | uint32_t * pt1; |
---|
870 | uint32_t pte1; |
---|
871 | |
---|
872 | uint32_t * pt2; |
---|
873 | ppn_t pt2_ppn; |
---|
874 | |
---|
875 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
876 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
877 | |
---|
878 | // get PTE1 value |
---|
879 | pt1 = gpt->ptr; |
---|
880 | pte1 = pt1[ix1]; |
---|
881 | |
---|
882 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not mapped |
---|
883 | { |
---|
884 | return false; |
---|
885 | } |
---|
886 | |
---|
887 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
888 | { |
---|
889 | return false; |
---|
890 | } |
---|
891 | else // it's a PTD1 |
---|
892 | { |
---|
893 | // compute PT2 base address |
---|
894 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
895 | pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
896 | |
---|
897 | if( pt2[2*ix2] & TSAR_MMU_COW ) return true; |
---|
898 | else return false; |
---|
899 | } |
---|
900 | } // end hal_gpt_pte_is_cow() |
---|
901 | |
---|
902 | |
---|
903 | |
---|
904 | |
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905 | |
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906 | |
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907 | |
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908 | |
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909 | |
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910 | |
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911 | |
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912 | |
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913 | /* deprecated : old hal_gpt_copy [AG] |
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914 | |
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915 | // scan the SRC_PT1 |
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916 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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917 | { |
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918 | pte1 = src_pt1[ix1]; |
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919 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
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920 | { |
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921 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // PTE1 => big kernel page |
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922 | { |
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923 | // big kernel pages are shared by all processes => copy it |
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924 | dst_pt1[ix1] = pte1; |
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925 | } |
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926 | else // PTD1 => smal pages |
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927 | { |
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928 | // allocate one physical page for a PT2 in DST_GPT |
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929 | kmem_req_t req; |
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930 | req.type = KMEM_PAGE; |
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931 | req.size = 0; // 1 small page |
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932 | req.flags = AF_KERNEL | AF_ZERO; |
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933 | page = (page_t *)kmem_alloc( &req ); |
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934 | |
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935 | if( page == NULL ) |
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936 | { |
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937 | // TODO release all memory allocated to DST_GPT |
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938 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
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939 | return ENOMEM; |
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940 | } |
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941 | |
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942 | // get extended pointer on page descriptor |
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943 | page_xp = XPTR( local_cxy , page ); |
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944 | |
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945 | // get pointer on new PT2 in DST_GPT |
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946 | xptr_t base_xp = ppm_page2base( page_xp ); |
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947 | dst_pt2 = (uint32_t *)GET_PTR( base_xp ); |
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948 | |
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949 | // set a new PTD1 in DST_GPT |
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950 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
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951 | dst_pt1[ix1] = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn; |
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952 | |
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953 | // get pointer on PT2 in SRC_GPT |
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954 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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955 | src_pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
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956 | |
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957 | // scan the SRC_PT2 |
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958 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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959 | { |
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960 | // get attr & ppn from PTE2 |
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961 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] ); |
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962 | |
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963 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) // valid PTE2 in SRC_GPT |
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964 | { |
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965 | // get GPT_WRITABLE & PPN |
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966 | pte2_writable = pte2_attr & GPT_WRITABLE; |
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967 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( src_pt2[2 * ix2 + 1] ); |
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968 | |
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969 | // set a new PTE2 in DST_GPT |
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970 | dst_pt2[2*ix2] = pte2_attr; |
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971 | dst_pt2[2*ix2 + 1] = pte2_ppn; |
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972 | |
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973 | // handle Copy-On-Write |
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974 | if( cow && pte2_writable ) |
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975 | { |
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976 | // reset GPT_WRITABLE in both SRC_GPT and DST_GPT |
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977 | hal_atomic_and( &dst_pt2[2*ix2] , ~GPT_WRITABLE ); |
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978 | hal_atomic_and( &src_pt2[2*ix2] , ~GPT_WRITABLE ); |
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979 | |
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980 | // register PG_COW in page descriptor |
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981 | page = (page_t *)GET_PTR( ppm_ppn2page( pte2_ppn ) ); |
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982 | hal_atomic_or( &page->flags , PG_COW ); |
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983 | hal_atomic_add( &page->fork_nr , 1 ); |
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984 | } |
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985 | } |
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986 | } // end loop on ix2 |
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987 | } |
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988 | } |
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989 | } // end loop ix1 |
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990 | |
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991 | hal_fence(); |
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992 | |
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993 | return 0; |
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994 | |
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995 | } // end hal_gpt_copy() |
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996 | |
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997 | */ |
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