[1] | 1 | /* |
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| 2 | * hal_special.c - implementation of Generic Special Register Access API for TSAR-MIPS32 |
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| 3 | * |
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[101] | 4 | * Author Alain Greiner (2016,2017) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH.. |
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| 9 | * |
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| 10 | * ALMOS-MKH. is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH. is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | |
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[457] | 25 | #include <hal_kernel_types.h> |
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[1] | 26 | #include <hal_special.h> |
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[101] | 27 | #include <core.h> |
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| 28 | #include <thread.h> |
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[1] | 29 | |
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| 30 | /**** Forward declarations ****/ |
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| 31 | |
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| 32 | struct thread_s; |
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| 33 | |
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[121] | 34 | ////////////////////////// |
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[481] | 35 | inline gid_t hal_get_gid( void ) |
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[1] | 36 | { |
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| 37 | uint32_t proc_id; |
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| 38 | |
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| 39 | asm volatile ("mfc0 %0, $15, 1" : "=&r" (proc_id)); |
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| 40 | |
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[16] | 41 | return (proc_id & 0x3FF); // 4/4/2 format for TSAR |
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[1] | 42 | } |
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| 43 | |
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[296] | 44 | ///////////////////////////// |
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[481] | 45 | inline reg_t hal_time_stamp( void ) |
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[121] | 46 | { |
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[296] | 47 | reg_t count; |
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[121] | 48 | |
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[279] | 49 | asm volatile ("mfc0 %0, $9" : "=&r" (count)); |
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[121] | 50 | |
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| 51 | return count; |
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| 52 | } |
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| 53 | |
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[1] | 54 | ///////////////////////// |
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[481] | 55 | inline reg_t hal_get_sr( void ) |
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[279] | 56 | { |
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[296] | 57 | reg_t sr; |
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[279] | 58 | |
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| 59 | asm volatile ("mfc0 %0, $12" : "=&r" (sr)); |
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| 60 | |
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| 61 | return sr; |
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| 62 | } |
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| 63 | |
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| 64 | ///////////////////////// |
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[481] | 65 | uint64_t hal_get_cycles( void ) |
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[1] | 66 | { |
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[95] | 67 | uint64_t cycles; // absolute time to be returned |
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| 68 | uint32_t last_count; // last registered cycles count |
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| 69 | uint32_t current_count; // current cycles count |
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| 70 | uint32_t elapsed; |
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| 71 | |
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| 72 | core_t * core = CURRENT_THREAD->core; |
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| 73 | |
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| 74 | // get last registered time stamp |
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| 75 | last_count = core->time_stamp; |
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| 76 | |
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| 77 | // get current time stamp from hardware register |
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[121] | 78 | current_count = hal_time_stamp(); |
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[95] | 79 | |
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| 80 | // compute number of elapsed cycles, taking into account 32 bits register wrap |
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| 81 | if(current_count < last_count) elapsed = (0xFFFFFFFF - last_count) + current_count; |
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| 82 | else elapsed = current_count - last_count; |
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| 83 | |
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| 84 | // compute absolute time |
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| 85 | cycles = core->cycles + elapsed; |
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| 86 | |
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| 87 | // update core time |
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| 88 | core->time_stamp = current_count; |
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| 89 | core->cycles = cycles; |
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| 90 | |
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[124] | 91 | hal_fence(); |
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[95] | 92 | |
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[1] | 93 | return cycles; |
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| 94 | } |
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| 95 | |
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[121] | 96 | ///////////////////////////////////////////////// |
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[481] | 97 | inline struct thread_s * hal_get_current_thread( void ) |
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[1] | 98 | { |
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| 99 | void * thread_ptr; |
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| 100 | |
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[279] | 101 | asm volatile ("mfc0 %0, $4, 2" : "=&r" (thread_ptr)); |
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[1] | 102 | |
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| 103 | return thread_ptr; |
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| 104 | } |
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| 105 | |
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| 106 | /////////////////////////////////////////////////////// |
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| 107 | void hal_set_current_thread( struct thread_s * thread ) |
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| 108 | { |
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[279] | 109 | asm volatile ("mtc0 %0, $4, 2" : : "r" (thread)); |
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[1] | 110 | } |
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| 111 | |
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| 112 | ///////////////////// |
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[481] | 113 | void hal_fpu_enable( void ) |
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[1] | 114 | { |
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[459] | 115 | // set CU1 bit (FPU enable) in c0_sr |
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[1] | 116 | asm volatile |
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| 117 | ( ".set noat \n" |
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| 118 | "lui $27, 0x2000 \n" |
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| 119 | "mfc0 $1, $12 \n" |
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| 120 | "or $27, $1, $27 \n" |
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| 121 | "mtc0 $27, $12 \n" |
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| 122 | ".set at \n" ); |
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[459] | 123 | |
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| 124 | // set CU1 bit in calling thread UZONE |
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| 125 | uint32_t * uzone = CURRENT_THREAD->uzone_current; |
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| 126 | uzone[34] |= 0x20000000; |
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[1] | 127 | } |
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| 128 | |
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| 129 | ////////////////////// |
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[481] | 130 | void hal_fpu_disable( void ) |
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[1] | 131 | { |
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[459] | 132 | // reset CU1 bit (FPU enable) in c0_sr |
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[1] | 133 | asm volatile |
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| 134 | ( ".set noat \n" |
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| 135 | "lui $27, 0xDFFF \n" |
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| 136 | "ori $27, $27, 0xFFFF \n" |
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| 137 | "mfc0 $1, $12 \n" |
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| 138 | "and $27, $1, $27 \n" |
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| 139 | "mtc0 $27, $12 \n" |
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| 140 | ".set at \n"); |
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[459] | 141 | |
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| 142 | // reset CU1 bit in calling thread UZONE |
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| 143 | uint32_t * uzone = CURRENT_THREAD->uzone_current; |
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| 144 | uzone[34] &= 0xDFFFFFFF; |
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[1] | 145 | } |
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| 146 | |
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| 147 | //////////////////////// |
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[481] | 148 | uint32_t hal_get_stack( void ) |
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[1] | 149 | { |
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| 150 | register uint32_t sp; |
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| 151 | |
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[279] | 152 | asm volatile ("or %0, $0, $29" : "=&r" (sp)); |
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[1] | 153 | |
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| 154 | return sp; |
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| 155 | } |
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| 156 | |
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| 157 | //////////////////////////////////////// |
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| 158 | uint32_t hal_set_stack( void * new_val ) |
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| 159 | { |
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| 160 | register uint32_t sp; |
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| 161 | |
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| 162 | asm volatile |
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| 163 | ( "or %0, $0, $29 \n" |
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| 164 | "or $29, $0, %1 \n" |
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| 165 | : "=&r" (sp) : "r" (new_val) ); |
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| 166 | |
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| 167 | return sp; |
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| 168 | } |
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| 169 | |
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| 170 | //////////////////////////// |
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[481] | 171 | uint32_t hal_get_bad_vaddr( void ) |
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[1] | 172 | { |
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| 173 | register uint32_t bad_va; |
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| 174 | |
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| 175 | asm volatile |
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| 176 | ( "mfc0 %0, $8 \n" |
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| 177 | : "=&r" (bad_va) ); |
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| 178 | |
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| 179 | return bad_va; |
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| 180 | } |
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| 181 | |
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| 182 | //////////////////////////////////////////// |
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| 183 | uint32_t hal_uncached_read( uint32_t * ptr ) |
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| 184 | { |
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| 185 | register uint32_t val; |
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| 186 | |
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| 187 | asm volatile |
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| 188 | ( "ll %0, (%1) \n" |
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| 189 | : "=&r"(val) : "r" (ptr) ); |
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| 190 | |
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| 191 | return val; |
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| 192 | } |
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| 193 | |
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| 194 | ////////////////////////////////////////// |
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| 195 | void hal_invalid_dcache_line( void * ptr ) |
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| 196 | { |
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| 197 | asm volatile |
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| 198 | ( "cache %0, (%1) \n" |
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| 199 | "sync \n" |
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| 200 | : : "i" (0x11) , "r" (ptr) ); |
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| 201 | } |
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| 202 | |
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[124] | 203 | //////////////// |
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[481] | 204 | void hal_fence( void ) |
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[1] | 205 | { |
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[407] | 206 | asm volatile ("sync"); |
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[1] | 207 | } |
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| 208 | |
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| 209 | //////////////// |
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[481] | 210 | void hal_rdbar( void ) |
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[1] | 211 | { |
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| 212 | asm volatile( "" ::: "memory" ); |
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| 213 | } |
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| 214 | |
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| 215 | ///////////////////// |
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[481] | 216 | void hal_core_sleep( void ) |
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[1] | 217 | { |
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[425] | 218 | while( 1 ) asm volatile ("nop"); |
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[1] | 219 | } |
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| 220 | |
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| 221 | ////////////////////////////////////// |
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| 222 | void hal_fixed_delay( uint32_t delay ) |
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| 223 | { |
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| 224 | asm volatile |
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[407] | 225 | ( ".set noreorder \n" |
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[1] | 226 | "or $27, %0, $0 \n" |
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[407] | 227 | "1: \n" |
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[1] | 228 | "addi $27, $27, -1 \n" |
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[407] | 229 | "nop \n" |
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[1] | 230 | "bne $27, $0, 1b \n" |
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| 231 | "nop \n" |
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[407] | 232 | ".set reorder \n" |
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| 233 | : : "r" (delay>>2) : "$27" ); |
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[1] | 234 | } |
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| 235 | |
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[16] | 236 | ////////////////////////////////////////////////// |
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| 237 | void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code, |
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| 238 | intptr_t * mmu_ins_bad_vaddr, |
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| 239 | intptr_t * mmu_dat_excp_code, |
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| 240 | intptr_t * mmu_dat_bad_vaddr ) |
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| 241 | { |
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| 242 | asm volatile |
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| 243 | ( "mfc2 %0, $11 \n" |
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| 244 | "mfc2 %1, $13 \n" |
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| 245 | "mfc2 %2, $12 \n" |
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| 246 | "mfc2 %3, $14 \n" |
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[406] | 247 | : "=&r"(*mmu_ins_excp_code), |
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| 248 | "=&r"(*mmu_ins_bad_vaddr), |
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| 249 | "=&r"(*mmu_dat_excp_code), |
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| 250 | "=&r"(*mmu_dat_bad_vaddr) ); |
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[16] | 251 | } |
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[406] | 252 | |
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