| [16] | 1 | /* |
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| 2 | * mips32_uzone.h - structures used to save MIPS32 core registers |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef _MIPS32_UZONE_REGS_H_ |
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| 25 | #define _MIPS32_UZONE_REGS_H_ |
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| 26 | |
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| 27 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 28 | // This file defines the MIPS32 specific mnemonics to access the "uzone", that is |
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| 29 | // a fixed size array of 32 bits integers, used by the kentry function to save/restore |
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| 30 | // the MIPS32 CPU registers, at each exception / interruption / syscall. |
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| 31 | // It also defines several initial values for the SR register. |
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| 32 | // |
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| 33 | // This file is included in the TSAR_MIPS32 specific hal_kentry.S, hal_syscall.c, |
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| 34 | // hal_exception.c, and hal_interrupt.c files. |
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| 35 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 36 | |
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| 37 | /**************************************************************************************** |
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| 38 | * This defines SR values for TSAR-MIPS32 |
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| 39 | ***************************************************************************************/ |
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| 40 | |
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| 41 | #define SR_USR_MODE 0xFC11 |
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| 42 | #define SR_USR_MODE_FPU 0x2000FC11 |
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| 43 | #define SR_SYS_MODE 0xFC00 |
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| 44 | |
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| 45 | /**************************************************************************************** |
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| 46 | * This defines the "uzone" mnemonics and size. |
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| 47 | ***************************************************************************************/ |
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| 48 | |
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| 49 | #define UZ_KSP 0 // kernel stack pointer |
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| 50 | #define UZ_AT 1 |
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| 51 | #define UZ_V0 2 |
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| 52 | #define UZ_V1 3 |
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| 53 | #define UZ_A0 4 |
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| 54 | #define UZ_A1 5 |
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| 55 | #define UZ_A2 6 |
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| 56 | #define UZ_A3 7 |
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| 57 | #define UZ_T0 8 |
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| 58 | #define UZ_T1 9 |
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| 59 | #define UZ_T2 10 |
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| 60 | #define UZ_T3 11 |
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| 61 | #define UZ_T4 12 |
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| 62 | #define UZ_T5 13 |
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| 63 | #define UZ_T6 14 |
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| 64 | #define UZ_T7 15 |
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| 65 | #define UZ_T8 16 |
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| 66 | #define UZ_T9 17 |
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| 67 | #define UZ_S0 18 |
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| 68 | #define UZ_S1 19 |
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| 69 | #define UZ_S2 20 |
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| 70 | #define UZ_S3 21 |
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| 71 | #define UZ_S4 22 |
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| 72 | #define UZ_S5 23 |
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| 73 | #define UZ_S6 24 |
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| 74 | #define UZ_S7 25 |
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| 75 | #define UZ_S8 26 |
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| 76 | #define UZ_GP 27 |
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| 77 | #define UZ_RA 28 |
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| 78 | #define UZ_EPC 29 // CP0 Exception Program Counter |
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| 79 | #define UZ_CR 30 // CP0 Cause register |
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| 80 | #define UZ_SP 31 // user stack pointer |
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| 81 | #define UZ_SR 32 // CP0 Status Register |
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| 82 | #define UZ_LO 33 |
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| 83 | #define UZ_HI 34 |
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| 84 | #define UZ_DEXT 35 // CP2 data paddr extension |
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| 85 | #define UZ_MODE 36 // CP2 MMU mode |
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| 86 | |
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| 87 | #define CPU_REGS_NR 37 |
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| 88 | |
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| 89 | |
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| 90 | #endif /* _MIPS32_UZONE_REGS_H_ */ |
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