source: trunk/hal/tsar_mips32/drivers/soclib_cma.h @ 224

Last change on this file since 224 was 75, checked in by max@…, 7 years ago

Create the drivers/ sub-directory in each hal, and move soclib
into it. Note that soclib is not valid for x86_64, but more
changes will come.
File size: 12.6 KB
Line 
1/*
2 * soclib_nic.h - SOCLIB_NIC (Network Interface Controler) driver definition.
3 *
4 * Author    Alain Greiner (2016)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef _SOCLIB_NIC_H_
25#define _SOCLIB_NIC_H_
26
27#include <device.h>
28#include <hal_types.h>
29
30/********************************************************************************************
31 * This driver supports both the Soclib VciMultiNic component, that is a GMII compliant
32 * Gigabit Ethernet controler, and the associated VciChbufDma component, that is a chained
33 * buffers DMA controler, in charge of moving packets between the NIC hardware buffers,
34 * and the kernel memory buffers.
35 *
36 * - The VciMultiNic component supports N channels, indexed by the source IP address
37 *   for the RX packets, and by the destination IP address for the TX packets.
38 * - The VciChbufDma component contains 2*N channels, to support the N TX queues,
39 *   and the N RX  queues.
40 *
41 * The Ethernet packet length can have any value, between 64 to 1538 bytes.
42 * The data transfer unit between software and the NIC is a 4 Kbytes "container",
43 * containing an integer number of variable size packets.
44 *
45 * Each DMA TX or TX channel transfers an (infinite) stream of "containers" between
46 * the hardware "chbuf" contained in the VciMultiNic hardware components, and the software
47 * "chbuf" located in a given cluster kernel memory, and implementing the TX or RX queue.
48 * Each NIC channel contains one two-containers RX chbuf, and one two-containers TX chbuf.
49 *
50 * The max number of packets in a container is 66 packets.
51 * The first 34 words of a container are the container header :
52 *
53 *     word0    |       NB_WORDS        |       NB_PACKETS      |
54 *     word1    |       PLEN[0]         |       PLEN[1]         |
55 *      ...         |   .......         |       ........        |
56 *     word33   |       PLEN[64]        |       PLEN[65]        |
57 *
58 *  - NB_PACKETS is the actual number of packets in the container.
59 *      - NB_WORDS   is the number of useful words in the container.
60 *      - PLEN[i]    is the number of bytes for the packet[i].
61 *
62 * Packets are stored in the (1024 - 34) following words, and the packets are word-aligned.
63 *
64 *      - The first 4 Kbytes contain the RX_0 container data
65 *      - The next  4 Kbytes contain the RX_1 container data
66 *      - The next  4 Kbytes contain the TX_0 container data
67 *      - The next  4 Kbytes contain the TX_1 container data
68 *      - The next  4 Kbytes contain the channel addressable registers:
69 *      * NIC_RX_STS_0      : RX_0 status               (read/write)
70 *      * NIC_RX_STS_1      : RX_1 status               (read/write)
71 *      * NIC_TX_STS_0      : TX_0 status               (read/write)
72 *      * NIC_TX_STS_1      : TX_1 status               (read/write)
73 *      * NIC_RX_DESC_LO_0  : RX_0 descriptor low word  (read/write)
74 *      * NIC_RX_DESC_HI_0  : RX_0 descriptor high word (read/write)
75 *      * NIC_RX_DESC_LO_1  : RX_1 descriptor low word  (read/write)
76 *      * NIC_RX_DESC_HI_1  : RX_1 descriptor high word (read/write)
77 *      * NIC_TX_DESC_LO_0  : TX_0 descriptor low word  (read/write)
78 *      * NIC_TX_DESC_HI_0  : TX_0 descriptor high word (read/write)
79 *      * NIC_TX_DESC_LO_1  : TX_1 descriptor low word  (read/write)
80 *      * NIC_TX_DESC_HI_1  : TX_1 descriptor high word (read/write)
81 *              * NIC_MAC_4         : MAC @ 32 LSB bits         (read_only)
82 *              * NIC_MAC_2         : MAC @ 16 MSB bits         (read_only)
83 *      * NIC_RX_RUN        : RX channel X activated    (write_only)
84 *      * NIC_TX_RUN        : TX channel X activated    (write_only)
85 *
86 * To access both the container status, and the data contained in the container, the DMA
87 * uses two physical addresses, that are packed in a 64 bits "container descriptor".
88 * - desc[25:0]  contain bits[31:6] of the status physical address.
89 * - desc[51:26] contain bits[31:6] of the buffer physical address.
90 * - desc[63:52] contain the common 12 physical address extension bits.
91 * Both the buffer address and its status address must be 64 bytes aligned.
92 *******************************************************************************************/
93
94/********************************************************************************************
95 *       SOCLIB_NIC registers offset
96 *******************************************************************************************/
97
98enum SoclibMultiNicHyperRegisters {
99    NIC_G_VIS                        = 0,    * bitfield : bit N = 0 -> channel N disabled
100    NIC_G_ON                         = 1,    * boolean : NIC component activated
101    NIC_G_NB_CHAN                    = 2,    * Number of channels (read only)
102    NIC_G_BC_ENABLE                  = 3,    * boolean : Enable Broadcast if non zero
103    NIC_G_TDM_ENABLE                 = 4,    * boolean : TDM Scheduler if non zero
104    NIC_G_TDM_PERIOD                 = 5,    * TDM time slot value
105    NIC_G_BYPASS_ENABLE              = 6,    * boolean : Enable bypass for TX packets
106    NIC_G_MAC_4                      = 8,    * channel mac address 32 LSB bits array[8]
107    NIC_G_MAC_2                      = 16,   * channel mac address 16 MSB bits array[8]
108    NIC_G_NPKT_RX_G2S_RECEIVED       = 32,   * number of packets received on GMII RX port
109    NIC_G_NPKT_RX_G2S_DISCARDED      = 33,   * number of RX packets discarded by RX_G2S FSM
110
111    NIC_G_NPKT_RX_DES_SUCCESS        = 34,   * number of RX packets transmited by RX_DES FSM
112    NIC_G_NPKT_RX_DES_TOO_SMALL      = 35,   * number of discarded too small RX packets (<60B)
113    NIC_G_NPKT_RX_DES_TOO_BIG        = 36,   * number of discarded too big RX packets (>1514B)
114    NIC_G_NPKT_RX_DES_MFIFO_FULL     = 37,   * number of discarded RX packets fifo full
115    NIC_G_NPKT_RX_DES_CRC_FAIL       = 38,   * number of discarded RX packets CRC32 failure
116
117    NIC_G_NPKT_RX_DISPATCH_RECEIVED  = 39,   * number of packets received by RX_DISPATCH FSM
118    NIC_G_NPKT_RX_DISPATCH_BROADCAST = 40,   * number of broadcast RX packets received
119    NIC_G_NPKT_RX_DISPATCH_DST_FAIL  = 41,   * number of discarded RX packets DST MAC not found
120    NIC_G_NPKT_RX_DISPATCH_CH_FULL   = 42,   * number of discarded RX packets for channel full
121
122    NIC_G_NPKT_TX_DISPATCH_RECEIVED  = 43,   * number of packets received by TX_DISPATCH FSM
123    NIC_G_NPKT_TX_DISPATCH_TOO_SMALL = 44,   * number of discarded too small TX packets (<60B)
124    NIC_G_NPKT_TX_DISPATCH_TOO_BIG   = 45,   * number of discarded too big TX packets (>1514B)
125    NIC_G_NPKT_TX_DISPATCH_SRC_FAIL  = 46,   * number of discarded TX packets SRC MAC failed
126    NIC_G_NPKT_TX_DISPATCH_BROADCAST = 47,   * number of broadcast TX packets received
127    NIC_G_NPKT_TX_DISPATCH_BYPASS    = 48,   * number of bypassed TX->RX packets
128    NIC_G_NPKT_TX_DISPATCH_TRANSMIT  = 49,   * number of transmit TX packets
129
130    NIC_CHANNEL_SPAN                 = 0x2000,
131};
132
133enum SoclibMultiNicChannelRegisters
134{
135    NIC_RX_STS_0              = 0,    * RX_0 status (full or empty)      (Read/Write)
136    NIC_RX_STS_1              = 16,   * RX_1 status (full or empty)      (Read/Write)
137    NIC_TX_STS_0              = 32,   * TX_0 status (full or empty)      (Read/Write)
138    NIC_TX_STS_1              = 48,   * TX_1 status (full or empty)      (Read/Write)
139    NIC_RX_DESC_LO_0          = 64,   * RX_0 descriptor low word         (Read/Write)
140    NIC_RX_DESC_HI_0          = 65,   * RX_0 descriptor high word        (Read/Write)
141    NIC_RX_DESC_LO_1          = 66,   * RX_1 descriptor low word         (Read/Write)
142    NIC_RX_DESC_HI_1          = 67,   * RX_1 descriptor high word        (Read/Write) 
143    NIC_TX_DESC_LO_0          = 68,   * TX_0 descriptor low word         (Read/Write)
144    NIC_TX_DESC_HI_0          = 69,   * TX_0 descriptor high word        (Read/Write) 
145    NIC_TX_DESC_LO_1          = 70,   * TX_1 descriptor low word         (Read/Write)
146    NIC_TX_DESC_HI_1          = 71,   * TX_1 descriptor high word        (Read/Write) 
147    NIC_MAC_4                 = 72,   * channel mac address 32 LSB bits  (Read Only)
148    NIC_MAC_2                 = 73,   * channel mac address 16 LSB bits  (Read Only)
149    NIC_RX_RUN                = 74,   * RX packets can be received       (write_only)
150    NIC_TX_RUN                = 75,   * TX packets can be transmitted    (write_only)
151};
152
153
154
155/********************************************************************************************
156 * This structure defines the chained buffer descriptor, used to implement both
157 * the RX and TX packets queues. Each buffer in a chbuf (called container) is a 4 Kbytes
158 * buffer containing a variable number of packets. All containers are allocated in
159 * the same cluster as the associated NIC device descriptor. The chbuf descriptor contains:
160 * - an array of container pointers cont[], used by the kernet threads to access the
161 *   packets contained in the containers.
162 * - an array of set/reset Boolean full[] used by both the software threads and
163 *   by the hardware FSMs for lock-less synchronisation.
164 * - an array of containers descriptors containing the physical addresses of the
165 *   "full[i]" and "cont[i]" variables, used by the DMA FSMs. and an array of set/reset
166 * Moreover, It contains three pointers (cont_id, pkt_id, and word_id) that are private
167 * variables used by the software thread to store the chbuf global state.
168 *******************************************************************************************/
169
170typedef struct nic_chbuf_s
171{
172    uint32_t * cont[CONFIG_NIC_CHBUF_DEPTH]; /*! container virtual base address            */
173    uint32_t   full[CONFIG_NIC_CHBUF_DEPTH]; /*! Boolean : container full if non zero      */
174    uint64_t   desc[CONFIG_NIC_CHBUF_DEPTH]  /*! container & status physical addresses     */
175    uint32_t   cont_id;                      /*! current container index                   */
176    uint32_t   pkt_id;                       /*! current packet index in container         */
177    uint32_t   word_id;                      /*! first word of current packet              */
178}
179nic_chbuf_t;
180
181/********************************************************************************************
182 *        SOCLIB_NIC driver access functions
183 *******************************************************************************************/
184
185/********************************************************************************************
186 * This function initializes the SOCLIB_NIC hardware registers, allocates memory for
187 * the RX and TX containers, alocates and initializes the RX and TX chbuf descriptors.
188 * It allocates one WTI mailbox for the IRQ signaling availability of an RX full container,
189 * or a TX empty container, and route the WTI IRQ to the core running the server thread.
190 ********************************************************************************************
191 * @ dev     : extended pointer on the generic NIC device descriptor.
192 *******************************************************************************************/
193extern void soclib_nic_init( xptr_t dev );
194
195/********************************************************************************************
196 * This function implement the READ / WRITE / READABLE / WRITABLE commands.
197 * - READABLE : returns in the command status a boolean true if a packet is available.
198 *   It update the RX queue read pointer if required.
199 * - READ : move a packet from the RX queue to the command buffer, and returns the packet
200 *   length in the command. The READABLE command must be called before the READ command.
201 * - WRITABLE : returns in the command status a boolean true if a packet with a given length
202 *   can be written in the TX queue. It update the RX queue read pointer if required.
203 * - WRITE : move a packet from the command buffer to the TX queue. The WRITABLE command
204 *   must be called before the WRITE command.
205 *******************************************************************************************/
206extern void soclib_nic_cmd();
207
208/********************************************************************************************
209 * TODO
210 ********************************************************************************************
211 * @ dev     : local pointer on the generic IOC device descriptor.
212 *******************************************************************************************/
213extern void soclib_nic_isr( device_t * dev );
214
215
216#endif /* _BLOCK_H_ */
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