source: trunk/hal/tsar_mips32/drivers/soclib_mmc.h

Last change on this file was 657, checked in by alain, 7 years ago

Introduce remote_buf.c/.h & socket.c/.h files.
Update dev_nic.c/.h files.
File size: 6.6 KB
Line 
1/*
2 * soclib_mmc.h - TSAR L2 cache driver definition.
3 *
4 * Author Alain Greiner (2016,2017,2018,2019),2020)
5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef _SOCLIB_MMC_H_
25#define _SOCLIB_MMC_H_
26
27#include <chdev.h>
28#include <dev_mmc.h>
29#include <hal_kernel_types.h>
30
31/********************************************************************************************
32 * This driver supports the SocLib VciMemCache component, that is the L2 cache used
33 * by the TSAR architure.
34 *******************************************************************************************/
35
36/********************************************************************************************
37 * SOCLIB_MMC registers offset
38 * - the register index is coded on 7 address bits : A[8:2]
39 * - the functionnality is coded on 2 address bits : A[10:9]
40 *******************************************************************************************/
41
42enum SoclibMemCacheFunc
43{
44 SOCLIB_MMC_CC_FUNC = 0,
45 SOCLIB_MMC_INSTR_FUNC = 1,
46 SOCLIB_MMC_ERROR_FUNC = 2,
47
48 SOCLIB_MMC_FUNC_SPAN = 0x200
49};
50
51enum SoclibMemCacheConfigCmd
52{
53 SOCLIB_MMC_CC_NOP = 0,
54 SOCLIB_MMC_CC_INVAL = 1,
55 SOCLIB_MMC_CC_SYNC = 2,
56};
57
58// CONFIG Registers indexes
59enum SoclibMemCacheCCRegs
60{
61 SOCLIB_MMC_ADDR_LO = 0,
62 SOCLIB_MMC_ADDR_HI = 1,
63 SOCLIB_MMC_BUF_LENGTH = 2,
64 SOCLIB_MMC_CMD_TYPE = 3,
65};
66
67// INSTRU Registers indexes
68enum SoclibMemCacheInstrRegs
69{
70
71 // NUMBER OF LOCAL TRANSACTIONS ON DIRECT NETWORK
72
73 SOCLIB_MMC_LOCAL_READ_LO = 0x00,
74 SOCLIB_MMC_LOCAL_READ_HI = 0x01,
75 SOCLIB_MMC_LOCAL_WRITE_LO = 0x02,
76 SOCLIB_MMC_LOCAL_WRITE_HI = 0x03,
77 SOCLIB_MMC_LOCAL_LL_LO = 0x04,
78 SOCLIB_MMC_LOCAL_LL_HI = 0x05,
79 SOCLIB_MMC_LOCAL_SC_LO = 0x06,
80 SOCLIB_MMC_LOCAL_SC_HI = 0x07,
81 SOCLIB_MMC_LOCAL_CAS_LO = 0x08,
82 SOCLIB_MMC_LOCAL_CAS_HI = 0x09,
83
84 // NUMBER OF REMOTE TRANSACTIONS ON DIRECT NETWORK
85
86 SOCLIB_MMC_REMOTE_READ_LO = 0x10,
87 SOCLIB_MMC_REMOTE_READ_HI = 0x11,
88 SOCLIB_MMC_REMOTE_WRITE_LO = 0x12,
89 SOCLIB_MMC_REMOTE_WRITE_HI = 0x13,
90 SOCLIB_MMC_REMOTE_LL_LO = 0x14,
91 SOCLIB_MMC_REMOTE_LL_HI = 0x15,
92 SOCLIB_MMC_REMOTE_SC_LO = 0x16,
93 SOCLIB_MMC_REMOTE_SC_HI = 0x17,
94 SOCLIB_MMC_REMOTE_CAS_LO = 0x18,
95 SOCLIB_MMC_REMOTE_CAS_HI = 0x19,
96
97 // COST OF TRANSACTIONS ON DIRECT NETWORK
98
99 SOCLIB_MMC_COST_READ_LO = 0x20,
100 SOCLIB_MMC_COST_READ_HI = 0x21,
101 SOCLIB_MMC_COST_WRITE_LO = 0x22,
102 SOCLIB_MMC_COST_WRITE_HI = 0x23,
103 SOCLIB_MMC_COST_LL_LO = 0x24,
104 SOCLIB_MMC_COST_LL_HI = 0x25,
105 SOCLIB_MMC_COST_SC_LO = 0x26,
106 SOCLIB_MMC_COST_SC_HI = 0x27,
107 SOCLIB_MMC_COST_CAS_LO = 0x28,
108 SOCLIB_MMC_COST_CAS_HI = 0x29,
109
110 // NUMBER OF LOCAL TRANSACTIONS ON CC NETWORK
111
112 SOCLIB_MMC_LOCAL_MUPDATE_LO = 0x40,
113 SOCLIB_MMC_LOCAL_MUPDATE_HI = 0x41,
114 SOCLIB_MMC_LOCAL_MINVAL_LO = 0x42,
115 SOCLIB_MMC_LOCAL_MINVAL_HI = 0x43,
116 SOCLIB_MMC_LOCAL_CLEANUP_LO = 0x44,
117 SOCLIB_MMC_LOCAL_CLEANUP_HI = 0x45,
118
119 // NUMBER OF REMOTE TRANSACTIONS ON CC NETWORK
120
121 SOCLIB_MMC_REMOTE_MUPDATE_LO = 0x50,
122 SOCLIB_MMC_REMOTE_MUPDATE_HI = 0x51,
123 SOCLIB_MMC_REMOTE_MINVAL_LO = 0x52,
124 SOCLIB_MMC_REMOTE_MINVAL_HI = 0x53,
125 SOCLIB_MMC_REMOTE_CLEANUP_LO = 0x54,
126 SOCLIB_MMC_REMOTE_CLEANUP_HI = 0x55,
127
128 // COST OF TRANSACTIONS ON CC NETWORK
129
130 SOCLIB_MMC_COST_MUPDATE_LO = 0x60,
131 SOCLIB_MMC_COST_MUPDATE_HI = 0x61,
132 SOCLIB_MMC_COST_MINVAL_LO = 0x62,
133 SOCLIB_MMC_COST_MINVAL_HI = 0x63,
134 SOCLIB_MMC_COST_CLEANUP_LO = 0x64,
135 SOCLIB_MMC_COST_CLEANUP_HI = 0x65,
136
137 // TOTAL
138
139 SOCLIB_MMC_TOTAL_MUPDATE_LO = 0x68,
140 SOCLIB_MMC_TOTAL_MUPDATE_HI = 0x69,
141 SOCLIB_MMC_TOTAL_MINVAL_LO = 0x6A,
142 SOCLIB_MMC_TOTAL_MINVAL_HI = 0x6B,
143 SOCLIB_MMC_TOTAL_BINVAL_LO = 0x6C,
144 SOCLIB_MMC_TOTAL_BINVAL_HI = 0x6D,
145};
146
147// ERROR registers indexes
148enum SoclibMemCacheRerrorRegs
149{
150 SOCLIB_MMC_ERROR_ADDR_LO = 0,
151 SOCLIB_MMC_ERROR_ADDR_HI = 1,
152 SOCLIB_MMC_ERROR_SRCID = 2,
153 SOCLIB_MMC_ERROR_IRQ_RESET = 3,
154 SOCLIB_MMC_ERROR_IRQ_ENABLE = 4,
155};
156
157
158#define MMC_REG(func,index) ((func<<7)|index)
159
160
161/********************************************************************************************
162 * This function initializes the SOCLIB_MMC peripheral hardware registers.
163 * It enables the MMC peripheral IRQ.
164 ********************************************************************************************
165 * @ chdev : local pointer on the MMC chdev descriptor.
166 *******************************************************************************************/
167extern void soclib_mmc_init( chdev_t * chdev );
168
169/********************************************************************************************
170 * This blocking function can be called by any thread running in any cluster.
171 * It executes the command registered in the calling thread descriptor.
172 * The MMC device spinlock must have been taken by the calling thead.
173 ********************************************************************************************
174 * @ thread_xp : extended pointer on the client thread.
175 *******************************************************************************************/
176extern void soclib_mmc_cmd( xptr_t thread_xp );
177
178/********************************************************************************************
179 * This Interrupt Service Routine is executed when the MMC IRQ signals a faulty address.
180 * The ISR should access the relevant MMC register to get the faulty physical address
181 * and the associated SRCID, and acknowledges the IRQ.
182 ********************************************************************************************
183 * @ chdev : local pointer on the MMC chdev descriptor.
184 *******************************************************************************************/
185extern void soclib_mmc_isr( chdev_t * chdev );
186
187
188#endif // SOCLIB_MMC_H_
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