[75] | 1 | /* |
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| 2 | * soclib_pic.c - soclib PIC driver implementation. |
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| 3 | * |
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[188] | 4 | * Author Alain Greiner (2016,2017) |
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[141] | 5 | * |
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[75] | 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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[141] | 10 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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[75] | 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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[141] | 14 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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[75] | 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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[141] | 20 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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[75] | 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[451] | 24 | #include <hal_kernel_types.h> |
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[75] | 25 | #include <chdev.h> |
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| 26 | #include <soclib_pic.h> |
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| 27 | #include <errno.h> |
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| 28 | #include <string.h> |
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| 29 | #include <vfs.h> |
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[296] | 30 | #include <rpc.h> |
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[188] | 31 | #include <cluster.h> |
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| 32 | #include <printk.h> |
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| 33 | #include <core.h> |
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| 34 | #include <thread.h> |
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[75] | 35 | |
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[188] | 36 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 37 | // Extern variables |
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| 38 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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| 40 | extern chdev_directory_t chdev_dir; // defined in chdev.h / allocated in kerneL-init.c |
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| 41 | |
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| 42 | extern iopic_input_t iopic_input; // defined in dev_pic.h / allocated in kernel_init.c |
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| 43 | extern lapic_input_t lapic_input; // defined in dev_pic.h / allocated in kernel_init.c |
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| 44 | |
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[407] | 45 | |
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| 46 | |
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[188] | 47 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 48 | // SOCLIB PIC private functions |
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| 49 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 50 | |
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| 51 | /////////////////////////////// |
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| 52 | uint32_t soclib_pic_wti_alloc() |
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| 53 | { |
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| 54 | uint32_t index; |
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| 55 | |
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| 56 | // get pointer on cluster extension for SOCLIB PIC (XCU descriptor) |
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| 57 | soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend; |
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| 58 | |
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| 59 | assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) , __FUNCTION__ , |
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| 60 | "no free WTI found : too much external IRQs\n"); |
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| 61 | |
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| 62 | // update WTI allocator |
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| 63 | index = ext_ptr->first_free_wti; |
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| 64 | ext_ptr->first_free_wti++; |
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| 65 | |
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| 66 | return index; |
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| 67 | |
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| 68 | } // end soclib_pic_wti_alloc() |
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| 69 | |
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| 70 | /////////////////////////////////////// |
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| 71 | inline uint32_t * soclib_pic_xcu_base() |
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| 72 | { |
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[205] | 73 | return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base; |
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| 74 | } |
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[188] | 75 | |
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[205] | 76 | ///////////////////////////////////////////////////////// |
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| 77 | inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy ) |
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| 78 | { |
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| 79 | soclib_pic_cluster_t * extend; |
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[188] | 80 | |
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[205] | 81 | // get extended pointer on PIC extension in remote cluster |
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| 82 | extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) ); |
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[188] | 83 | |
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[205] | 84 | return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) ); |
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| 85 | |
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| 86 | } |
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| 87 | |
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[188] | 88 | /////////////////////////////////////////// |
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| 89 | void soclib_pic_xcu_status( lid_t lid, |
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| 90 | uint32_t * hwi_status, |
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| 91 | uint32_t * wti_status, |
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| 92 | uint32_t * pti_status ) |
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| 93 | { |
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| 94 | // get local XCU segment base |
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| 95 | uint32_t * base = soclib_pic_xcu_base(); |
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| 96 | |
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| 97 | // read PRIO register |
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[432] | 98 | // in TSAR : XCU output [4*lid] is connected to core [lid] |
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| 99 | uint32_t prio = base[ (XCU_PRIO << 5) | (lid<<2) ]; |
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[188] | 100 | |
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| 101 | *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0; |
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| 102 | *hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0; |
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| 103 | *pti_status = (prio & 0x1) ? (((prio >> 8) & 0x1F) + 1) : 0; |
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| 104 | |
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| 105 | } |
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| 106 | |
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[279] | 107 | //////////////////////////////////////////////////// |
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| 108 | inline uint32_t soclib_pic_xcu_ack( uint32_t * reg ) |
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| 109 | { |
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| 110 | return *reg; |
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| 111 | } |
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| 112 | |
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[188] | 113 | ///////////////////////////// |
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| 114 | void soclib_pic_irq_handler() |
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| 115 | { |
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| 116 | uint32_t hwi_status; // HWI index + 1 / no pending HWI if 0 |
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| 117 | uint32_t wti_status; // WTI index + 1 / no pending WTI if 0 |
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| 118 | uint32_t pti_status; // PTI index + 1 / no pending PTI if 0 |
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| 119 | chdev_t * src_chdev; // pointer on source chdev descriptor |
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[279] | 120 | uint32_t index; // WTI / HWI / PTI index |
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[188] | 121 | |
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[406] | 122 | uint32_t * xcu_base = soclib_pic_xcu_base(); |
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[188] | 123 | |
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[406] | 124 | core_t * core = CURRENT_THREAD->core; |
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| 125 | |
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[188] | 126 | // get XCU status |
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| 127 | soclib_pic_xcu_status( core->lid, |
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| 128 | &hwi_status, |
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| 129 | &wti_status, |
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| 130 | &pti_status ); |
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| 131 | |
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[438] | 132 | #if DEBUG_HAL_IRQS |
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[435] | 133 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[438] | 134 | if (DEBUG_HAL_IRQS < cycle ) |
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[435] | 135 | printk("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x / cycle %d\n", |
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| 136 | __FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status, cycle ); |
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| 137 | #endif |
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[279] | 138 | |
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[188] | 139 | // analyse status and handle up to 3 pending IRQ (one WTI, one HWI, one PTI) |
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| 140 | |
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| 141 | if( wti_status ) // pending WTI |
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| 142 | { |
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| 143 | index = wti_status - 1; |
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| 144 | |
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[438] | 145 | //////////////////////////////////////////////////////// |
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[188] | 146 | if( index < LOCAL_CLUSTER->cores_nr ) // it is an IPI |
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| 147 | { |
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| 148 | assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" ); |
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| 149 | |
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[438] | 150 | #if DEBUG_HAL_IRQS |
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| 151 | if (DEBUG_HAL_IRQS < cycle ) |
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[435] | 152 | printk("\n[DBG] %s : core[%x,%d] received an IPI\n", __FUNCTION__ , local_cxy , core->lid ); |
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| 153 | #endif |
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[438] | 154 | // acknowledge IRQ (this require an XCU read) |
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[406] | 155 | uint32_t ack = xcu_base[(XCU_WTI_REG << 5) | core->lid]; |
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[438] | 156 | |
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[296] | 157 | // check RPC FIFO, and activate or create a RPC thread |
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[337] | 158 | // condition is always true, but we must use the ack value |
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| 159 | if( ack + 1 ) rpc_check(); |
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[188] | 160 | } |
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[438] | 161 | //////////////////////////////////////////////////////////////// |
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| 162 | else // it is an external IRQ |
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[188] | 163 | { |
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| 164 | // get pointer on source chdev |
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| 165 | src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index]; |
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| 166 | |
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| 167 | if( src_chdev == NULL ) // strange, but not fatal |
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| 168 | { |
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| 169 | printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n", |
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| 170 | __FUNCTION__ , index , core->lid , local_cxy ); |
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| 171 | |
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| 172 | core->spurious_irqs ++; |
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| 173 | |
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[279] | 174 | // disable WTI in local XCU controller |
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[438] | 175 | xcu_base[(XCU_MSK_WTI_DISABLE << 5) | core->lid] = 1 << core->lid; |
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| 176 | |
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| 177 | hal_fence(); |
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[188] | 178 | } |
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| 179 | else // call relevant ISR |
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| 180 | { |
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| 181 | |
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[438] | 182 | #if DEBUG_HAL_IRQS |
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| 183 | if (DEBUG_HAL_IRQS < cycle ) |
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[435] | 184 | printk("\n[DBG] %s : core[%x,%d] received external WTI %d\n", |
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| 185 | __FUNCTION__ , local_cxy , core->lid , index ); |
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| 186 | #endif |
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[188] | 187 | // call ISR |
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| 188 | src_chdev->isr( src_chdev ); |
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| 189 | } |
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| 190 | } |
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| 191 | } |
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| 192 | |
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[438] | 193 | ///////////////////////////////////////////////////////////// |
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| 194 | if( hwi_status ) // It is an Internal IRQ |
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[188] | 195 | { |
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| 196 | index = hwi_status - 1; |
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| 197 | |
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| 198 | // get pointer on source chdev |
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| 199 | src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index]; |
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| 200 | |
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| 201 | if( src_chdev == NULL ) // strange, but not fatal |
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| 202 | { |
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| 203 | printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n", |
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| 204 | __FUNCTION__ , index , core->lid , local_cxy ); |
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| 205 | |
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| 206 | core->spurious_irqs ++; |
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| 207 | |
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[279] | 208 | // disable HWI in local XCU controller |
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[406] | 209 | xcu_base[(XCU_MSK_HWI_DISABLE << 5) | core->lid] = 1 << core->lid; |
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[438] | 210 | |
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| 211 | hal_fence(); |
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[188] | 212 | } |
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| 213 | else // call relevant ISR |
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| 214 | { |
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| 215 | |
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[438] | 216 | #if DEBUG_HAL_IRQS |
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| 217 | if (DEBUG_HAL_IRQS < cycle ) |
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[435] | 218 | printk("\n[DBG] %s : core[%x,%d] received HWI %d\n", |
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| 219 | __FUNCTION__ , local_cxy , core->lid , index ); |
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| 220 | #endif |
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[188] | 221 | // call ISR |
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| 222 | src_chdev->isr( src_chdev ); |
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| 223 | } |
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| 224 | } |
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[438] | 225 | /////////////////////////////////////////////////////// |
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| 226 | if( pti_status ) // It is a Timer IRQ |
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[188] | 227 | { |
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| 228 | index = pti_status - 1; |
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| 229 | |
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| 230 | assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n"); |
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| 231 | |
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[438] | 232 | #if DEBUG_HAL_IRQS |
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| 233 | if (DEBUG_HAL_IRQS < cycle ) |
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[435] | 234 | printk("\n[DBG] %s : core[%x,%d] received PTI %d\n", |
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| 235 | __FUNCTION__ , core->lid , local_cxy , index ); |
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| 236 | #endif |
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[438] | 237 | // acknowledge IRQ (this require a read access to XCU) |
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[406] | 238 | uint32_t ack = xcu_base[(XCU_PTI_ACK << 5) | core->lid]; |
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[188] | 239 | |
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[279] | 240 | // execute all actions related to TICK event |
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[406] | 241 | // condition is always true, but we must use the ack value |
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| 242 | if( ack + 1 ) core_clock( core ); |
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[188] | 243 | } |
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| 244 | } // end soclib_pic_irq_handler() |
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| 245 | |
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| 246 | |
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| 247 | |
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| 248 | |
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| 249 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 250 | // SOCLIC PIC device generic API |
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| 251 | ////////////////////////////////////////////////////////////////////////////////////// |
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| 252 | |
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| 253 | ///////////////////////////////////// |
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| 254 | void soclib_pic_init( chdev_t * pic ) |
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| 255 | { |
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| 256 | uint32_t i; // for loop on IOPIC inputs |
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| 257 | |
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| 258 | // get IOPIC controller cluster and segment base pointer |
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[451] | 259 | cxy_t iopic_seg_cxy = GET_CXY( pic->base ); |
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| 260 | uint32_t * iopic_seg_ptr = GET_PTR( pic->base ); |
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[188] | 261 | |
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[407] | 262 | // reset the IOPIC component registers : disable all input IRQs |
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[188] | 263 | for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ ) |
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| 264 | { |
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| 265 | xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy, |
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| 266 | iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK ); |
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| 267 | hal_remote_sw( iopic_seg_xp , 0 ); |
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| 268 | } |
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| 269 | |
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| 270 | } // end soclib_pic_init() |
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| 271 | |
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| 272 | ////////////////////////////////////////////////// |
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| 273 | void soclib_pic_extend_init( uint32_t * xcu_base ) |
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| 274 | { |
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| 275 | soclib_pic_cluster_t * cluster_ext_ptr; |
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| 276 | soclib_pic_core_t * core_ext_ptr; |
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| 277 | kmem_req_t req; |
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| 278 | uint32_t lid; |
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| 279 | uint32_t idx; |
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| 280 | |
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| 281 | cluster_t * cluster = LOCAL_CLUSTER; |
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| 282 | |
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| 283 | // create core extension for all cores in cluster |
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| 284 | for( lid = 0 ; lid < cluster->cores_nr ; lid++ ) |
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| 285 | { |
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| 286 | // allocate memory for core extension |
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| 287 | req.type = KMEM_GENERIC; |
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| 288 | req.size = sizeof(soclib_pic_core_t); |
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| 289 | req.flags = AF_KERNEL; |
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| 290 | core_ext_ptr = kmem_alloc( &req ); |
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| 291 | |
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| 292 | assert( (core_ext_ptr != NULL) , __FUNCTION__ , |
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| 293 | "cannot allocate memory for core extension\n"); |
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| 294 | |
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| 295 | // reset the HWI / WTI interrupt vectors |
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| 296 | for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL; |
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| 297 | for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL; |
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| 298 | |
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| 299 | // register PIC extension in core descriptor |
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| 300 | cluster->core_tbl[lid].pic_extend = core_ext_ptr; |
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| 301 | } |
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| 302 | |
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| 303 | // allocate memory for cluster extension |
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| 304 | req.type = KMEM_GENERIC; |
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| 305 | req.size = sizeof(soclib_pic_cluster_t); |
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| 306 | req.flags = AF_KERNEL; |
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| 307 | cluster_ext_ptr = kmem_alloc( &req ); |
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| 308 | |
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| 309 | assert( (cluster_ext_ptr != NULL) , __FUNCTION__ , |
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| 310 | "cannot allocate memory for cluster extension\n"); |
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| 311 | |
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| 312 | // get XCU characteristics from the XCU config register |
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| 313 | uint32_t config = xcu_base[XCU_CONFIG<<5]; |
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| 314 | uint32_t wti_nr = (config >> 16) & 0xFF; |
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| 315 | uint32_t hwi_nr = (config >> 8 ) & 0xFF; |
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| 316 | uint32_t pti_nr = (config ) & 0xFF; |
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| 317 | |
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| 318 | // initialize the cluster extension |
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| 319 | // The first WTI slots are for IPIs (one slot per core) |
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| 320 | cluster_ext_ptr->xcu_base = xcu_base; |
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| 321 | cluster_ext_ptr->hwi_nr = hwi_nr; |
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| 322 | cluster_ext_ptr->wti_nr = wti_nr; |
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| 323 | cluster_ext_ptr->pti_nr = pti_nr; |
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| 324 | cluster_ext_ptr->first_free_wti = cluster->cores_nr; |
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| 325 | |
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| 326 | // register PIC extension in cluster manager |
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| 327 | cluster->pic_extend = cluster_ext_ptr; |
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| 328 | |
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[451] | 329 | // reset the XCU component registers |
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| 330 | // mask all HWIs, all WTIs, and all PTIs, for all cores in local cluster |
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| 331 | for( lid = 0 ; lid < cluster->cores_nr ; lid++ ) |
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| 332 | { |
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| 333 | xcu_base[XCU_MSK_HWI_DISABLE << 5 | lid] = 0xFFFFFFFF; |
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| 334 | xcu_base[XCU_MSK_WTI_DISABLE << 5 | lid] = 0xFFFFFFFF; |
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| 335 | xcu_base[XCU_MSK_PTI_DISABLE << 5 | lid] = 0xFFFFFFFF; |
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| 336 | } |
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| 337 | |
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[188] | 338 | } // end soclib_pic_extend_init() |
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| 339 | |
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[75] | 340 | //////////////////////////////////////// |
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[188] | 341 | void soclib_pic_bind_irq( lid_t lid, |
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| 342 | chdev_t * src_chdev ) |
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[75] | 343 | { |
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[435] | 344 | |
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[438] | 345 | #if DEBUG_HAL_IRQS |
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[435] | 346 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[438] | 347 | if( DEBUG_HAL_IRQS < cycle ) |
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[435] | 348 | printk("\n[DBG] %s : thread %x enter for core[%x,%d] / cycle %d\n", |
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| 349 | __FUNCTION__ , CURRENT_THREAD , local_cxy , lid , cycle ); |
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| 350 | #endif |
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| 351 | |
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[188] | 352 | // get extended & local pointers on PIC chdev descriptor |
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| 353 | xptr_t pic_xp = chdev_dir.pic; |
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| 354 | cxy_t pic_cxy = GET_CXY( pic_xp ); |
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| 355 | chdev_t * pic_ptr = (chdev_t *)GET_PTR( pic_xp ); |
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[75] | 356 | |
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[188] | 357 | // get extended and local pointers on IOPIC segment base |
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| 358 | xptr_t seg_pic_xp = hal_remote_lwd( XPTR( pic_cxy , &pic_ptr->base ) ); |
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| 359 | cxy_t seg_pic_cxy = GET_CXY( seg_pic_xp ); |
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| 360 | uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp ); |
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| 361 | |
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| 362 | // get local pointer on XCU segment base |
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| 363 | uint32_t * seg_xcu_ptr = soclib_pic_xcu_base(); |
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| 364 | |
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| 365 | // get the source chdev functionnal type, channel, and direction |
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| 366 | uint32_t func = src_chdev->func; |
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| 367 | uint32_t channel = src_chdev->channel; |
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| 368 | bool_t is_rx = src_chdev->is_rx; |
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| 369 | |
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| 370 | if( (func == DEV_FUNC_IOC) || (func == DEV_FUNC_NIC) || |
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| 371 | (func == DEV_FUNC_TXT) || (func == DEV_FUNC_IOB) ) // external IRQ => WTI |
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[75] | 372 | { |
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[188] | 373 | // get external IRQ index |
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[407] | 374 | uint32_t hwi_id; |
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| 375 | if ( func == DEV_FUNC_IOC ) hwi_id = iopic_input.ioc[channel]; |
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| 376 | else if( func == DEV_FUNC_TXT && is_rx ) hwi_id = iopic_input.txt_rx[channel]; |
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| 377 | else if( func == DEV_FUNC_TXT && !is_rx ) hwi_id = iopic_input.txt_tx[channel]; |
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| 378 | else if( (func == DEV_FUNC_NIC) && is_rx ) hwi_id = iopic_input.nic_rx[channel]; |
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| 379 | else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel]; |
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| 380 | else if( func == DEV_FUNC_IOB ) hwi_id = iopic_input.iob; |
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[188] | 381 | else assert( false , __FUNCTION__ , "illegal device functionnal type\n"); |
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| 382 | |
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| 383 | // get a WTI mailbox from local XCU descriptor |
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| 384 | uint32_t wti_id = soclib_pic_wti_alloc(); |
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| 385 | |
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| 386 | // register IRQ type and index in chdev |
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| 387 | src_chdev->irq_type = SOCLIB_TYPE_WTI; |
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| 388 | src_chdev->irq_id = wti_id; |
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| 389 | |
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| 390 | // compute extended pointer on WTI mailbox in local XCU |
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| 391 | xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) | wti_id] ); |
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| 392 | |
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| 393 | // set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC |
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| 394 | uint32_t lsb_wdata = (uint32_t)wti_xp; |
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| 395 | uint32_t msb_wdata = (uint32_t)(wti_xp >> 32); |
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[407] | 396 | xptr_t lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS ); |
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| 397 | xptr_t msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND ); |
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[188] | 398 | hal_remote_sw( lsb_xp , lsb_wdata ); |
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| 399 | hal_remote_sw( msb_xp , msb_wdata ); |
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| 400 | |
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[407] | 401 | // enable IRQ in IOPIC |
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| 402 | hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 ); |
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[188] | 403 | |
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| 404 | // update the WTI interrupt vector for core[lid] |
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| 405 | core_t * core = &LOCAL_CLUSTER->core_tbl[lid]; |
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| 406 | ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev; |
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[407] | 407 | |
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[438] | 408 | #if DEBUG_HAL_IRQS |
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| 409 | if( DEBUG_HAL_IRQS < cycle ) |
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[435] | 410 | printk("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n", |
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[407] | 411 | __FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy ); |
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[435] | 412 | #endif |
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[407] | 413 | |
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[75] | 414 | } |
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[188] | 415 | else if( (func == DEV_FUNC_DMA) || (func == DEV_FUNC_MMC) ) // internal IRQ => HWI |
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| 416 | { |
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| 417 | // get internal IRQ index |
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| 418 | uint32_t hwi_id; |
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| 419 | if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel]; |
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| 420 | else hwi_id = lapic_input.mmc; |
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[75] | 421 | |
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[188] | 422 | // register IRQ type and index in chdev |
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| 423 | src_chdev->irq_type = SOCLIB_TYPE_HWI; |
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| 424 | src_chdev->irq_id = hwi_id; |
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| 425 | |
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| 426 | // update the HWI interrupt vector for core[lid] |
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| 427 | core_t * core = &LOCAL_CLUSTER->core_tbl[lid]; |
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| 428 | ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev; |
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[407] | 429 | |
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[438] | 430 | #if DEBUG_HAL_IRQS |
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| 431 | if( DEBUG_HAL_IRQS < cycle ) |
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[435] | 432 | printk("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n", |
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[407] | 433 | __FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy ); |
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[435] | 434 | #endif |
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[407] | 435 | |
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[188] | 436 | } |
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| 437 | else |
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| 438 | { |
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| 439 | assert( false , __FUNCTION__ , "illegal device functionnal type\n" ); |
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| 440 | } |
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| 441 | } // end soclib_pic_bind_irq(); |
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| 442 | |
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[205] | 443 | /////////////////////////////////////// |
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| 444 | void soclib_pic_enable_irq( lid_t lid, |
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| 445 | xptr_t src_chdev_xp ) |
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[75] | 446 | { |
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[205] | 447 | // get cluster and local pointer on remote src_chdev |
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| 448 | cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp ); |
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| 449 | chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp ); |
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[141] | 450 | |
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[205] | 451 | // get local pointer on remote XCU segment base |
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| 452 | uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy ); |
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| 453 | |
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[188] | 454 | // get the source chdev IRQ type and index |
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[205] | 455 | uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) ); |
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| 456 | uint32_t irq_id = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) ); |
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[141] | 457 | |
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[188] | 458 | if( irq_type == SOCLIB_TYPE_HWI ) |
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| 459 | { |
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[205] | 460 | // enable this HWI in remote XCU controller |
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[432] | 461 | // in TSAR : XCU output [4*lid] is connected to core [lid] |
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[205] | 462 | hal_remote_sw( XPTR( src_chdev_cxy , |
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[440] | 463 | &seg_xcu_ptr[ (XCU_MSK_HWI_ENABLE << 5) | (lid<<2) ] ) , (1 << irq_id) ); |
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[188] | 464 | } |
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| 465 | else if( irq_type == SOCLIB_TYPE_WTI ) |
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| 466 | { |
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[279] | 467 | // enable this WTI in remote XCU controller |
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[432] | 468 | // in TSAR : XCU output [4*lid] is connected to core [lid] |
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[205] | 469 | hal_remote_sw( XPTR( src_chdev_cxy , |
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[440] | 470 | &seg_xcu_ptr[ (XCU_MSK_WTI_ENABLE << 5) | (lid<<2) ] ) , (1 << irq_id) ); |
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[188] | 471 | } |
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| 472 | else |
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| 473 | { |
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| 474 | assert( false , __FUNCTION__ , "illegal IRQ type\n" ); |
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| 475 | } |
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| 476 | } // end soclib_pic_enable_irq() |
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[75] | 477 | |
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[205] | 478 | //////////////////////////////////////// |
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| 479 | void soclib_pic_disable_irq( lid_t lid, |
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| 480 | xptr_t src_chdev_xp ) |
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[188] | 481 | { |
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[205] | 482 | // get cluster and local pointer on remote src_chdev |
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| 483 | cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp ); |
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| 484 | chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp ); |
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[75] | 485 | |
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[205] | 486 | // get local pointer on remote XCU segment base |
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| 487 | uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy ); |
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| 488 | |
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[188] | 489 | // get the source chdev IRQ type and index |
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[205] | 490 | uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) ); |
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| 491 | uint32_t irq_id = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) ); |
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[75] | 492 | |
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[188] | 493 | if( irq_type == SOCLIB_TYPE_HWI ) |
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| 494 | { |
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[432] | 495 | // enable this HWI in remote XCU controller |
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| 496 | // in TSAR : XCU output [4*lid] is connected to core [lid] |
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[205] | 497 | hal_remote_sw( XPTR( src_chdev_cxy , |
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[432] | 498 | &seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | (lid<<2) ] ) , (1 << irq_id) ); |
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[188] | 499 | } |
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| 500 | else if( irq_type == SOCLIB_TYPE_WTI ) |
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| 501 | { |
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[279] | 502 | // enable this WTI in remote XCU controller |
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[432] | 503 | // in TSAR : XCU output [4*lid] is connected to core [lid] |
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[205] | 504 | hal_remote_sw( XPTR( src_chdev_cxy , |
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[440] | 505 | &seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | (lid<<2) ] ) , (1 << irq_id) ); |
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[188] | 506 | } |
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| 507 | else |
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| 508 | { |
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| 509 | assert( false , __FUNCTION__ , "illegal IRQ type\n" ); |
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| 510 | } |
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| 511 | } // end soclib_pic_enable_irq() |
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[75] | 512 | |
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[188] | 513 | /////////////////////////////////////////////// |
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| 514 | void soclib_pic_enable_timer( uint32_t period ) |
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[75] | 515 | { |
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[188] | 516 | // calling core local index |
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| 517 | lid_t lid = CURRENT_CORE->lid; |
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[141] | 518 | |
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[188] | 519 | // get XCU segment base |
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| 520 | uint32_t * base = soclib_pic_xcu_base(); |
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[141] | 521 | |
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[380] | 522 | // set period value in XCU (in cycles) |
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[407] | 523 | uint32_t cycles = period * SOCLIB_CYCLES_PER_MS; |
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[380] | 524 | base[(XCU_PTI_PER << 5) | lid] = cycles; |
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[75] | 525 | |
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[279] | 526 | // enable PTI in local XCU controller |
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[432] | 527 | // In TSAR : XCU output [4*lid] is connected to core [lid] |
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| 528 | base[ (XCU_MSK_PTI_ENABLE << 5) | (lid<<2) ] = 1 << lid; |
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[75] | 529 | } |
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| 530 | |
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[279] | 531 | //////////////////////////// |
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| 532 | void soclib_pic_enable_ipi() |
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| 533 | { |
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| 534 | // calling core local index |
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| 535 | lid_t lid = CURRENT_CORE->lid; |
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| 536 | |
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| 537 | // get XCU segment base |
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| 538 | uint32_t * base = soclib_pic_xcu_base(); |
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| 539 | |
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| 540 | // enable WTI in local XCU controller |
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[432] | 541 | // In TSAR : XCU output [4*lid] is connected to core [lid] |
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| 542 | base[ (XCU_MSK_WTI_ENABLE << 5) | (lid<<2) ] = 1 << lid; |
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[279] | 543 | } |
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| 544 | |
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[188] | 545 | /////////////////////////////////////// |
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| 546 | void soclib_pic_send_ipi( cxy_t cxy, |
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| 547 | lid_t lid ) |
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[75] | 548 | { |
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[188] | 549 | // get pointer on local XCU segment base |
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| 550 | uint32_t * base = soclib_pic_xcu_base(); |
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[141] | 551 | |
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[188] | 552 | // write to WTI mailbox[cxy][lid] |
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[432] | 553 | hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid ] ) , 0 ); |
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[188] | 554 | } |
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[141] | 555 | |
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[407] | 556 | ///////////////////////// |
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| 557 | void soclib_pic_ack_ipi() |
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| 558 | { |
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| 559 | // get calling core local index |
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| 560 | lid_t lid = CURRENT_THREAD->core->lid; |
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[75] | 561 | |
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[407] | 562 | // get pointer on local XCU segment base |
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| 563 | uint32_t * base = soclib_pic_xcu_base(); |
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[75] | 564 | |
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[407] | 565 | // acknowlege IPI |
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[432] | 566 | uint32_t ack = base[ (XCU_WTI_REG << 5) | lid ]; |
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[407] | 567 | |
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| 568 | // we must make a fake use for ack value to avoid a warning |
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[424] | 569 | if( (ack + 1) == 0 ) asm volatile( "nop" ); |
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[407] | 570 | } |
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| 571 | |
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| 572 | |
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