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source: trunk/hal/tsar_mips32/drivers/soclib_pic.c @ 439

Last change on this file since 439 was 438, checked in by alain, 7 years ago
Fix a bug in scheduler related to RPC blocking.
File size: 20.9 KB

Line
1	/*
2	* soclib_pic.c - soclib PIC driver implementation.
3	*
4	* Author Alain Greiner (2016,2017)
5	*
6	* Copyright (c) UPMC Sorbonne Universites
7	*
8	* This file is part of ALMOS-MKH.
9	*
10	* ALMOS-MKH is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU General Public License as published by
12	* the Free Software Foundation; version 2.0 of the License.
13	*
14	* ALMOS-MKH is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* General Public License for more details.
18	*
19	* You should have received a copy of the GNU General Public License
20	* along with ALMOS-MKH; if not, write to the Free Software Foundation,
21	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22	*/
23
24	#include <hal_types.h>
25	#include <chdev.h>
26	#include <soclib_pic.h>
27	#include <errno.h>
28	#include <string.h>
29	#include <vfs.h>
30	#include <rpc.h>
31	#include <cluster.h>
32	#include <printk.h>
33	#include <core.h>
34	#include <thread.h>
35
36	//////////////////////////////////////////////////////////////////////////////////////
37	// Extern variables
38	//////////////////////////////////////////////////////////////////////////////////////
39
40	extern chdev_directory_t chdev_dir; // defined in chdev.h / allocated in kerneL-init.c
41
42	extern iopic_input_t iopic_input; // defined in dev_pic.h / allocated in kernel_init.c
43	extern lapic_input_t lapic_input; // defined in dev_pic.h / allocated in kernel_init.c
44
45
46
47	//////////////////////////////////////////////////////////////////////////////////////
48	// SOCLIB PIC private functions
49	//////////////////////////////////////////////////////////////////////////////////////
50
51	///////////////////////////////
52	uint32_t soclib_pic_wti_alloc()
53	{
54	uint32_t index;
55
56	// get pointer on cluster extension for SOCLIB PIC (XCU descriptor)
57	soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend;
58
59	assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) , __FUNCTION__ ,
60	"no free WTI found : too much external IRQs\n");
61
62	// update WTI allocator
63	index = ext_ptr->first_free_wti;
64	ext_ptr->first_free_wti++;
65
66	return index;
67
68	} // end soclib_pic_wti_alloc()
69
70	///////////////////////////////////////
71	inline uint32_t * soclib_pic_xcu_base()
72	{
73	return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base;
74	}
75
76	/////////////////////////////////////////////////////////
77	inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy )
78	{
79	soclib_pic_cluster_t * extend;
80
81	// get extended pointer on PIC extension in remote cluster
82	extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) );
83
84	return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) );
85
86	}
87
88	///////////////////////////////////////////
89	void soclib_pic_xcu_status( lid_t lid,
90	uint32_t * hwi_status,
91	uint32_t * wti_status,
92	uint32_t * pti_status )
93	{
94	// get local XCU segment base
95	uint32_t * base = soclib_pic_xcu_base();
96
97	// read PRIO register
98	// in TSAR : XCU output [4*lid] is connected to core [lid]
99	uint32_t prio = base[ (XCU_PRIO << 5) \| (lid<<2) ];
100
101	*wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
102	*hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0;
103	*pti_status = (prio & 0x1) ? (((prio >> 8) & 0x1F) + 1) : 0;
104
105	}
106
107	////////////////////////////////////////////////////
108	inline uint32_t soclib_pic_xcu_ack( uint32_t * reg )
109	{
110	return *reg;
111	}
112
113	/////////////////////////////
114	void soclib_pic_irq_handler()
115	{
116	uint32_t hwi_status; // HWI index + 1 / no pending HWI if 0
117	uint32_t wti_status; // WTI index + 1 / no pending WTI if 0
118	uint32_t pti_status; // PTI index + 1 / no pending PTI if 0
119	chdev_t * src_chdev; // pointer on source chdev descriptor
120	uint32_t index; // WTI / HWI / PTI index
121
122	uint32_t * xcu_base = soclib_pic_xcu_base();
123
124	core_t * core = CURRENT_THREAD->core;
125
126	// get XCU status
127	soclib_pic_xcu_status( core->lid,
128	&hwi_status,
129	&wti_status,
130	&pti_status );
131
132	#if DEBUG_HAL_IRQS
133	uint32_t cycle = (uint32_t)hal_get_cycles();
134	if (DEBUG_HAL_IRQS < cycle )
135	printk("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x / cycle %d\n",
136	__FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status, cycle );
137	#endif
138
139	// analyse status and handle up to 3 pending IRQ (one WTI, one HWI, one PTI)
140
141	if( wti_status ) // pending WTI
142	{
143	index = wti_status - 1;
144
145	////////////////////////////////////////////////////////
146	if( index < LOCAL_CLUSTER->cores_nr ) // it is an IPI
147	{
148	assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" );
149
150	#if DEBUG_HAL_IRQS
151	if (DEBUG_HAL_IRQS < cycle )
152	printk("\n[DBG] %s : core[%x,%d] received an IPI\n", __FUNCTION__ , local_cxy , core->lid );
153	#endif
154	// acknowledge IRQ (this require an XCU read)
155	uint32_t ack = xcu_base[(XCU_WTI_REG << 5) \| core->lid];
156
157	// check RPC FIFO, and activate or create a RPC thread
158	// condition is always true, but we must use the ack value
159	if( ack + 1 ) rpc_check();
160	}
161	////////////////////////////////////////////////////////////////
162	else // it is an external IRQ
163	{
164	// get pointer on source chdev
165	src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index];
166
167	if( src_chdev == NULL ) // strange, but not fatal
168	{
169	printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n",
170	__FUNCTION__ , index , core->lid , local_cxy );
171
172	core->spurious_irqs ++;
173
174	// disable WTI in local XCU controller
175	xcu_base[(XCU_MSK_WTI_DISABLE << 5) \| core->lid] = 1 << core->lid;
176
177	hal_fence();
178	}
179	else // call relevant ISR
180	{
181
182	#if DEBUG_HAL_IRQS
183	if (DEBUG_HAL_IRQS < cycle )
184	printk("\n[DBG] %s : core[%x,%d] received external WTI %d\n",
185	__FUNCTION__ , local_cxy , core->lid , index );
186	#endif
187	// call ISR
188	src_chdev->isr( src_chdev );
189	}
190	}
191	}
192
193	/////////////////////////////////////////////////////////////
194	if( hwi_status ) // It is an Internal IRQ
195	{
196	index = hwi_status - 1;
197
198	// get pointer on source chdev
199	src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index];
200
201	if( src_chdev == NULL ) // strange, but not fatal
202	{
203	printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n",
204	__FUNCTION__ , index , core->lid , local_cxy );
205
206	core->spurious_irqs ++;
207
208	// disable HWI in local XCU controller
209	xcu_base[(XCU_MSK_HWI_DISABLE << 5) \| core->lid] = 1 << core->lid;
210
211	hal_fence();
212	}
213	else // call relevant ISR
214	{
215
216	#if DEBUG_HAL_IRQS
217	if (DEBUG_HAL_IRQS < cycle )
218	printk("\n[DBG] %s : core[%x,%d] received HWI %d\n",
219	__FUNCTION__ , local_cxy , core->lid , index );
220	#endif
221	// call ISR
222	src_chdev->isr( src_chdev );
223	}
224	}
225	///////////////////////////////////////////////////////
226	if( pti_status ) // It is a Timer IRQ
227	{
228	index = pti_status - 1;
229
230	assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n");
231
232	#if DEBUG_HAL_IRQS
233	if (DEBUG_HAL_IRQS < cycle )
234	printk("\n[DBG] %s : core[%x,%d] received PTI %d\n",
235	__FUNCTION__ , core->lid , local_cxy , index );
236	#endif
237	// acknowledge IRQ (this require a read access to XCU)
238	uint32_t ack = xcu_base[(XCU_PTI_ACK << 5) \| core->lid];
239
240	// execute all actions related to TICK event
241	// condition is always true, but we must use the ack value
242	if( ack + 1 ) core_clock( core );
243	}
244	} // end soclib_pic_irq_handler()
245
246
247
248
249	//////////////////////////////////////////////////////////////////////////////////////
250	// SOCLIC PIC device generic API
251	//////////////////////////////////////////////////////////////////////////////////////
252
253	/////////////////////////////////////
254	void soclib_pic_init( chdev_t * pic )
255	{
256	uint32_t i; // for loop on IOPIC inputs
257	uint32_t x; // for loop on clusters in a row
258	uint32_t y; // for loop on clusters in a column inputs
259	uint32_t lid; // for loop on cores in a cluster
260
261	// get target architecture parameters
262	cluster_t * cluster = LOCAL_CLUSTER;
263	uint32_t x_size = cluster->x_size;
264	uint32_t y_size = cluster->y_size;
265	uint32_t y_width = cluster->y_width;
266	uint32_t ncores = cluster->cores_nr;
267
268	// get IOPIC controller cluster and segment base pointer
269	cxy_t iopic_seg_cxy = (cxy_t)GET_CXY( pic->base );
270	uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );
271
272	// reset the IOPIC component registers : disable all input IRQs
273	for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
274	{
275	xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy,
276	iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK );
277	hal_remote_sw( iopic_seg_xp , 0 );
278	}
279
280	// GET XCU controller segment base
281	uint32_t * base = soclib_pic_xcu_base();
282
283	// reset the XCU component registers in all clusters:
284	// mask all HWIs, all WTIs, and all PTIs, for all cores
285	for( x = 0 ; x < x_size ; x++ )
286	{
287	for( y = 0 ; y < y_size ; y++ )
288	{
289	for( lid = 0 ; lid < ncores ; lid++ )
290	{
291	cxy_t cxy = (x<<y_width) + y;
292	xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 \| lid) );
293	xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 \| lid) );
294	xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 \| lid) );
295	hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF );
296	hal_remote_sw( wti_mask_xp , 0xFFFFFFFF );
297	hal_remote_sw( pti_mask_xp , 0xFFFFFFFF );
298	}
299	}
300	}
301	} // end soclib_pic_init()
302
303	//////////////////////////////////////////////////
304	void soclib_pic_extend_init( uint32_t * xcu_base )
305	{
306	soclib_pic_cluster_t * cluster_ext_ptr;
307	soclib_pic_core_t * core_ext_ptr;
308	kmem_req_t req;
309	uint32_t lid;
310	uint32_t idx;
311
312	cluster_t * cluster = LOCAL_CLUSTER;
313
314	// create core extension for all cores in cluster
315	for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
316	{
317	// allocate memory for core extension
318	req.type = KMEM_GENERIC;
319	req.size = sizeof(soclib_pic_core_t);
320	req.flags = AF_KERNEL;
321	core_ext_ptr = kmem_alloc( &req );
322
323	assert( (core_ext_ptr != NULL) , __FUNCTION__ ,
324	"cannot allocate memory for core extension\n");
325
326	// reset the HWI / WTI interrupt vectors
327	for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL;
328	for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL;
329
330	// register PIC extension in core descriptor
331	cluster->core_tbl[lid].pic_extend = core_ext_ptr;
332	}
333
334	// allocate memory for cluster extension
335	req.type = KMEM_GENERIC;
336	req.size = sizeof(soclib_pic_cluster_t);
337	req.flags = AF_KERNEL;
338	cluster_ext_ptr = kmem_alloc( &req );
339
340	assert( (cluster_ext_ptr != NULL) , __FUNCTION__ ,
341	"cannot allocate memory for cluster extension\n");
342
343	// get XCU characteristics from the XCU config register
344	uint32_t config = xcu_base[XCU_CONFIG<<5];
345	uint32_t wti_nr = (config >> 16) & 0xFF;
346	uint32_t hwi_nr = (config >> 8 ) & 0xFF;
347	uint32_t pti_nr = (config ) & 0xFF;
348
349	// initialize the cluster extension
350	// The first WTI slots are for IPIs (one slot per core)
351	cluster_ext_ptr->xcu_base = xcu_base;
352	cluster_ext_ptr->hwi_nr = hwi_nr;
353	cluster_ext_ptr->wti_nr = wti_nr;
354	cluster_ext_ptr->pti_nr = pti_nr;
355	cluster_ext_ptr->first_free_wti = cluster->cores_nr;
356
357	// register PIC extension in cluster manager
358	cluster->pic_extend = cluster_ext_ptr;
359
360	} // end soclib_pic_extend_init()
361
362	////////////////////////////////////////
363	void soclib_pic_bind_irq( lid_t lid,
364	chdev_t * src_chdev )
365	{
366
367	#if DEBUG_HAL_IRQS
368	uint32_t cycle = (uint32_t)hal_get_cycles();
369	if( DEBUG_HAL_IRQS < cycle )
370	printk("\n[DBG] %s : thread %x enter for core[%x,%d] / cycle %d\n",
371	__FUNCTION__ , CURRENT_THREAD , local_cxy , lid , cycle );
372	#endif
373
374	// get extended & local pointers on PIC chdev descriptor
375	xptr_t pic_xp = chdev_dir.pic;
376	cxy_t pic_cxy = GET_CXY( pic_xp );
377	chdev_t * pic_ptr = (chdev_t *)GET_PTR( pic_xp );
378
379	// get extended and local pointers on IOPIC segment base
380	xptr_t seg_pic_xp = hal_remote_lwd( XPTR( pic_cxy , &pic_ptr->base ) );
381	cxy_t seg_pic_cxy = GET_CXY( seg_pic_xp );
382	uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp );
383
384	// get local pointer on XCU segment base
385	uint32_t * seg_xcu_ptr = soclib_pic_xcu_base();
386
387	// get the source chdev functionnal type, channel, and direction
388	uint32_t func = src_chdev->func;
389	uint32_t channel = src_chdev->channel;
390	bool_t is_rx = src_chdev->is_rx;
391
392	if( (func == DEV_FUNC_IOC) \|\| (func == DEV_FUNC_NIC) \|\|
393	(func == DEV_FUNC_TXT) \|\| (func == DEV_FUNC_IOB) ) // external IRQ => WTI
394	{
395	// get external IRQ index
396	uint32_t hwi_id;
397	if ( func == DEV_FUNC_IOC ) hwi_id = iopic_input.ioc[channel];
398	else if( func == DEV_FUNC_TXT && is_rx ) hwi_id = iopic_input.txt_rx[channel];
399	else if( func == DEV_FUNC_TXT && !is_rx ) hwi_id = iopic_input.txt_tx[channel];
400	else if( (func == DEV_FUNC_NIC) && is_rx ) hwi_id = iopic_input.nic_rx[channel];
401	else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel];
402	else if( func == DEV_FUNC_IOB ) hwi_id = iopic_input.iob;
403	else assert( false , __FUNCTION__ , "illegal device functionnal type\n");
404
405	// get a WTI mailbox from local XCU descriptor
406	uint32_t wti_id = soclib_pic_wti_alloc();
407
408	// register IRQ type and index in chdev
409	src_chdev->irq_type = SOCLIB_TYPE_WTI;
410	src_chdev->irq_id = wti_id;
411
412	// compute extended pointer on WTI mailbox in local XCU
413	xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) \| wti_id] );
414
415	// set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC
416	uint32_t lsb_wdata = (uint32_t)wti_xp;
417	uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
418	xptr_t lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS );
419	xptr_t msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND );
420	hal_remote_sw( lsb_xp , lsb_wdata );
421	hal_remote_sw( msb_xp , msb_wdata );
422
423	// enable IRQ in IOPIC
424	hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
425
426	// update the WTI interrupt vector for core[lid]
427	core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
428	((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
429
430	#if DEBUG_HAL_IRQS
431	if( DEBUG_HAL_IRQS < cycle )
432	printk("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
433	__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
434	#endif
435
436	}
437	else if( (func == DEV_FUNC_DMA) \|\| (func == DEV_FUNC_MMC) ) // internal IRQ => HWI
438	{
439	// get internal IRQ index
440	uint32_t hwi_id;
441	if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel];
442	else hwi_id = lapic_input.mmc;
443
444	// register IRQ type and index in chdev
445	src_chdev->irq_type = SOCLIB_TYPE_HWI;
446	src_chdev->irq_id = hwi_id;
447
448	// update the HWI interrupt vector for core[lid]
449	core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
450	((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev;
451
452	#if DEBUG_HAL_IRQS
453	if( DEBUG_HAL_IRQS < cycle )
454	printk("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
455	__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );
456	#endif
457
458	}
459	else
460	{
461	assert( false , __FUNCTION__ , "illegal device functionnal type\n" );
462	}
463	} // end soclib_pic_bind_irq();
464
465	///////////////////////////////////////
466	void soclib_pic_enable_irq( lid_t lid,
467	xptr_t src_chdev_xp )
468	{
469	// get cluster and local pointer on remote src_chdev
470	cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp );
471	chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
472
473	// get local pointer on remote XCU segment base
474	uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
475
476	// get the source chdev IRQ type and index
477	uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
478	uint32_t irq_id = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
479
480	if( irq_type == SOCLIB_TYPE_HWI )
481	{
482	// enable this HWI in remote XCU controller
483	// in TSAR : XCU output [4*lid] is connected to core [lid]
484	hal_remote_sw( XPTR( src_chdev_cxy ,
485	&seg_xcu_ptr[ (XCU_MSK_HWI_ENABLE << 5) \| (lid<<4) ] ) , (1 << irq_id) );
486	}
487	else if( irq_type == SOCLIB_TYPE_WTI )
488	{
489	// enable this WTI in remote XCU controller
490	// in TSAR : XCU output [4*lid] is connected to core [lid]
491	hal_remote_sw( XPTR( src_chdev_cxy ,
492	&seg_xcu_ptr[ (XCU_MSK_WTI_ENABLE << 5) \| (lid<<4) ] ) , (1 << irq_id) );
493	}
494	else
495	{
496	assert( false , __FUNCTION__ , "illegal IRQ type\n" );
497	}
498	} // end soclib_pic_enable_irq()
499
500	////////////////////////////////////////
501	void soclib_pic_disable_irq( lid_t lid,
502	xptr_t src_chdev_xp )
503	{
504	// get cluster and local pointer on remote src_chdev
505	cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp );
506	chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
507
508	// get local pointer on remote XCU segment base
509	uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
510
511	// get the source chdev IRQ type and index
512	uint32_t irq_type = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
513	uint32_t irq_id = hal_remote_lw( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
514
515	if( irq_type == SOCLIB_TYPE_HWI )
516	{
517	// enable this HWI in remote XCU controller
518	// in TSAR : XCU output [4*lid] is connected to core [lid]
519	hal_remote_sw( XPTR( src_chdev_cxy ,
520	&seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
521	}
522	else if( irq_type == SOCLIB_TYPE_WTI )
523	{
524	// enable this WTI in remote XCU controller
525	// in TSAR : XCU output [4*lid] is connected to core [lid]
526	hal_remote_sw( XPTR( src_chdev_cxy ,
527	&seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) \| (lid<<4) ] ) , (1 << irq_id) );
528	}
529	else
530	{
531	assert( false , __FUNCTION__ , "illegal IRQ type\n" );
532	}
533	} // end soclib_pic_enable_irq()
534
535	///////////////////////////////////////////////
536	void soclib_pic_enable_timer( uint32_t period )
537	{
538	// calling core local index
539	lid_t lid = CURRENT_CORE->lid;
540
541	// get XCU segment base
542	uint32_t * base = soclib_pic_xcu_base();
543
544	// set period value in XCU (in cycles)
545	uint32_t cycles = period * SOCLIB_CYCLES_PER_MS;
546	base[(XCU_PTI_PER << 5) \| lid] = cycles;
547
548	// enable PTI in local XCU controller
549	// In TSAR : XCU output [4*lid] is connected to core [lid]
550	base[ (XCU_MSK_PTI_ENABLE << 5) \| (lid<<2) ] = 1 << lid;
551	}
552
553	////////////////////////////
554	void soclib_pic_enable_ipi()
555	{
556	// calling core local index
557	lid_t lid = CURRENT_CORE->lid;
558
559	// get XCU segment base
560	uint32_t * base = soclib_pic_xcu_base();
561
562	// enable WTI in local XCU controller
563	// In TSAR : XCU output [4*lid] is connected to core [lid]
564	base[ (XCU_MSK_WTI_ENABLE << 5) \| (lid<<2) ] = 1 << lid;
565	}
566
567	///////////////////////////////////////
568	void soclib_pic_send_ipi( cxy_t cxy,
569	lid_t lid )
570	{
571	// get pointer on local XCU segment base
572	uint32_t * base = soclib_pic_xcu_base();
573
574	// write to WTI mailbox[cxy][lid]
575	hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) \| lid ] ) , 0 );
576	}
577
578	/////////////////////////
579	void soclib_pic_ack_ipi()
580	{
581	// get calling core local index
582	lid_t lid = CURRENT_THREAD->core->lid;
583
584	// get pointer on local XCU segment base
585	uint32_t * base = soclib_pic_xcu_base();
586
587	// acknowlege IPI
588	uint32_t ack = base[ (XCU_WTI_REG << 5) \| lid ];
589
590	// we must make a fake use for ack value to avoid a warning
591	if( (ack + 1) == 0 ) asm volatile( "nop" );
592	}
593
594

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