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source: trunk/hal/tsar_mips32/drivers/soclib_pic.c @ 604

Last change on this file since 604 was 570, checked in by alain, 6 years ago
Introduction of the soclib_mty driver for the TSAR-LETI architecture.
File size: 20.3 KB

Line
1	/*
2	* soclib_pic.c - soclib PIC driver implementation.
3	*
4	* Author Alain Greiner (2016,2017)
5	*
6	* Copyright (c) UPMC Sorbonne Universites
7	*
8	* This file is part of ALMOS-MKH.
9	*
10	* ALMOS-MKH is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU General Public License as published by
12	* the Free Software Foundation; version 2.0 of the License.
13	*
14	* ALMOS-MKH is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* General Public License for more details.
18	*
19	* You should have received a copy of the GNU General Public License
20	* along with ALMOS-MKH; if not, write to the Free Software Foundation,
21	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22	*/
23
24	#include <hal_kernel_types.h>
25	#include <chdev.h>
26	#include <soclib_pic.h>
27	#include <errno.h>
28	#include <string.h>
29	#include <vfs.h>
30	#include <rpc.h>
31	#include <cluster.h>
32	#include <printk.h>
33	#include <core.h>
34	#include <thread.h>
35
36	//////////////////////////////////////////////////////////////////////////////////////
37	// Extern variables
38	//////////////////////////////////////////////////////////////////////////////////////
39
40	extern chdev_directory_t chdev_dir; // defined in chdev.h / allocated in kerneL-init.c
41
42	extern iopic_input_t iopic_input; // defined in dev_pic.h / allocated in kernel_init.c
43	extern lapic_input_t lapic_input; // defined in dev_pic.h / allocated in kernel_init.c
44
45
46
47	//////////////////////////////////////////////////////////////////////////////////////
48	// SOCLIB PIC private functions
49	//////////////////////////////////////////////////////////////////////////////////////
50
51	/////////////////////////////////////
52	uint32_t soclib_pic_wti_alloc( void )
53	{
54	uint32_t index;
55
56	// get pointer on cluster extension for SOCLIB PIC (XCU descriptor)
57	soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend;
58
59	assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) ,
60	"no free WTI found : too much external IRQs\n");
61
62	// update WTI allocator
63	index = ext_ptr->first_free_wti;
64	ext_ptr->first_free_wti++;
65
66	return index;
67
68	} // end soclib_pic_wti_alloc()
69
70	/////////////////////////////////////////////
71	inline uint32_t * soclib_pic_xcu_base( void )
72	{
73	return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base;
74	}
75
76	/////////////////////////////////////////////////////////
77	inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy )
78	{
79	soclib_pic_cluster_t * extend;
80
81	// get extended pointer on PIC extension in remote cluster
82	extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) );
83
84	return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) );
85
86	}
87
88	///////////////////////////////////////////
89	void soclib_pic_xcu_status( lid_t lid,
90	uint32_t * hwi_status,
91	uint32_t * wti_status,
92	uint32_t * pti_status )
93	{
94	// get local XCU segment base
95	uint32_t * base = soclib_pic_xcu_base();
96
97	// read PRIO register
98	// in TSAR : XCU output [4*lid] is connected to core [lid]
99	uint32_t prio = base[ (XCU_PRIO << 5) \| (lid<<2) ];
100
101	*wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
102	*hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0;
103	*pti_status = (prio & 0x1) ? (((prio >> 8) & 0x1F) + 1) : 0;
104
105	}
106
107	////////////////////////////////////////////////////
108	inline uint32_t soclib_pic_xcu_ack( uint32_t * reg )
109	{
110	return *reg;
111	}
112
113	///////////////////////////////////
114	void soclib_pic_irq_handler( void )
115	{
116	uint32_t hwi_status; // HWI index + 1 / no pending HWI if 0
117	uint32_t wti_status; // WTI index + 1 / no pending WTI if 0
118	uint32_t pti_status; // PTI index + 1 / no pending PTI if 0
119	chdev_t * src_chdev; // pointer on source chdev descriptor
120	uint32_t index; // WTI / HWI / PTI index
121
122	uint32_t * xcu_base = soclib_pic_xcu_base();
123
124	core_t * core = CURRENT_THREAD->core;
125
126	// get XCU status
127	soclib_pic_xcu_status( core->lid,
128	&hwi_status,
129	&wti_status,
130	&pti_status );
131
132	#if DEBUG_HAL_IRQS
133	uint32_t cycle = (uint32_t)hal_get_cycles();
134	if (DEBUG_HAL_IRQS < cycle )
135	printk("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x / cycle %d\n",
136	__FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status, cycle );
137	#endif
138
139	// analyse status and handle up to 3 pending IRQs (one WTI, one HWI, one PTI)
140
141	if( wti_status ) // pending WTI
142	{
143	index = wti_status - 1;
144
145	////////////////////////////////////////////////////////
146	if( index < LOCAL_CLUSTER->cores_nr ) // it is an IPI
147	{
148	assert( (index == core->lid) , "illegal IPI index" );
149
150	#if DEBUG_HAL_IRQS
151	if (DEBUG_HAL_IRQS < cycle )
152	printk("\n[DBG] %s : core[%x,%d] handling IPI\n", __FUNCTION__ , local_cxy , core->lid );
153	#endif
154	// acknowledge IRQ (this require an XCU read)
155	uint32_t ack = xcu_base[(XCU_WTI_REG << 5) \| core->lid];
156
157	// check RPC FIFO, and activate or create a RPC thread
158	// (condition is always true, but we use the ack value to avoid a GCC warning)
159	if( ack + 1 ) sched_yield("IPI received");
160	}
161	////////////////////////////////////////////////////////////////
162	else // it is an external IRQ
163	{
164	// get pointer on source chdev
165	src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index];
166
167	if( src_chdev == NULL ) // strange, but not fatal
168	{
169	printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n",
170	__FUNCTION__ , index , core->lid , local_cxy );
171
172	core->spurious_irqs ++;
173
174	// disable WTI in local XCU controller
175	xcu_base[(XCU_MSK_WTI_DISABLE << 5) \| core->lid] = 1 << core->lid;
176
177	hal_fence();
178	}
179	else // call relevant ISR
180	{
181
182	#if DEBUG_HAL_IRQS
183	if (DEBUG_HAL_IRQS < cycle )
184	printk("\n[DBG] %s : core[%x,%d] handling external WTI %d\n",
185	__FUNCTION__ , local_cxy , core->lid , index );
186	#endif
187	// call ISR
188	src_chdev->isr( src_chdev );
189	}
190	}
191	}
192
193	/////////////////////////////////////////////////////////////
194	if( hwi_status ) // It is an Internal IRQ
195	{
196	index = hwi_status - 1;
197
198	// get pointer on source chdev
199	src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index];
200
201	if( src_chdev == NULL ) // strange, but not fatal
202	{
203	printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n",
204	__FUNCTION__ , index , core->lid , local_cxy );
205
206	core->spurious_irqs ++;
207
208	// disable HWI in local XCU controller
209	xcu_base[(XCU_MSK_HWI_DISABLE << 5) \| core->lid] = 1 << core->lid;
210
211	hal_fence();
212	}
213	else // call relevant ISR
214	{
215
216	#if DEBUG_HAL_IRQS
217	if (DEBUG_HAL_IRQS < cycle )
218	printk("\n[DBG] %s : core[%x,%d] handling HWI %d\n",
219	__FUNCTION__ , local_cxy , core->lid , index );
220	#endif
221	// call ISR
222	src_chdev->isr( src_chdev );
223	}
224	}
225	///////////////////////////////////////////////////////
226	if( pti_status ) // It is a Timer IRQ
227	{
228	index = pti_status - 1;
229
230	assert( (index == core->lid) , "unconsistent PTI index\n");
231
232	#if DEBUG_HAL_IRQS
233	if (DEBUG_HAL_IRQS < cycle )
234	printk("\n[DBG] %s : core[%x,%d] handling PTI %d\n",
235	__FUNCTION__ , core->lid , local_cxy , index );
236	#endif
237	// acknowledge IRQ (this require a read access to XCU)
238	uint32_t ack = xcu_base[(XCU_PTI_ACK << 5) \| core->lid];
239
240	// execute all actions related to TICK event
241	// condition is always true, but we use the ack value
242	// to avoid a GCC warning
243	if( ack + 1 ) core_clock( core );
244	}
245	} // end soclib_pic_irq_handler()
246
247
248
249
250	//////////////////////////////////////////////////////////////////////////////////////
251	// SOCLIC PIC device generic API
252	//////////////////////////////////////////////////////////////////////////////////////
253
254	/////////////////////////////////////
255	void soclib_pic_init( chdev_t * pic )
256	{
257	uint32_t i; // for loop on IOPIC inputs
258
259	// get IOPIC controller cluster and segment base pointer
260	cxy_t iopic_seg_cxy = GET_CXY( pic->base );
261	uint32_t * iopic_seg_ptr = GET_PTR( pic->base );
262
263	// reset the IOPIC component registers : disable all input IRQs
264	for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
265	{
266	xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy,
267	iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK );
268	hal_remote_s32( iopic_seg_xp , 0 );
269	}
270
271	} // end soclib_pic_init()
272
273	//////////////////////////////////////////////////
274	void soclib_pic_extend_init( uint32_t * xcu_base )
275	{
276	soclib_pic_cluster_t * cluster_ext_ptr;
277	soclib_pic_core_t * core_ext_ptr;
278	kmem_req_t req;
279	uint32_t lid;
280	uint32_t idx;
281
282	cluster_t * cluster = LOCAL_CLUSTER;
283
284	// create core extension for all cores in cluster
285	for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
286	{
287	// allocate memory for core extension
288	req.type = KMEM_GENERIC;
289	req.size = sizeof(soclib_pic_core_t);
290	req.flags = AF_KERNEL;
291	core_ext_ptr = kmem_alloc( &req );
292
293	assert( (core_ext_ptr != NULL) ,
294	"cannot allocate memory for core extension\n");
295
296	// reset the HWI / WTI interrupt vectors
297	for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL;
298	for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL;
299
300	// register PIC extension in core descriptor
301	cluster->core_tbl[lid].pic_extend = core_ext_ptr;
302	}
303
304	// allocate memory for cluster extension
305	req.type = KMEM_GENERIC;
306	req.size = sizeof(soclib_pic_cluster_t);
307	req.flags = AF_KERNEL;
308	cluster_ext_ptr = kmem_alloc( &req );
309
310	assert( (cluster_ext_ptr != NULL) ,
311	"cannot allocate memory for cluster extension\n");
312
313	// get XCU characteristics from the XCU config register
314	uint32_t config = xcu_base[XCU_CONFIG<<5];
315	uint32_t wti_nr = (config >> 16) & 0xFF;
316	uint32_t hwi_nr = (config >> 8 ) & 0xFF;
317	uint32_t pti_nr = (config ) & 0xFF;
318
319	// initialize the cluster extension
320	// The first WTI slots are for IPIs (one slot per core)
321	cluster_ext_ptr->xcu_base = xcu_base;
322	cluster_ext_ptr->hwi_nr = hwi_nr;
323	cluster_ext_ptr->wti_nr = wti_nr;
324	cluster_ext_ptr->pti_nr = pti_nr;
325	cluster_ext_ptr->first_free_wti = cluster->cores_nr;
326
327	// register PIC extension in cluster manager
328	cluster->pic_extend = cluster_ext_ptr;
329
330	// reset the XCU component registers
331	// mask all HWIs, all WTIs, and all PTIs, for all cores in local cluster
332	for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
333	{
334	xcu_base[XCU_MSK_HWI_DISABLE << 5 \| lid] = 0xFFFFFFFF;
335	xcu_base[XCU_MSK_WTI_DISABLE << 5 \| lid] = 0xFFFFFFFF;
336	xcu_base[XCU_MSK_PTI_DISABLE << 5 \| lid] = 0xFFFFFFFF;
337	}
338
339	} // end soclib_pic_extend_init()
340
341	////////////////////////////////////////
342	void soclib_pic_bind_irq( lid_t lid,
343	chdev_t * src_chdev )
344	{
345
346	#if DEBUG_HAL_IRQS
347	uint32_t cycle = (uint32_t)hal_get_cycles();
348	if( DEBUG_HAL_IRQS < cycle )
349	printk("\n[DBG] %s : thread %x enter for core[%x,%d] / cycle %d\n",
350	__FUNCTION__ , CURRENT_THREAD , local_cxy , lid , cycle );
351	#endif
352
353	// get extended & local pointers on PIC chdev descriptor
354	xptr_t pic_xp = chdev_dir.pic;
355	cxy_t pic_cxy = GET_CXY( pic_xp );
356	chdev_t * pic_ptr = (chdev_t *)GET_PTR( pic_xp );
357
358	// get extended and local pointers on IOPIC segment base
359	xptr_t seg_pic_xp = hal_remote_l64( XPTR( pic_cxy , &pic_ptr->base ) );
360	cxy_t seg_pic_cxy = GET_CXY( seg_pic_xp );
361	uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp );
362
363	// get local pointer on XCU segment base
364	uint32_t * seg_xcu_ptr = soclib_pic_xcu_base();
365
366	// get the source chdev functionnal type, channel, and direction
367	uint32_t func = src_chdev->func;
368	uint32_t impl = src_chdev->impl;
369	uint32_t channel = src_chdev->channel;
370	bool_t is_rx = src_chdev->is_rx;
371
372	if( (func == DEV_FUNC_IOC && impl == IMPL_IOC_BDV) \|\| (func == DEV_FUNC_NIC) \|\|
373	(func == DEV_FUNC_TXT && impl == IMPL_TXT_TTY) \|\| (func == DEV_FUNC_IOB) ) // external IRQ => WTI
374	{
375	// get external IRQ index
376	uint32_t hwi_id;
377	if ( func == DEV_FUNC_IOC ) hwi_id = iopic_input.ioc[channel];
378	else if( func == DEV_FUNC_TXT && is_rx ) hwi_id = iopic_input.txt_rx[channel];
379	else if( func == DEV_FUNC_TXT && !is_rx ) hwi_id = iopic_input.txt_tx[channel];
380	else if( (func == DEV_FUNC_NIC) && is_rx ) hwi_id = iopic_input.nic_rx[channel];
381	else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel];
382	else if( func == DEV_FUNC_IOB ) hwi_id = iopic_input.iob;
383	else assert( false , "illegal device functionnal type\n");
384
385	// get a WTI mailbox from local XCU descriptor
386	uint32_t wti_id = soclib_pic_wti_alloc();
387
388	// register IRQ type and index in chdev
389	src_chdev->irq_type = SOCLIB_TYPE_WTI;
390	src_chdev->irq_id = wti_id;
391
392	// compute extended pointer on WTI mailbox in local XCU
393	xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) \| wti_id] );
394
395	// set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC
396	uint32_t lsb_wdata = (uint32_t)wti_xp;
397	uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
398	xptr_t lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS );
399	xptr_t msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND );
400	hal_remote_s32( lsb_xp , lsb_wdata );
401	hal_remote_s32( msb_xp , msb_wdata );
402
403	// enable IRQ in IOPIC
404	hal_remote_s32( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
405
406	// update the WTI interrupt vector for core[lid]
407	core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
408	((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
409
410	#if DEBUG_HAL_IRQS
411	if( DEBUG_HAL_IRQS < cycle )
412	printk("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
413	__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
414	#endif
415
416	}
417	else if( (func == DEV_FUNC_DMA) \|\| (func == DEV_FUNC_MMC) \|\|
418	(func == DEV_FUNC_TXT && impl == IMPL_TXT_MTY) \|\|
419	(func == DEV_FUNC_IOC && impl == IMPL_IOC_SPI) ) // internal IRQ => HWI
420	{
421	// get internal IRQ index
422	uint32_t hwi_id;
423	if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel];
424	else if (func == DEV_FUNC_TXT ) hwi_id = lapic_input.mtty;
425	else if (func == DEV_FUNC_IOC ) hwi_id = lapic_input.sdcard;
426	else hwi_id = lapic_input.mmc;
427
428	// register IRQ type and index in chdev
429	src_chdev->irq_type = SOCLIB_TYPE_HWI;
430	src_chdev->irq_id = hwi_id;
431
432	// update the HWI interrupt vector for core[lid]
433	core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
434	((soclib_pic_core_t *)core->pic_extend)->hwi_vector[hwi_id] = src_chdev;
435
436	#if DEBUG_HAL_IRQS
437	if( DEBUG_HAL_IRQS < cycle )
438	printk("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
439	__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );
440	#endif
441
442	}
443	else
444	{
445	assert( false , "illegal device functionnal type\n" );
446	}
447	} // end soclib_pic_bind_irq();
448
449	///////////////////////////////////////
450	void soclib_pic_enable_irq( lid_t lid,
451	xptr_t src_chdev_xp )
452	{
453	// get cluster and local pointer on remote src_chdev
454	cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp );
455	chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
456
457	// get local pointer on remote XCU segment base
458	uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
459
460	// get the source chdev IRQ type and index
461	uint32_t irq_type = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
462	uint32_t irq_id = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
463
464	if( irq_type == SOCLIB_TYPE_HWI )
465	{
466	// enable this HWI in remote XCU controller
467	// in TSAR : XCU output [4*lid] is connected to core [lid]
468	hal_remote_s32( XPTR( src_chdev_cxy ,
469	&seg_xcu_ptr[ (XCU_MSK_HWI_ENABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
470	}
471	else if( irq_type == SOCLIB_TYPE_WTI )
472	{
473	// enable this WTI in remote XCU controller
474	// in TSAR : XCU output [4*lid] is connected to core [lid]
475	hal_remote_s32( XPTR( src_chdev_cxy ,
476	&seg_xcu_ptr[ (XCU_MSK_WTI_ENABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
477	}
478	else
479	{
480	assert( false , "illegal IRQ type\n" );
481	}
482	} // end soclib_pic_enable_irq()
483
484	////////////////////////////////////////
485	void soclib_pic_disable_irq( lid_t lid,
486	xptr_t src_chdev_xp )
487	{
488	// get cluster and local pointer on remote src_chdev
489	cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp );
490	chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
491
492	// get local pointer on remote XCU segment base
493	uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
494
495	// get the source chdev IRQ type and index
496	uint32_t irq_type = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
497	uint32_t irq_id = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
498
499	if( irq_type == SOCLIB_TYPE_HWI )
500	{
501	// enable this HWI in remote XCU controller
502	// in TSAR : XCU output [4*lid] is connected to core [lid]
503	hal_remote_s32( XPTR( src_chdev_cxy ,
504	&seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
505	}
506	else if( irq_type == SOCLIB_TYPE_WTI )
507	{
508	// enable this WTI in remote XCU controller
509	// in TSAR : XCU output [4*lid] is connected to core [lid]
510	hal_remote_s32( XPTR( src_chdev_cxy ,
511	&seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
512	}
513	else
514	{
515	assert( false , "illegal IRQ type\n" );
516	}
517	} // end soclib_pic_enable_irq()
518
519	///////////////////////////////////////////////
520	void soclib_pic_enable_timer( uint32_t period )
521	{
522	// calling core local index
523	lid_t lid = CURRENT_THREAD->core->lid;
524
525	// get XCU segment base
526	uint32_t * base = soclib_pic_xcu_base();
527
528	// set period value in XCU (in cycles)
529	uint32_t cycles = period * SOCLIB_CYCLES_PER_MS;
530	base[(XCU_PTI_PER << 5) \| lid] = cycles;
531
532	// enable PTI in local XCU controller
533	// In TSAR : XCU output [4*lid] is connected to core [lid]
534	base[ (XCU_MSK_PTI_ENABLE << 5) \| (lid<<2) ] = 1 << lid;
535	}
536
537	////////////////////////////
538	void soclib_pic_enable_ipi( void )
539	{
540	// calling core local index
541	lid_t lid = CURRENT_THREAD->core->lid;
542
543	// get XCU segment base
544	uint32_t * base = soclib_pic_xcu_base();
545
546	// enable WTI in local XCU controller
547	// In TSAR : XCU output [4*lid] is connected to core [lid]
548	base[ (XCU_MSK_WTI_ENABLE << 5) \| (lid<<2) ] = 1 << lid;
549	}
550
551	///////////////////////////////////////
552	void soclib_pic_send_ipi( cxy_t cxy,
553	lid_t lid )
554	{
555	// get pointer on local XCU segment base
556	uint32_t * base = soclib_pic_xcu_base();
557
558	// write to WTI mailbox[cxy][lid]
559	hal_remote_s32( XPTR( cxy , &base[(XCU_WTI_REG << 5) \| lid ] ) , 0 );
560	}
561
562	/////////////////////////
563	void soclib_pic_ack_ipi( void )
564	{
565	// get calling core local index
566	lid_t lid = CURRENT_THREAD->core->lid;
567
568	// get pointer on local XCU segment base
569	uint32_t * base = soclib_pic_xcu_base();
570
571	// acknowlege IPI
572	uint32_t ack = base[ (XCU_WTI_REG << 5) \| lid ];
573
574	// we must make a fake use for ack value to avoid a warning
575	if( (ack + 1) == 0 ) asm volatile( "nop" );
576	}
577
578

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