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source: trunk/hal/tsar_mips32/drivers/soclib_pic.c @ 682

Last change on this file since 682 was 679, checked in by alain, 4 years ago
Mainly cosmetic.
File size: 20.7 KB

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1	/*
2	* soclib_pic.c - soclib PIC driver implementation.
3	*
4	* Author Alain Greiner (2016,2017,2018,2019)
5	*
6	* Copyright (c) UPMC Sorbonne Universites
7	*
8	* This file is part of ALMOS-MKH.
9	*
10	* ALMOS-MKH is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU General Public License as published by
12	* the Free Software Foundation; version 2.0 of the License.
13	*
14	* ALMOS-MKH is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* General Public License for more details.
18	*
19	* You should have received a copy of the GNU General Public License
20	* along with ALMOS-MKH; if not, write to the Free Software Foundation,
21	* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22	*/
23
24	#include <hal_kernel_types.h>
25	#include <chdev.h>
26	#include <soclib_pic.h>
27	#include <errno.h>
28	#include <string.h>
29	#include <bits.h>
30	#include <vfs.h>
31	#include <rpc.h>
32	#include <cluster.h>
33	#include <printk.h>
34	#include <core.h>
35	#include <thread.h>
36
37	//////////////////////////////////////////////////////////////////////////////////////
38	// Extern variables
39	//////////////////////////////////////////////////////////////////////////////////////
40
41	extern chdev_directory_t chdev_dir; // defined in chdev.h / allocated in kerneL-init.c
42
43	extern iopic_input_t iopic_input; // defined in dev_pic.h / allocated in kernel_init.c
44	extern lapic_input_t lapic_input; // defined in dev_pic.h / allocated in kernel_init.c
45
46
47
48	//////////////////////////////////////////////////////////////////////////////////////
49	// SOCLIB PIC private functions
50	//////////////////////////////////////////////////////////////////////////////////////
51
52	/////////////////////////////////////
53	uint32_t soclib_pic_wti_alloc( void )
54	{
55	uint32_t index;
56
57	// get pointer on cluster extension for SOCLIB PIC (XCU descriptor)
58	soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend;
59
60	assert( __FUNCTION__, (ext_ptr->first_free_wti < ext_ptr->wti_nr) ,
61	"no free WTI found : too much external IRQs\n");
62
63	// update WTI allocator
64	index = ext_ptr->first_free_wti;
65	ext_ptr->first_free_wti++;
66
67	return index;
68
69	} // end soclib_pic_wti_alloc()
70
71	/////////////////////////////////////////////
72	inline uint32_t * soclib_pic_xcu_base( void )
73	{
74	return ((soclib_pic_cluster_t *)(LOCAL_CLUSTER->pic_extend))->xcu_base;
75	}
76
77	/////////////////////////////////////////////////////////
78	inline uint32_t * soclib_pic_remote_xcu_base( cxy_t cxy )
79	{
80	soclib_pic_cluster_t * extend;
81
82	// get extended pointer on PIC extension in remote cluster
83	extend = hal_remote_lpt( XPTR( cxy , &cluster_manager.pic_extend ) );
84
85	return (uint32_t *)hal_remote_lpt( XPTR( cxy , &extend->xcu_base ) );
86
87	}
88
89	///////////////////////////////////////////
90	void soclib_pic_xcu_status( lid_t lid,
91	uint32_t * hwi_status,
92	uint32_t * wti_status,
93	uint32_t * pti_status )
94	{
95	// get local XCU segment base
96	uint32_t * base = soclib_pic_xcu_base();
97
98	// read PRIO register
99	// in TSAR : XCU output [4*lid] is connected to core [lid]
100	uint32_t prio = base[ (XCU_PRIO << 5) \| (lid<<2) ];
101
102	*wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
103	*hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0;
104	*pti_status = (prio & 0x1) ? (((prio >> 8) & 0x1F) + 1) : 0;
105
106	}
107
108	////////////////////////////////////////////////////
109	inline uint32_t soclib_pic_xcu_ack( uint32_t * reg )
110	{
111	return *reg;
112	}
113
114	///////////////////////////////////
115	void soclib_pic_irq_handler( void )
116	{
117	uint32_t hwi_status; // HWI index + 1 / no pending HWI if 0
118	uint32_t wti_status; // WTI index + 1 / no pending WTI if 0
119	uint32_t pti_status; // PTI index + 1 / no pending PTI if 0
120	chdev_t * src_chdev; // pointer on source chdev descriptor
121	uint32_t index; // WTI / HWI / PTI index
122
123	uint32_t * xcu_base = soclib_pic_xcu_base();
124
125	core_t * core = CURRENT_THREAD->core;
126
127	// get XCU status
128	soclib_pic_xcu_status( core->lid,
129	&hwi_status,
130	&wti_status,
131	&pti_status );
132
133	#if DEBUG_HAL_IRQS
134	uint32_t cycle = (uint32_t)hal_get_cycles();
135	if (DEBUG_HAL_IRQS < cycle )
136	printk("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x / cycle %d\n",
137	__FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status, cycle );
138	#endif
139
140	// analyse status and handle up to 3 pending IRQs (one WTI, one HWI, one PTI)
141
142	if( wti_status ) // pending WTI
143	{
144	index = wti_status - 1;
145
146	////////////////////////////////////////////////////////
147	if( index < LOCAL_CLUSTER->cores_nr ) // it is an IPI
148	{
149	assert( __FUNCTION__, (index == core->lid) , "illegal IPI index" );
150
151	#if DEBUG_HAL_IRQS
152	if (DEBUG_HAL_IRQS < cycle )
153	printk("\n[DBG] %s : core[%x,%d] handling IPI\n", __FUNCTION__ , local_cxy , core->lid );
154	#endif
155	// acknowledge IRQ (this require an XCU read)
156	uint32_t ack = xcu_base[(XCU_WTI_REG << 5) \| core->lid];
157
158	// check RPC FIFO, and activate or create a RPC thread
159	// condition is always true, but we use the ack value
160	// to avoid a GCC warning
161	if( ack + 1 ) sched_yield("IPI received");
162	}
163	////////////////////////////////////////////////////////////////
164	else // it is an external IRQ
165	{
166	// get pointer on source chdev
167	src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index];
168
169	if( src_chdev == NULL ) // strange, but not fatal
170	{
171	printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n",
172	__FUNCTION__ , index , core->lid , local_cxy );
173
174	core->spurious_irqs ++;
175
176	// disable WTI in local XCU controller
177	xcu_base[(XCU_MSK_WTI_DISABLE << 5) \| core->lid] = 1 << core->lid;
178
179	hal_fence();
180	}
181	else // call relevant ISR
182	{
183
184	#if DEBUG_HAL_IRQS
185	if (DEBUG_HAL_IRQS < cycle )
186	printk("\n[DBG] %s : core[%x,%d] handling external WTI %d\n",
187	__FUNCTION__ , local_cxy , core->lid , index );
188	#endif
189	// call ISR
190	src_chdev->isr( src_chdev );
191	}
192	}
193	}
194
195	/////////////////////////////////////////////////////////////
196	if( hwi_status ) // It is an Internal IRQ
197	{
198	index = hwi_status - 1;
199
200	// get pointer on source chdev
201	src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index];
202
203	if( src_chdev == NULL ) // strange, but not fatal
204	{
205	printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n",
206	__FUNCTION__ , index , core->lid , local_cxy );
207
208	core->spurious_irqs ++;
209
210	// disable HWI in local XCU controller
211	xcu_base[(XCU_MSK_HWI_DISABLE << 5) \| core->lid] = 1 << core->lid;
212
213	hal_fence();
214	}
215	else // call relevant ISR
216	{
217
218	#if DEBUG_HAL_IRQS
219	if (DEBUG_HAL_IRQS < cycle )
220	printk("\n[DBG] %s : core[%x,%d] handling HWI %d\n",
221	__FUNCTION__ , local_cxy , core->lid , index );
222	#endif
223	// call ISR
224	src_chdev->isr( src_chdev );
225	}
226	}
227	///////////////////////////////////////////////////////
228	if( pti_status ) // It is a Timer IRQ
229	{
230	index = pti_status - 1;
231
232	assert( __FUNCTION__, (index == core->lid) , "unconsistent PTI index\n");
233
234	#if DEBUG_HAL_IRQS
235	if (DEBUG_HAL_IRQS < cycle )
236	printk("\n[DBG] %s : core[%x,%d] handling PTI %d\n",
237	__FUNCTION__ , core->lid , local_cxy , index );
238	#endif
239	// acknowledge IRQ (this require a read access to XCU)
240	uint32_t ack = xcu_base[(XCU_PTI_ACK << 5) \| core->lid];
241
242	// execute all actions related to TICK event
243	// condition is always true, but we use the ack value
244	// to avoid a GCC warning
245	if( ack + 1 ) core_clock( core );
246	}
247	} // end soclib_pic_irq_handler()
248
249
250
251
252	//////////////////////////////////////////////////////////////////////////////////////
253	// SOCLIC PIC device generic API
254	//////////////////////////////////////////////////////////////////////////////////////
255
256	/////////////////////////////////////
257	void soclib_pic_init( chdev_t * pic )
258	{
259	uint32_t i; // for loop on IOPIC inputs
260
261	// get IOPIC controller cluster and segment base pointer
262	cxy_t iopic_seg_cxy = GET_CXY( pic->base );
263	uint32_t * iopic_seg_ptr = GET_PTR( pic->base );
264
265	// reset the IOPIC component registers : disable all input IRQs
266	for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ )
267	{
268	xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy,
269	iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK );
270	hal_remote_s32( iopic_seg_xp , 0 );
271	}
272
273	} // end soclib_pic_init()
274
275	//////////////////////////////////////////////////
276	void soclib_pic_extend_init( uint32_t * xcu_base )
277	{
278	soclib_pic_cluster_t * cluster_ext_ptr;
279	soclib_pic_core_t * core_ext_ptr;
280	kmem_req_t req;
281	uint32_t lid;
282	uint32_t idx;
283
284	cluster_t * cluster = LOCAL_CLUSTER;
285
286	// create core extension for all cores in cluster
287	for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
288	{
289	// allocate memory for core extension
290	req.type = KMEM_KCM;
291	req.order = bits_log2( sizeof(soclib_pic_core_t) );
292	req.flags = AF_KERNEL;
293	core_ext_ptr = kmem_alloc( &req );
294
295	if( core_ext_ptr == NULL )
296	{
297	printk("\n[PANIC] in %s : cannot allocate memory for core extension\n",
298	__FUNCTION__ );
299	}
300
301	// reset the HWI / WTI interrupt vectors
302	for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL;
303	for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL;
304
305	// register PIC extension in core descriptor
306	cluster->core_tbl[lid].pic_extend = core_ext_ptr;
307	}
308
309	// allocate memory for cluster extension
310	req.type = KMEM_KCM;
311	req.order = bits_log2( sizeof(soclib_pic_cluster_t) );
312	req.flags = AF_KERNEL;
313	cluster_ext_ptr = kmem_alloc( &req );
314
315	if( cluster_ext_ptr == NULL )
316	{
317	printk("\n[PANIC] in %s : cannot allocate memory for cluster extension\n",
318	__FUNCTION__ );
319	}
320
321	assert( __FUNCTION__, (cluster_ext_ptr != NULL) , "cannot allocate memory for cluster extension");
322
323	// get XCU characteristics from the XCU config register
324	uint32_t config = xcu_base[XCU_CONFIG<<5];
325	uint32_t wti_nr = (config >> 16) & 0xFF;
326	uint32_t hwi_nr = (config >> 8 ) & 0xFF;
327	uint32_t pti_nr = (config ) & 0xFF;
328
329	// initialize the cluster extension
330	// The first WTI slots are for IPIs (one slot per core)
331	cluster_ext_ptr->xcu_base = xcu_base;
332	cluster_ext_ptr->hwi_nr = hwi_nr;
333	cluster_ext_ptr->wti_nr = wti_nr;
334	cluster_ext_ptr->pti_nr = pti_nr;
335	cluster_ext_ptr->first_free_wti = cluster->cores_nr;
336
337	// register PIC extension in cluster manager
338	cluster->pic_extend = cluster_ext_ptr;
339
340	// reset the XCU component registers
341	// mask all HWIs, all WTIs, and all PTIs, for all cores in local cluster
342	for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
343	{
344	xcu_base[XCU_MSK_HWI_DISABLE << 5 \| lid] = 0xFFFFFFFF;
345	xcu_base[XCU_MSK_WTI_DISABLE << 5 \| lid] = 0xFFFFFFFF;
346	xcu_base[XCU_MSK_PTI_DISABLE << 5 \| lid] = 0xFFFFFFFF;
347	}
348
349	} // end soclib_pic_extend_init()
350
351	////////////////////////////////////////
352	void soclib_pic_bind_irq( lid_t lid,
353	chdev_t * src_chdev )
354	{
355
356	#if DEBUG_HAL_IRQS
357	uint32_t cycle = (uint32_t)hal_get_cycles();
358	if( DEBUG_HAL_IRQS < cycle )
359	printk("\n[DBG] %s : thread %x enter for core[%x,%d] / cycle %d\n",
360	__FUNCTION__ , CURRENT_THREAD , local_cxy , lid , cycle );
361	#endif
362
363	// get extended & local pointers on PIC chdev descriptor
364	xptr_t pic_xp = chdev_dir.pic;
365	cxy_t pic_cxy = GET_CXY( pic_xp );
366	chdev_t * pic_ptr = (chdev_t *)GET_PTR( pic_xp );
367
368	// get extended and local pointers on IOPIC segment base
369	xptr_t seg_pic_xp = hal_remote_l64( XPTR( pic_cxy , &pic_ptr->base ) );
370	cxy_t seg_pic_cxy = GET_CXY( seg_pic_xp );
371	uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp );
372
373	// get local pointer on XCU segment base
374	uint32_t * seg_xcu_ptr = soclib_pic_xcu_base();
375
376	// get the source chdev functionnal type, channel, and direction
377	uint32_t func = src_chdev->func;
378	uint32_t impl = src_chdev->impl;
379	uint32_t channel = src_chdev->channel;
380	bool_t is_rx = src_chdev->is_rx;
381
382	if( (func == DEV_FUNC_IOC && impl == IMPL_IOC_BDV) \|\| (func == DEV_FUNC_NIC) \|\|
383	(func == DEV_FUNC_TXT && impl == IMPL_TXT_TTY) \|\| (func == DEV_FUNC_IOB) ) // external IRQ => WTI
384	{
385	// get external IRQ index
386	uint32_t hwi_id = 0;
387	if ( func == DEV_FUNC_IOC ) hwi_id = iopic_input.ioc[channel];
388	else if( func == DEV_FUNC_TXT && is_rx ) hwi_id = iopic_input.txt_rx[channel];
389	else if( func == DEV_FUNC_TXT && !is_rx ) hwi_id = iopic_input.txt_tx[channel];
390	else if( (func == DEV_FUNC_NIC) && is_rx ) hwi_id = iopic_input.nic_rx[channel];
391	else if( (func == DEV_FUNC_NIC) && !is_rx ) hwi_id = iopic_input.nic_tx[channel];
392	else if( func == DEV_FUNC_IOB ) hwi_id = iopic_input.iob;
393	else assert( __FUNCTION__, false , "illegal device functionnal type\n");
394
395	// get a WTI mailbox from local XCU descriptor
396	uint32_t wti_id = soclib_pic_wti_alloc();
397
398	// register IRQ type and index in chdev
399	src_chdev->irq_type = SOCLIB_TYPE_WTI;
400	src_chdev->irq_id = wti_id;
401
402	// compute extended pointer on WTI mailbox in local XCU
403	xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) \| wti_id] );
404
405	// set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC
406	uint32_t lsb_wdata = (uint32_t)wti_xp;
407	uint32_t msb_wdata = (uint32_t)(wti_xp >> 32);
408	xptr_t lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_ADDRESS );
409	xptr_t msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_EXTEND );
410	hal_remote_s32( lsb_xp , lsb_wdata );
411	hal_remote_s32( msb_xp , msb_wdata );
412
413	// enable IRQ in IOPIC
414	hal_remote_s32( XPTR( seg_pic_cxy , seg_pic_ptr+hwi_id*IOPIC_SPAN+IOPIC_MASK ), 1 );
415
416	// update the WTI interrupt vector for core[lid]
417	core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
418	((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev;
419
420	#if DEBUG_HAL_IRQS
421	if( DEBUG_HAL_IRQS < cycle )
422	printk("\n[DBG] %s : %s / channel = %d / rx = %d / hwi_id = %d / wti_id = %d / cluster = %x\n",
423	__FUNCTION__ , chdev_func_str( func ) , channel , is_rx , hwi_id , wti_id , local_cxy );
424	#endif
425
426	}
427	else if( (func == DEV_FUNC_DMA) \|\| (func == DEV_FUNC_MMC) \|\|
428	(func == DEV_FUNC_TXT && impl == IMPL_TXT_MTY) \|\|
429	(func == DEV_FUNC_IOC && impl == IMPL_IOC_SPI) ) // internal IRQ => HWI
430	{
431	// get internal IRQ index
432	uint32_t hwi_id;
433	if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel];
434	else if (func == DEV_FUNC_TXT ) hwi_id = lapic_input.mtty;
435	else if (func == DEV_FUNC_IOC ) hwi_id = lapic_input.sdcard;
436	else hwi_id = lapic_input.mmc;
437
438	// register IRQ type and index in chdev
439	src_chdev->irq_type = SOCLIB_TYPE_HWI;
440	src_chdev->irq_id = hwi_id;
441
442	// update the HWI interrupt vector for core[lid]
443	core_t * core = &LOCAL_CLUSTER->core_tbl[lid];
444	((soclib_pic_core_t *)core->pic_extend)->hwi_vector[hwi_id] = src_chdev;
445
446	#if DEBUG_HAL_IRQS
447	if( DEBUG_HAL_IRQS < cycle )
448	printk("\n[DBG] %s : %s / channel = %d / hwi_id = %d / cluster = %x\n",
449	__FUNCTION__ , chdev_func_str( func ) , channel , hwi_id , local_cxy );
450	#endif
451
452	}
453	else
454	{
455	assert( __FUNCTION__, false , "illegal device functionnal type\n" );
456	}
457	} // end soclib_pic_bind_irq();
458
459	///////////////////////////////////////
460	void soclib_pic_enable_irq( lid_t lid,
461	xptr_t src_chdev_xp )
462	{
463	// get cluster and local pointer on remote src_chdev
464	cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp );
465	chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
466
467	// get local pointer on remote XCU segment base
468	uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
469
470	// get the source chdev IRQ type and index
471	uint32_t irq_type = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
472	uint32_t irq_id = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
473
474	if( irq_type == SOCLIB_TYPE_HWI )
475	{
476	// enable this HWI in remote XCU controller
477	// in TSAR : XCU output [4*lid] is connected to core [lid]
478	hal_remote_s32( XPTR( src_chdev_cxy ,
479	&seg_xcu_ptr[ (XCU_MSK_HWI_ENABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
480	}
481	else if( irq_type == SOCLIB_TYPE_WTI )
482	{
483	// enable this WTI in remote XCU controller
484	// in TSAR : XCU output [4*lid] is connected to core [lid]
485	hal_remote_s32( XPTR( src_chdev_cxy ,
486	&seg_xcu_ptr[ (XCU_MSK_WTI_ENABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
487	}
488	else
489	{
490	assert( __FUNCTION__, false , "illegal IRQ type\n" );
491	}
492	} // end soclib_pic_enable_irq()
493
494	////////////////////////////////////////
495	void soclib_pic_disable_irq( lid_t lid,
496	xptr_t src_chdev_xp )
497	{
498	// get cluster and local pointer on remote src_chdev
499	cxy_t src_chdev_cxy = GET_CXY( src_chdev_xp );
500	chdev_t * src_chdev_ptr = (chdev_t *)GET_PTR( src_chdev_xp );
501
502	// get local pointer on remote XCU segment base
503	uint32_t * seg_xcu_ptr = soclib_pic_remote_xcu_base( src_chdev_cxy );
504
505	// get the source chdev IRQ type and index
506	uint32_t irq_type = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_type ) );
507	uint32_t irq_id = hal_remote_l32( XPTR( src_chdev_cxy , &src_chdev_ptr->irq_id ) );
508
509	if( irq_type == SOCLIB_TYPE_HWI )
510	{
511	// enable this HWI in remote XCU controller
512	// in TSAR : XCU output [4*lid] is connected to core [lid]
513	hal_remote_s32( XPTR( src_chdev_cxy ,
514	&seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
515	}
516	else if( irq_type == SOCLIB_TYPE_WTI )
517	{
518	// enable this WTI in remote XCU controller
519	// in TSAR : XCU output [4*lid] is connected to core [lid]
520	hal_remote_s32( XPTR( src_chdev_cxy ,
521	&seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) \| (lid<<2) ] ) , (1 << irq_id) );
522	}
523	else
524	{
525	assert( __FUNCTION__, false , "illegal IRQ type\n" );
526	}
527	} // end soclib_pic_enable_irq()
528
529	///////////////////////////////////////////////
530	void soclib_pic_enable_timer( uint32_t period )
531	{
532	// calling core local index
533	lid_t lid = CURRENT_THREAD->core->lid;
534
535	// get XCU segment base
536	uint32_t * base = soclib_pic_xcu_base();
537
538	// set period value in XCU (in cycles)
539	uint32_t cycles = period * SOCLIB_CYCLES_PER_MS;
540	base[(XCU_PTI_PER << 5) \| lid] = cycles;
541
542	// enable PTI in local XCU controller
543	// In TSAR : XCU output [4*lid] is connected to core [lid]
544	base[ (XCU_MSK_PTI_ENABLE << 5) \| (lid<<2) ] = 1 << lid;
545	}
546
547	////////////////////////////
548	void soclib_pic_enable_ipi( void )
549	{
550	// calling core local index
551	lid_t lid = CURRENT_THREAD->core->lid;
552
553	// get XCU segment base
554	uint32_t * base = soclib_pic_xcu_base();
555
556	// enable WTI in local XCU controller
557	// In TSAR : XCU output [4*lid] is connected to core [lid]
558	base[ (XCU_MSK_WTI_ENABLE << 5) \| (lid<<2) ] = 1 << lid;
559	}
560
561	///////////////////////////////////////
562	void soclib_pic_send_ipi( cxy_t cxy,
563	lid_t lid )
564	{
565	// get pointer on local XCU segment base
566	uint32_t * base = soclib_pic_xcu_base();
567
568	// write to WTI mailbox[cxy][lid]
569	hal_remote_s32( XPTR( cxy , &base[(XCU_WTI_REG << 5) \| lid ] ) , 0 );
570	}
571
572	/////////////////////////
573	void soclib_pic_ack_ipi( void )
574	{
575	// get calling core local index
576	lid_t lid = CURRENT_THREAD->core->lid;
577
578	// get pointer on local XCU segment base
579	uint32_t * base = soclib_pic_xcu_base();
580
581	// acknowlege IPI
582	uint32_t ack = base[ (XCU_WTI_REG << 5) \| lid ];
583
584	// we must make a fake use for ack value to avoid a warning
585	if( (ack + 1) == 0 ) asm volatile( "nop" );
586	}
587
588

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