[1] | 1 | /* |
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| 2 | * hal_do_exception.c - implementation of exception handler for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Authors Ghassan Almaless (2008,2009,2010,2011,2012) |
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| 5 | * Alain Greiner (2016) |
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| 6 | * |
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| 7 | * Copyright (c) UPMC Sorbonne Universites |
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| 8 | * |
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| 9 | * This file is part of ALMOS-MKH. |
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| 10 | * |
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| 11 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU General Public License as published by |
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| 13 | * the Free Software Foundation; version 2.0 of the License. |
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| 14 | * |
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| 15 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU General Public License |
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| 21 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 22 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 23 | */ |
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| 24 | |
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| 25 | #include <types.h> |
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| 26 | #include <task.h> |
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| 27 | #include <thread.h> |
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| 28 | #include <kdmsg.h> |
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| 29 | #include <pmm.h> |
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| 30 | #include <vmm.h> |
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| 31 | #include <errno.h> |
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| 32 | #include <scheduler.h> |
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| 33 | #include <cpu.h> |
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| 34 | #include <spinlock.h> |
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| 35 | #include <distlock.h> |
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| 36 | #include <cpu-trace.h> |
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| 37 | #include <cpu-regs.h> |
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| 38 | |
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| 39 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 40 | // This enum defines the relevant values for the XCODE field from CP0_CR register. |
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| 41 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 42 | |
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| 43 | typedef enum |
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| 44 | { |
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| 45 | XCODE_ADEL = 4, // Illegal address for data load |
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| 46 | XCODE_ADES = 5, // Illegal address for data store |
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| 47 | XCODE_IBE = 6, // Instruction MMU exception |
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| 48 | XCODE_DBE = 7, // Data MMU exception |
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| 49 | XCODE_RI = 10, // Reserved instruction exception |
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| 50 | XCODE_FPU = 11, // FPU coprocessor exception |
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| 51 | XCODE_OVR = 12 // Arithmetic Overflow exception |
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| 52 | } |
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| 53 | xcode_values_t; |
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| 54 | |
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| 55 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 56 | // This defines the masks used to analyse the TSAR MMU exception code |
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| 57 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 58 | |
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| 59 | #define TSAR_MMU_PAGE_UNMAPPED 0x0003 // page fault (PTE unmapped) |
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| 60 | #define TSAR_MMU_USER_PRIVILEGE 0x0004 // user access to a kernel segment |
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| 61 | #define TSAR_MMU_USER_WRITE 0x0008 // user access to non writable segment |
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| 62 | #define TSAR_MMU_USER_EXEC 0x0010 // user access to non executable segment |
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| 63 | #define TSAR_MMU_KERNEL_XTN 0x0020 // kernel illegal external access |
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| 64 | #define TSAR_MMU_KERNEL_PT1 0x0040 // kernel illegal PT1 access |
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| 65 | #define TSAR_MMU_KERNEL_PT2 0x0080 // kernel illegal PT2 access |
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| 66 | #define TSAR_MMU_KERNEL_DATA 0x0100 // kernel illegal data access |
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| 67 | |
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| 68 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 69 | // This defines the masks used to get the TSAR MMU PTE attributes |
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| 70 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 71 | |
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| 72 | #define TSAR_MMU_PTE_V 0x80000000 // Valid |
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| 73 | #define TSAR_MMU_PTE_T 0x40000000 // Small Page |
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| 74 | #define TSAR_MMU_PTE_C 0x08000000 // Cachable |
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| 75 | #define TSAR_MMU_PTE_W 0x04000000 // Writable |
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| 76 | #define TSAR_MMU_PTE_X 0x02000000 // eXecutable |
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| 77 | #define TSAR_MMU_PTE_U 0x01000000 // User accessible |
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| 78 | |
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| 79 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 80 | // This enum defines the various types of error code returned to the hal_do_exception() |
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| 81 | // function by the mmu_exception_handler() and fpu_exception_handler(). |
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| 82 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 83 | |
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| 84 | typedef enum |
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| 85 | { |
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| 86 | EXCP_SOLVED = 0, // No error => the unmapped PTE has been mapped |
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| 87 | EXCP_USER_ERROR = 1, // User error => user process will receive a SIGSEGV |
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| 88 | EXCP_KERNEL_PANIC = 2, // Kernel error => kernel panic |
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| 89 | } |
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| 90 | mmu_excp_t; |
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| 91 | |
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| 92 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 93 | // This remote_spinlock is a global variable defined in all clusters, |
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| 94 | // but only the spinlock implemented in the boot cluster is used. |
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| 95 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 96 | |
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| 97 | remote_spinlock_t exception_lock; |
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| 98 | |
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| 99 | |
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| 100 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 101 | // This function is called by the hal_do_exception() function when a "FPU unusable" |
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| 102 | // exception has been detected by the calling thread. |
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| 103 | // This function check in CP0_CR register that the unavailable CPU is actually CP1, |
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| 104 | // it saves the FPU context in the owner thread descriptor, and restore the FPU context |
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| 105 | // from the calling thread descriptor. |
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| 106 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 107 | static error_t fpu_exception_handler( reg_t * regs_tbl ) |
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| 108 | { |
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| 109 | thread_t * this = CURRENT_THREAD; // calling thread |
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| 110 | core_t * core = this->core; // associated core |
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| 111 | |
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| 112 | // check coprocessor index |
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| 113 | if( ((regs_tbl[CR] >> 28) & 0x3) != 1 ) |
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| 114 | { |
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| 115 | printk(WARNING, "%s for thread %x : bad coprocessor indexn", |
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| 116 | __FUNCTION__ , this->trdid ); |
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| 117 | return EXCP_KERNEL_PANIC; |
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| 118 | } |
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| 119 | |
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| 120 | hal_fpu_enable(); |
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| 121 | |
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| 122 | if( (core->fpu_owner != NULL) && (core->fpu_owner != this) ) |
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| 123 | { |
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| 124 | hal_fpu_context_save ( &core->fpu_owner->uzone ); |
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| 125 | } |
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| 126 | |
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| 127 | hal_fpu_context_restore( &this->uzone ); |
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| 128 | cpu->fpu_owner = this; |
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| 129 | |
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| 130 | return EXCP_SOLVED; |
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| 131 | } |
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| 132 | |
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| 133 | |
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| 134 | /////////////////////////////////////////////////////////////////////////////////// |
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| 135 | // This function is called by the hal_do_exception() function when a TSAR-MMU |
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| 136 | // exception has been detected. There is three possible actions : |
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| 137 | // 1) simple page fault => page table is updated and thread resume. |
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| 138 | // 2) user error => user process is killed. |
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| 139 | // 3) kernel error => system crash. |
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| 140 | /////////////////////////////////////////////////////////////////////////////////// |
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| 141 | // @ excp_code : generic exception code returned by TSAR-MMU |
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| 142 | // @ bad_vaddr : faulty virtual address |
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| 143 | // @ return EXCP_RESOLVED / MMU_EXCP_USER_ERROR / MMU_EXCP_KERNEL_PANIC |
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| 144 | /////////////////////////////////////////////////////////////////////////////////// |
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| 145 | static error_t mmu_exception_handler( uint32_t excp_code, |
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| 146 | uint32_t bad_vaddr ) |
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| 147 | { |
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| 148 | thread_t * this; // calling thread pointer |
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| 149 | vseg_t * vseg; // vseg containing the bad_vaddr |
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| 150 | process_t * process; // local process descriptor |
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| 151 | vmm_t * vmm; // VMM for calling thread |
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| 152 | vpn_t vpn; // VPN for bad_vaddr |
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| 153 | uint32_t flags; // vseg flags |
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| 154 | error_t error; // return value |
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| 155 | |
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| 156 | this = CURRENT_THREAD; |
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| 157 | process = this->process; |
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| 158 | vmm = &process->vmm; |
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| 159 | vpn = bad_vaddr>>CONFIG_PPM_PAGE_SHIFT; |
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| 160 | |
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| 161 | vmm_dmsg(2, "%s enters for thread %x in process %x / bad_vaddr = %x / excep_code = %x\n", |
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| 162 | __FUNCTION__, this->trdid , process->pid , bad_vaddr , excep_code ); |
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| 163 | |
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| 164 | // a kernel thread should not rise an MMU exception |
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| 165 | if( this->type != T_USER ) |
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| 166 | { |
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| 167 | printk(WARNING, "%s for thread %x : it's a kernel thread / vaddr = %x\n", |
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| 168 | __FUNCTION__ , this->trdid , bad_vaddr ); |
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| 169 | return EXCP_KERNEL_PANIC; |
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| 170 | } |
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| 171 | |
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| 172 | // enable IRQs |
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| 173 | hal_enable_irq( NULL ); |
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| 174 | |
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| 175 | // update user_time |
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| 176 | tm_usr_compute( this ); |
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| 177 | |
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| 178 | // vaddr must be contained in a registered vseg |
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| 179 | vseg = vmm_get_vseg( process , bad_vaddr ); |
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| 180 | |
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| 181 | if( vseg == NULL ) // vseg not found |
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| 182 | { |
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| 183 | if( cxy != cxy_ref ) // try to get vseg from reference VMM |
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| 184 | { |
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| 185 | rpc_vmm_get_ref_vseg_client( cxy_ref , process_ref , bad_vaddr , &vseg ); |
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| 186 | } |
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| 187 | |
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| 188 | if( vseg == NULL ) // illegal user vaddr => return user error |
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| 189 | { |
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| 190 | printk(WARNING, "%s for thread %x : no vseg for vaddr = %x\n", |
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| 191 | __FUNCTION__ , this->trdid , bad_vaddr ); |
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| 192 | hal_disable_irq( NULL ); |
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| 193 | return EXCP_USER_ERROR; |
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| 194 | } |
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| 195 | else // legal vaddr => get vseg flags |
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| 196 | { |
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| 197 | flags = vseg->flags; |
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| 198 | } |
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| 199 | } |
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| 200 | |
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| 201 | vmm_dmsg(2, "%s found vseg for thread %x / vseg_base = %x / vseg_flags = %x\n", |
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| 202 | __FUNCTION__ , this->trdid , vseg->begin , vseg->flags ); |
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| 203 | |
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| 204 | // analyse TSAR MMU exception code |
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| 205 | if( excp_code & TSAR_MMU_UNMAPPED ) |
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| 206 | { |
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| 207 | // try to map the unmapped PTE |
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| 208 | error = vmm_handle_page_fault( process , vseg , vpn ); |
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| 209 | if( error ) |
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| 210 | { |
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| 211 | printk(WARNING, "%s for thread %x : cannot allocate memory for new PTE\n", |
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| 212 | __FUNCTION__ , this->trdid , bad_vaddr ); |
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| 213 | hal_disable_irq( NULL ); |
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| 214 | return EXCP_KERNEL_PANIC; |
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| 215 | } |
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| 216 | else |
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| 217 | { |
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| 218 | vmm_dmsg(2, "%s page fault succesfully handled for vaddr = %x in thread %x\n", |
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| 219 | __FUNCTION__ , bad_vaddr , this->trdid ); |
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| 220 | |
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| 221 | // page fault successfully handled |
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| 222 | hal_disable_irq( NULL ); |
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| 223 | |
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| 224 | hal_yield(); // TODO Pourquoi ce yield ? |
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| 225 | |
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| 226 | // update kernel_time |
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| 227 | tm_sys_compute(this); |
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| 228 | |
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| 229 | return EXCP_SOLVED; |
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| 230 | } |
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| 231 | } |
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| 232 | else if( excp_code & TSAR_MMU_USER_PRIVILEGE ) |
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| 233 | { |
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| 234 | printk(WARNING,"%s for thread %x : user access to kernel vseg at vaddr = %x\n", |
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| 235 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 236 | return EXCP_USER_ERROR; |
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| 237 | } |
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| 238 | else if( excp_code & TSAR_MMU_USER_EXEC ) |
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| 239 | { |
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| 240 | printk(WARNING,"%s for thread %x : access to non-exec vseg at vaddr = %x\n" |
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| 241 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 242 | return EXCP_USER_ERROR; |
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| 243 | } |
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| 244 | else if( excp_code & TSAR_MMU_USER_WRITE ) |
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| 245 | { |
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| 246 | printk(WARNING,"%s for thread %x : write to non-writable vseg at vaddr = %x\n" |
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| 247 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 248 | return EXCP_USER_ERROR; |
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| 249 | } |
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| 250 | else if( excp_code & TSAR_MMU_KERNEL_XTN ) |
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| 251 | { |
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| 252 | printk(WARNING,"%s for thread %x : kernel illegal access to external address = %x\n" |
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| 253 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 254 | return EXCP_KERNEL_PANIC; |
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| 255 | } |
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| 256 | else if( excp_code & TSAR_MMU_KERNEL_PT1 ) |
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| 257 | { |
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| 258 | printk(WARNING,"%s for thread %x : kernel bus error accessing PT1 / vaddr = %x\n" |
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| 259 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 260 | return EXCP_KERNEL_PANIC; |
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| 261 | } |
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| 262 | else if( excp_code & TSAR_MMU_KERNEL_PT2 ) |
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| 263 | { |
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| 264 | printk(WARNING,"%s for thread %x : kernel bus error accessing PT2 / vaddr = %x\n" |
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| 265 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 266 | return EXCP_KERNEL_PANIC; |
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| 267 | } |
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| 268 | else if( excp_code & TSAR_MMU_KERNEL_DATA ) |
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| 269 | { |
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| 270 | printk(WARNING,"%s for thread %x : kernel bus error accessing DATA / vaddr = %x\n" |
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| 271 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 272 | return EXCP_KERNEL_PANIC; |
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| 273 | } |
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| 274 | else |
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| 275 | { |
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| 276 | printk(WARNING,"%s for thread %x : undefined MMUexception code ??? / vaddr = %x\n" |
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| 277 | __FUNCTION__ , thread->trdid , bad_vaddr ); |
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| 278 | return EXCP_KERNEL_PANIC; |
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| 279 | } |
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| 280 | |
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| 281 | } // end mmu_exception_handler() |
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| 282 | |
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| 283 | |
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| 284 | /////////////////////////////////////// |
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| 285 | void hal_do_exception( thread_t * this, |
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| 286 | gid_t gid, |
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| 287 | reg_t * regs_tbl ) |
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| 288 | { |
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| 289 | error_t error; |
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| 290 | uint32_t excCode; // XCODE from CP0_CR |
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| 291 | uint32_t mmu_iexcp_code; // MMU IEXCP_CODE from CP2 |
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| 292 | uint32_t mmu_ibad_vaddr; // MMU IBAD_VADDR from CP2 |
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| 293 | uint32_t mmu_dexcp_code; // MMU DEXCP_CODE from CP2 |
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| 294 | uint32_t mmu_dbad_vaddr; // MMU BDAD_VADDR from CP2 |
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| 295 | bool_t isInKernelMode; |
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| 296 | mmu_except_info_t * entry; |
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| 297 | hal_except_info_t * execErr; |
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| 298 | |
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| 299 | // get XCODE from CP0_CR register |
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| 300 | excCode = (regs_tbl[CR] >> 2) & 0x1F; |
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| 301 | |
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| 302 | // get relevant values from CP2 registers |
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| 303 | mmu_iexcp_code = mips_get_cp2(MMU_IETR, 0); |
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| 304 | mmu_ibad_vaddr = mips_get_cp2(MMU_IBVAR, 0); |
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| 305 | mmu_dexcp_code = mips_get_cp2(MMU_DETR, 0); |
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| 306 | mmu_dbad_vaddr = mips_get_cp2(MMU_DBVAR, 0); |
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| 307 | |
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| 308 | switch(excCode) |
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| 309 | { |
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| 310 | case XCODE_IBE: |
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| 311 | error = mmu_exception_handler( mmu_iexcp_code , mmu_ibad_vaddr ); |
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| 312 | break; |
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| 313 | case XCODE_DBE: |
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| 314 | error = mmu_exception_handler( mmu_dexcp_code , mmu_dbad_vaddr ); |
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| 315 | break; |
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| 316 | case XCODE_CPU: |
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| 317 | error = fpu_exception_handler( regs_tbl ); |
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| 318 | break; |
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| 319 | default: |
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| 320 | error = EXCP_KERNEL_PANIC; |
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| 321 | break; |
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| 322 | } |
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| 323 | |
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| 324 | // analyse error code |
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| 325 | if( error == EXCP_SOLVED ) // page fault successfully handled => just return |
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| 326 | { |
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| 327 | return; |
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| 328 | } |
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| 329 | |
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| 330 | else if( error == EXCP_USER_ERROR ) // user error => kill the user process and return |
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| 331 | { |
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| 332 | // TODO [AG] |
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| 333 | // uspace_start = (uint32_t) &__uspace_start; |
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| 334 | // uspace_end = (uint32_t) &__uspace_end; |
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| 335 | // |
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| 336 | // if((regs_tbl[EPC] >= uspace_start) && (regs_tbl[EPC] <= uspace_end)) |
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| 337 | // { |
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| 338 | // regs_tbl[EPC] = (reg_t) &hal_uspace_error; |
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| 339 | // regs_tbl[MMU_MD] = (reg_t) 0x3;//MMU_MODE OFF |
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| 340 | // return; |
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| 341 | // } |
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| 342 | } |
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| 343 | else // kernel error => kernel panic |
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| 344 | { |
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| 345 | // take the exception_lock located in boot_cluster |
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| 346 | cxy_t boot_cxy = LOCAL_CLUSTER->boot_cxy; |
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| 347 | remote_spinlock_lock( XPTR( boot_cxy , &exception_lock ) ); |
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| 348 | |
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| 349 | thread_t * this = CURRENT_THREAD; |
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| 350 | process_t * process = this->process; |
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| 351 | |
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| 352 | // dump registers values |
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| 353 | |
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| 354 | except_dmsg("====================================================================\n"); |
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| 355 | except_dmsg("Kernel Panic: thread %x in process %x on core %x at cycle %d\n", |
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| 356 | this->trdid , process->pid , gid , hal_time_stamp() ); |
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| 357 | |
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| 358 | except_dmsg("Processor State:\n"); |
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| 359 | |
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| 360 | except_dmsg("CR: %x\tEPC: %x\tSR: %x\tSP: %x\tUSR SP %x\n", |
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| 361 | regs_tbl[CR],regs_tbl[EPC],regs_tbl[SR],regs_tbl[SP],this->uzone.regs[SP]); |
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| 362 | |
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| 363 | except_dmsg("at_1 %x\tv0_2 %x\t\tv1_3 %x\ta0_4 %x\ta1_5 %x\n", |
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| 364 | regs_tbl[AT],regs_tbl[V0],regs_tbl[V1],regs_tbl[A0],regs_tbl[A1]); |
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| 365 | |
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| 366 | except_dmsg("a2_6 %x\t\ta3_7 %x\tt0_8 %x\tt1_9 %x\tt2_10 %x\n", |
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| 367 | regs_tbl[A2],regs_tbl[A3],regs_tbl[T0],regs_tbl[T1],regs_tbl[T2]); |
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| 368 | |
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| 369 | except_dmsg("t3_11 %x\tt4_12 %x\t\tt5_13 %x\tt6_14 %x\tt7_15 %x\n", |
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| 370 | regs_tbl[T3],regs_tbl[T4],regs_tbl[T5],regs_tbl[T6],regs_tbl[T7]); |
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| 371 | |
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| 372 | except_dmsg("t8_24 %x\t\tt9_25 %x\tgp_28 %x\tc0_hi %x\tc0_lo %x\n", |
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| 373 | regs_tbl[T8],regs_tbl[T9],regs_tbl[GP],regs_tbl[HI],regs_tbl[LO]); |
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| 374 | |
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| 375 | except_dmsg("s0_16 %x\ts1_17 %x\ts2_18 %x\ts3_19 %x\ts4_20 %x\n", |
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| 376 | regs_tbl[S0],regs_tbl[S1],regs_tbl[S2],regs_tbl[S3],regs_tbl[S4]); |
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| 377 | |
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| 378 | except_dmsg("s5_21 %x\ts6_22 %x\t\ts7_23 %x\ts8_30 %x\tra_31 %x\n\n", |
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| 379 | regs_tbl[S5],regs_tbl[S6],regs_tbl[S7],regs_tbl[S8],regs_tbl[RA]); |
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| 380 | |
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| 381 | except_dmsg("Thread State %x\n" |
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| 382 | "\tsys_stack_top = %x\n" |
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| 383 | "tusr_stack = %x\n" |
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| 384 | "\tutls = %x\n" |
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| 385 | "\tstate = %s\n" |
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| 386 | "\tlocks = %d\n", |
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| 387 | this->trdid, |
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| 388 | this->uzone.regs[KSP], |
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| 389 | this->uzone.regs[SP], |
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| 390 | this->uzone.regs[TLS_K1], |
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| 391 | thread_get_state_name( this->state ), |
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| 392 | this->locks_count); |
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| 393 | |
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| 394 | isInKernelMode = (regs_tbl[SR] & 0x10) ? false : true; |
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| 395 | |
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| 396 | except_dmsg("\nIs in kernel: %s\n", (isInKernelMode) ? "YES" : "NO"); |
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| 397 | |
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| 398 | if(isInKernelMode) |
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| 399 | { |
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| 400 | execErr = hal_except_get_entry(excCode); |
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| 401 | if(regs_tbl[EPC] >= __ktext_start && regs_tbl[EPC] <= __ktext_end) |
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| 402 | instContent = *((uint32_t*) regs_tbl[EPC]); |
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| 403 | else |
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| 404 | instContent = 0; |
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| 405 | |
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| 406 | except_dmsg("Pid %d, Cpu %d, Inst. %x, Exception : code %d, name %s, description %s, bad address %x\n", |
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| 407 | this->task->pid, |
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| 408 | gid, |
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| 409 | instContent, |
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| 410 | excCode, |
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| 411 | execErr->name, |
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| 412 | execErr->desc, |
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| 413 | hal_get_bad_vaddr() |
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| 414 | ); |
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| 415 | |
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| 416 | } |
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| 417 | |
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| 418 | |
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| 419 | except_dmsg("====================================================================\n"); |
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| 420 | |
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| 421 | // release exception lock |
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| 422 | remote_spinlock_unlock( XPTR( boot_cxy , &exception_lock ) ); |
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| 423 | |
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| 424 | sched_exit(this); // TODO ??? [AG] |
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| 425 | while(entry != NULL); |
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| 426 | } |
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