[1] | 1 | /* |
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| 2 | * hal_special.c - implementation of Generic Special Register Access API for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Author Ghassan Almaless (2008,2009,2010,2011,2012) |
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| 5 | * Alain Greiner (2016) |
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| 6 | * |
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| 7 | * Copyright (c) UPMC Sorbonne Universites |
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| 8 | * |
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| 9 | * This file is part of ALMOS-MKH.. |
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| 10 | * |
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| 11 | * ALMOS-MKH. is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU General Public License as published by |
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| 13 | * the Free Software Foundation; version 2.0 of the License. |
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| 14 | * |
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| 15 | * ALMOS-MKH. is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU General Public License |
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| 21 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 22 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 23 | */ |
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| 24 | |
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| 25 | |
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| 26 | #include <hal_types.h> |
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| 27 | #include <hal_special.h> |
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| 28 | |
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| 29 | /**** Forward declarations ****/ |
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| 30 | |
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| 31 | struct thread_s; |
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| 32 | |
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| 33 | /////////////////// |
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| 34 | gid_t hal_get_gid() |
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| 35 | { |
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| 36 | uint32_t proc_id; |
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| 37 | |
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| 38 | asm volatile ("mfc0 %0, $15, 1" : "=&r" (proc_id)); |
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| 39 | |
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[16] | 40 | return (proc_id & 0x3FF); // 4/4/2 format for TSAR |
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[1] | 41 | } |
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| 42 | |
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| 43 | ///////////////////////// |
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| 44 | uint32_t hal_time_stamp() |
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| 45 | { |
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| 46 | uint32_t cycles; |
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| 47 | |
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| 48 | asm volatile ("mfc0 %0, $9 " : "=&r" (cycles)); |
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| 49 | |
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| 50 | return cycles; |
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| 51 | } |
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| 52 | |
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| 53 | ////////////////////////////////////////// |
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| 54 | struct thread_s * hal_get_current_thread() |
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| 55 | { |
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| 56 | void * thread_ptr; |
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| 57 | |
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| 58 | asm volatile |
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| 59 | ( "mfc0 %0, $4, 2 \n" |
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| 60 | : "=&r" (thread_ptr) ); |
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| 61 | |
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| 62 | return thread_ptr; |
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| 63 | } |
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| 64 | |
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| 65 | /////////////////////////////////////////////////////// |
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| 66 | void hal_set_current_thread( struct thread_s * thread ) |
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| 67 | { |
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| 68 | asm volatile |
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| 69 | ( "mtc0 %0, $4, 2 \n" |
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| 70 | : : "r" (thread) ); |
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| 71 | } |
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| 72 | |
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| 73 | ///////////////////// |
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| 74 | void hal_fpu_enable() |
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| 75 | { |
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| 76 | asm volatile |
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| 77 | ( ".set noat \n" |
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| 78 | "lui $27, 0x2000 \n" |
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| 79 | "mfc0 $1, $12 \n" |
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| 80 | "or $27, $1, $27 \n" |
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| 81 | "mtc0 $27, $12 \n" |
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| 82 | ".set at \n" ); |
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| 83 | } |
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| 84 | |
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| 85 | ////////////////////// |
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| 86 | void hal_fpu_disable() |
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| 87 | { |
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| 88 | asm volatile |
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| 89 | ( ".set noat \n" |
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| 90 | "lui $27, 0xDFFF \n" |
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| 91 | "ori $27, $27, 0xFFFF \n" |
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| 92 | "mfc0 $1, $12 \n" |
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| 93 | "and $27, $1, $27 \n" |
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| 94 | "mtc0 $27, $12 \n" |
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| 95 | ".set at \n"); |
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| 96 | } |
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| 97 | |
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| 98 | //////////////////////// |
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| 99 | uint32_t hal_get_stack() |
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| 100 | { |
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| 101 | register uint32_t sp; |
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| 102 | |
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| 103 | asm volatile |
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| 104 | ( "or %0, $0, $29 \n" |
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| 105 | : "=&r" (sp) ); |
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| 106 | |
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| 107 | return sp; |
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| 108 | } |
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| 109 | |
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| 110 | //////////////////////////////////////// |
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| 111 | uint32_t hal_set_stack( void * new_val ) |
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| 112 | { |
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| 113 | register uint32_t sp; |
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| 114 | |
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| 115 | asm volatile |
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| 116 | ( "or %0, $0, $29 \n" |
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| 117 | "or $29, $0, %1 \n" |
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| 118 | : "=&r" (sp) : "r" (new_val) ); |
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| 119 | |
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| 120 | return sp; |
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| 121 | } |
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| 122 | |
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| 123 | //////////////////////////// |
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| 124 | uint32_t hal_get_bad_vaddr() |
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| 125 | { |
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| 126 | register uint32_t bad_va; |
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| 127 | |
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| 128 | asm volatile |
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| 129 | ( "mfc0 %0, $8 \n" |
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| 130 | : "=&r" (bad_va) ); |
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| 131 | |
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| 132 | return bad_va; |
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| 133 | } |
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| 134 | |
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| 135 | //////////////////////////////////////////// |
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| 136 | uint32_t hal_uncached_read( uint32_t * ptr ) |
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| 137 | { |
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| 138 | register uint32_t val; |
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| 139 | |
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| 140 | asm volatile |
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| 141 | ( "ll %0, (%1) \n" |
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| 142 | : "=&r"(val) : "r" (ptr) ); |
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| 143 | |
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| 144 | return val; |
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| 145 | } |
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| 146 | |
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| 147 | ////////////////////////////////////////// |
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| 148 | void hal_invalid_dcache_line( void * ptr ) |
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| 149 | { |
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| 150 | asm volatile |
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| 151 | ( "cache %0, (%1) \n" |
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| 152 | "sync \n" |
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| 153 | : : "i" (0x11) , "r" (ptr) ); |
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| 154 | } |
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| 155 | |
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| 156 | ////////////////// |
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| 157 | void hal_wbflush() |
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| 158 | { |
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| 159 | asm volatile |
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| 160 | ( "sync \n":: ); |
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| 161 | } |
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| 162 | |
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| 163 | //////////////// |
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| 164 | void hal_rdbar() |
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| 165 | { |
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| 166 | asm volatile( "" ::: "memory" ); |
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| 167 | } |
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| 168 | |
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| 169 | ///////////////////// |
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| 170 | void hal_core_sleep() |
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| 171 | { |
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| 172 | asm volatile |
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| 173 | ("wait \n"::); |
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| 174 | } |
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| 175 | |
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| 176 | ////////////////////////////////////// |
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| 177 | void hal_fixed_delay( uint32_t delay ) |
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| 178 | { |
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| 179 | asm volatile |
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| 180 | ( "1: \n" |
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| 181 | "or $27, %0, $0 \n" |
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| 182 | "addi $27, $27, -1 \n" |
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| 183 | "bne $27, $0, 1b \n" |
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| 184 | "nop \n" |
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| 185 | : : "r" (delay) : "$27" ); |
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| 186 | } |
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| 187 | |
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[16] | 188 | ////////////////////////////////////////////////// |
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| 189 | void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code, |
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| 190 | intptr_t * mmu_ins_bad_vaddr, |
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| 191 | intptr_t * mmu_dat_excp_code, |
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| 192 | intptr_t * mmu_dat_bad_vaddr ) |
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| 193 | { |
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| 194 | asm volatile |
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| 195 | ( "mfc2 %0, $11 \n" |
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| 196 | "mfc2 %1, $13 \n" |
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| 197 | "mfc2 %2, $12 \n" |
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| 198 | "mfc2 %3, $14 \n" |
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| 199 | : "=&r"(mmu_ins_excp_code), |
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| 200 | "=&r"(mmu_ins_bad_vaddr), |
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| 201 | "=&r"(mmu_dat_excp_code), |
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| 202 | "=&r"(mmu_dat_bad_vaddr) ); |
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| 203 | } |
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