| [16] | 1 | /* |
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| 2 | * mips32_context.h - structures used to save MIPS32 CPU & FPU registers |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef _MIPS32_CONTEXT_H_ |
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| 25 | #define _MIPS32_CONTEXT_H_ |
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| 26 | |
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| 27 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 28 | // This file defines the MIPPS32specific structures, that are used to save /restore |
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| 29 | // MIPS32 CPU and FPU registers at context swich. |
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| 30 | ////////////////////////////////////////////////////////////////////////////////////////// |
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| 31 | |
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| 32 | /**************************************************************************************** |
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| 33 | * This defines the "mips32_cpu_context_t" structure, containing general registers, |
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| 34 | * as well as CP0 or CP2 registers. |
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| 35 | * These registers are saved/restored at each context switch. |
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| 36 | * It can be accessed through a void* pointer contained in the thread descriptor. |
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| 37 | * |
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| 38 | * WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore() |
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| 39 | * functions when modifying this structure. |
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| 40 | ***************************************************************************************/ |
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| 41 | |
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| 42 | typedef struct mips_32_cpu_context_s |
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| 43 | { |
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| 44 | uint32_t s0_16; // slot 0 |
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| 45 | uint32_t s1_17; // slot 1 |
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| 46 | uint32_t s2_18; // slot 2 |
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| 47 | uint32_t s3_19; // slot 3 |
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| 48 | uint32_t s4_20; // slot 4 |
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| 49 | uint32_t s5_21; // slot 5 |
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| 50 | uint32_t s6_22; // slot 6 |
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| 51 | uint32_t s7_23; // slot 7 |
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| 52 | uint32_t sp_29; // slot 8 |
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| 53 | uint32_t fp_30; // slot 9 |
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| 54 | uint32_t ra_31; // slot 10 |
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| 55 | uint32_t c0_sr; // slot 11 |
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| 56 | uint32_t c0_th; // slot 12 |
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| 57 | uint32_t c2_ptpr; // slot 13 |
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| 58 | uint32_t c2_mode; // slot 14 |
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| 59 | } |
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| 60 | mips32_cpu_context_t; |
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| 61 | |
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| 62 | /**************************************************************************************** |
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| 63 | * This defines the "mips32_fpu_context_t" structure, containing all FPU registers |
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| 64 | * (i.e. CP1 coprocessor registers). |
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| 65 | * These registers are saved/restored each time the FPU is allocated to a thread. |
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| 66 | * It can be accessed through a void* pointer contained in the thread descriptor. |
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| 67 | * |
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| 68 | * WARNING : update the hal_fpu_context_save() and hal_fpu_context_restore() |
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| 69 | * functions when modifying this structure. |
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| 70 | ***************************************************************************************/ |
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| 71 | |
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| 72 | typedef struct mips32_fpu_context_s |
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| 73 | { |
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| 74 | uint32_t fpu_regs[32]; |
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| 75 | } |
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| 76 | mips32_fpu_context_t; |
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| 77 | |
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| 78 | |
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| 79 | #endif /* _MIPS32_CONTEXT_H_ */ |
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