[45] | 1 | /* |
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[82] | 2 | * hal_apic.c - Advanced Programmable Interrupt Controller |
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[45] | 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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| 22 | #include <hal_types.h> |
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[83] | 23 | #include <hal_boot.h> |
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[82] | 24 | #include <hal_register.h> |
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[45] | 25 | #include <hal_segmentation.h> |
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[82] | 26 | #include <hal_apic.h> |
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[45] | 27 | #include <hal_internal.h> |
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| 28 | |
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| 29 | #include <memcpy.h> |
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| 30 | #include <thread.h> |
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| 31 | #include <string.h> |
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| 32 | #include <process.h> |
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| 33 | #include <printk.h> |
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| 34 | #include <vmm.h> |
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| 35 | #include <core.h> |
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| 36 | #include <cluster.h> |
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| 37 | |
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[82] | 38 | /* -------------------------------------------------------------------------- */ |
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| 39 | |
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| 40 | #define PIC1_CMD 0x0020 |
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| 41 | #define PIC1_DATA 0x0021 |
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| 42 | #define PIC2_CMD 0x00a0 |
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| 43 | #define PIC2_DATA 0x00a1 |
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| 44 | |
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| 45 | static void hal_pic_init() |
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| 46 | { |
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| 47 | /* |
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| 48 | * Disable the PIC (8259A). We are going to use IOAPIC instead. |
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| 49 | */ |
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| 50 | out8(PIC1_DATA, 0xff); |
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| 51 | out8(PIC2_DATA, 0xff); |
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| 52 | } |
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| 53 | |
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| 54 | /* -------------------------------------------------------------------------- */ |
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| 55 | |
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[89] | 56 | paddr_t ioapic_pa __in_kdata = 0; |
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| 57 | vaddr_t ioapic_va __in_kdata = 0; |
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| 58 | |
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| 59 | #define IRQ_TIMER 0x00 |
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| 60 | #define IRQ_KEYBOARD 0x01 |
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| 61 | #define IRQ_COM2 0x03 |
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| 62 | #define IRQ_COM1 0x04 |
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| 63 | #define IRQ_FLOPPY 0x06 |
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| 64 | #define IRQ_ATA0 0x0e |
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| 65 | #define IRQ_ATA1 0x0f |
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| 66 | |
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| 67 | #define IOREGSEL 0x00 |
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| 68 | #define IOWIN 0x10 |
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| 69 | |
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| 70 | #define IOAPICID 0x00 |
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| 71 | #define IOAPICVER 0x01 |
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| 72 | #define IOAPICARB 0x02 |
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| 73 | #define IOREDTBL 0x10 |
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| 74 | |
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| 75 | #define IOENTRY_DISABLE 0x10000 |
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| 76 | |
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| 77 | void hal_ioapic_write(uint8_t reg, uint32_t val) |
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| 78 | { |
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| 79 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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| 80 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val; |
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| 81 | } |
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| 82 | |
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| 83 | uint32_t hal_ioapic_read(uint8_t reg) |
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| 84 | { |
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| 85 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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| 86 | return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)); |
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| 87 | } |
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| 88 | |
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| 89 | void hal_ioapic_set_entry(uint8_t index, uint64_t data) |
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| 90 | { |
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| 91 | hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF)); |
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| 92 | hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32)); |
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| 93 | } |
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| 94 | |
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| 95 | static void hal_ioapic_init() |
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| 96 | { |
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| 97 | size_t i, pins; |
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| 98 | uint32_t ver; |
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| 99 | |
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| 100 | ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 101 | |
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| 102 | hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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| 103 | |
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| 104 | ver = hal_ioapic_read(IOAPICVER); |
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| 105 | pins = ((ver >> 16) & 0xFF) + 1; |
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| 106 | |
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| 107 | /* Explicitly disable (mask) each vector */ |
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| 108 | for (i = 0; i < pins; i++) { |
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| 109 | hal_ioapic_set_entry(i, IOENTRY_DISABLE); |
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| 110 | } |
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| 111 | |
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| 112 | /* Now, enable the keyboard */ |
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| 113 | hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR); |
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| 114 | } |
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| 115 | |
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| 116 | /* -------------------------------------------------------------------------- */ |
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| 117 | |
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[45] | 118 | paddr_t lapic_pa __in_kdata = 0; |
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| 119 | vaddr_t lapic_va __in_kdata = 0; |
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| 120 | |
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[46] | 121 | void hal_lapic_write(uint32_t reg, uint32_t val) |
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[45] | 122 | { |
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[82] | 123 | *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val; |
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[45] | 124 | } |
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| 125 | |
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[46] | 126 | uint32_t hal_lapic_read(uint32_t reg) |
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[45] | 127 | { |
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[82] | 128 | return *((volatile uint32_t *)((uint8_t *)lapic_va + reg)); |
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[45] | 129 | } |
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| 130 | |
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[46] | 131 | uint32_t hal_lapic_gid() |
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[45] | 132 | { |
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[46] | 133 | return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT; |
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| 134 | } |
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[45] | 135 | |
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[82] | 136 | /* |
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| 137 | * We have 8 interrupt sources: |
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| 138 | * - Spurious |
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| 139 | * - APIC Timer (TMR) |
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| 140 | * - Local Interrupt 0 (LINT0) |
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| 141 | * - Local Interrupt 1 (LINT1) |
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| 142 | * - Performance Monitor Counters (PMC) |
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| 143 | * - Thermal Sensors (THM) |
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| 144 | * - APIC internal error (ERR) |
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| 145 | * - Extended (Implementation dependent) |
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| 146 | */ |
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| 147 | static void hal_lapic_init() |
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[46] | 148 | { |
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[45] | 149 | lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 150 | |
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[82] | 151 | if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) { |
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| 152 | x86_panic("APICBASE and ACPI don't match!\n"); |
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| 153 | } |
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| 154 | wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN); |
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| 155 | |
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[83] | 156 | hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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[45] | 157 | |
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[46] | 158 | hal_lapic_write(LAPIC_TPR, 0); |
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[82] | 159 | hal_lapic_write(LAPIC_EOI, 0); |
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[46] | 160 | hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|LAPIC_SPURIOUS_VECTOR); |
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[82] | 161 | |
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| 162 | /* Explicitly disable (mask) each vector */ |
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| 163 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M); |
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| 164 | hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M); |
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| 165 | hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M); |
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| 166 | hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M); |
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| 167 | hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M); |
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| 168 | hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M); |
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[86] | 169 | |
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| 170 | /* Now, enable the timer in repeated mode. */ |
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| 171 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M); |
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| 172 | hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1); |
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| 173 | hal_lapic_write(LAPIC_ICR_TIMER, 1000000000); // XXX calibrate |
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| 174 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR); |
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[45] | 175 | } |
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| 176 | |
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[82] | 177 | /* -------------------------------------------------------------------------- */ |
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| 178 | |
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| 179 | void hal_apic_init() |
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| 180 | { |
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| 181 | /* Disable the PIC */ |
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| 182 | hal_pic_init(); |
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| 183 | |
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| 184 | /* Enable the LAPIC */ |
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| 185 | hal_lapic_init(); |
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[89] | 186 | |
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| 187 | /* Enable the IOAPIC */ |
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| 188 | hal_ioapic_init(); |
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[82] | 189 | } |
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| 190 | |
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