source: trunk/hal/x86_64/core/hal_apic.c @ 202

Last change on this file since 202 was 202, checked in by max@…, 8 years ago

register the ATA IRQs
File size: 10.7 KB
Line 
1/*
2 * hal_apic.c - Advanced Programmable Interrupt Controller
3 *
4 * Copyright (c) 2017 Maxime Villard
5 *
6 * This file is part of ALMOS-MKH.
7 *
8 * ALMOS-MKH is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2.0 of the License.
11 *
12 * ALMOS-MKH is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <hal_types.h>
23#include <hal_boot.h>
24#include <hal_register.h>
25#include <hal_segmentation.h>
26#include <hal_apic.h>
27#include <hal_internal.h>
28
29#include <memcpy.h>
30#include <thread.h>
31#include <string.h>
32#include <process.h>
33#include <printk.h>
34#include <vmm.h>
35#include <core.h>
36#include <cluster.h>
37
38/* -------------------------------------------------------------------------- */
39
40#define PIC1_CMD        0x0020
41#define PIC1_DATA       0x0021
42#define PIC2_CMD        0x00a0
43#define PIC2_DATA       0x00a1
44
45static void hal_pic_init()
46{
47        /*
48         * Disable the PIC (8259A). We are going to use IOAPIC instead.
49         */
50        out8(PIC1_DATA, 0xff);
51        out8(PIC2_DATA, 0xff);
52}
53
54/* -------------------------------------------------------------------------- */
55
56uint64_t pit_ticks_base __in_kdata = 0;
57
58#define PIT_FREQUENCY   1193182
59#define HZ              100 /* 1/HZ = 10ms */
60
61#define PIT_TIMER0      0x40
62
63#define PIT_CMD         0x43
64#       define CMD_BINARY       0x00 /* Use Binary counter values */
65#       define CMD_BCD          0x01 /* Use Binary Coded Decimal counter values */
66#       define CMD_MODE0        0x00 /* Interrupt on Terminal Count */
67#       define CMD_MODE1        0x02 /* Hardware Retriggerable One-Shot */
68#       define CMD_MODE2        0x04 /* Rate Generator */
69#       define CMD_MODE3        0x06 /* Square Wave */
70#       define CMD_MODE4        0x08 /* Software Trigerred Strobe */
71#       define CMD_MODE5        0x0a /* Hardware Trigerred Strobe */
72#       define CMD_LATCH        0x00 /* latch counter for reading */
73#       define CMD_LSB          0x10 /* LSB, 8 bits */
74#       define CMD_MSB          0x20 /* MSB, 8 bits */
75#       define CMD_16BIT        0x30 /* LSB and MSB, 16 bits */
76#       define CMD_COUNTER0     0x00
77#       define CMD_COUNTER1     0x40
78#       define CMD_COUNTER2     0x80
79#       define CMD_READBACK     0xc0
80
81void hal_pit_init()
82{
83        /* Initialize PIT clock 0 to the maximum counter value, 65535. */
84        out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT);
85        out8(PIT_TIMER0, 0xFF);
86        out8(PIT_TIMER0, 0xFF);
87}
88
89uint64_t
90hal_pit_timer_read()
91{
92        static uint16_t last;
93
94        uint8_t lo, hi;
95        uint16_t ctr;
96        uint64_t ticks;
97
98        /* Read the current timer counter. */
99        out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH);
100        lo = in8(PIT_TIMER0);
101        hi = in8(PIT_TIMER0);
102        ctr = (hi << 8) | lo;
103
104        /* If the counter has wrapped, assume we're into the next tick. */
105        if (ctr > last)
106                pit_ticks_base += 0xFFFF;
107        last = ctr;
108
109        ticks = pit_ticks_base + (0xFFFF - ctr);
110
111        return ticks;
112}
113
114/* -------------------------------------------------------------------------- */
115
116#define BAUDRATE        19200
117#define BAUDRATE_DIV    (115200 / BAUDRATE)
118
119#define RS232_COM1_BASE 0x3F8
120
121#define RS232_DATA      0x00
122#define RS232_IER       0x01
123#       define IER_RD           0x01
124#       define IER_TBE          0x02
125#       define IER_ER_BRK       0x04
126#       define IER_RS232IN      0x08
127#define RS232_DIVLO     0x00    /* when DLAB = 1 */
128#define RS232_DIVHI     0x01    /* when DLAB = 1 */
129#define RS232_IIR       0x02
130#define RS232_LCR       0x03
131#       define LCR_DATA5        0x00
132#       define LCR_DATA6        0x01
133#       define LCR_DATA7        0x02
134#       define LCR_DATA8        0x03
135#       define LCR_TWOSTOP      0x04
136#       define LCR_PARITY       0x08
137#       define LCR_EVEN         0x10
138#       define LCR_STICK        0x20
139#       define LCR_DLAB         0x80
140#define RS232_MCR       0x04
141#       define MCR_DTR          0x01
142#       define MCR_RTS          0x02
143#       define MCR_ELL          0x04
144#       define MCR_IR           0x40
145#define RS232_LSR       0x05
146#       define LSR_DR           0x01
147#       define LSR_OVR          0x02
148#       define LSR_PE           0x04
149#       define LSR_FE           0x08
150#       define LSR_BRK          0x10
151#       define LSR_TBE          0x20
152#       define LSR_TE           0x40
153#define RS232_MSR       0x06
154#       define MSR_DCTS         0x01
155#       define MSR_DDSR         0x02
156#       define MSR_DRI          0x04
157#       define MSR_DDCD         0x08
158#       define MSR_CTS          0x10
159#       define MSR_DSR          0x20
160#       define MSR_RI           0x40
161#       define MSR_DCD          0x80
162
163#define RS232_SCRATCH   0x07
164
165static bool_t hal_com_received()
166{
167        return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_DR) != 0;
168}
169
170static bool_t hal_com_transmit_empty()
171{
172        return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_TBE) != 0;
173}
174
175char hal_com_read()
176{
177        while (!hal_com_received());
178        return in8(RS232_COM1_BASE + RS232_DATA);
179}
180
181void hal_com_send(uint8_t chan, char c)
182{
183        uint8_t mcr = in8(RS232_COM1_BASE + RS232_MCR);
184        out8(RS232_COM1_BASE + RS232_MCR, mcr | MCR_RTS);
185
186        while (!hal_com_transmit_empty());
187        out8(RS232_COM1_BASE + RS232_DATA, chan | 0x80);
188        out8(RS232_COM1_BASE + RS232_DATA, c);
189
190        out8(RS232_COM1_BASE + RS232_MCR, mcr);
191}
192
193/*
194 * Called early to provide x86-specific messages. Interrupts disabled.
195 */
196void hal_com_init_early()
197{
198        /* Disable all interrupts */
199        out8(RS232_COM1_BASE + RS232_IER, 0x00);
200
201        /* Set baudrate */
202        out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB);
203        out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV);
204        out8(RS232_COM1_BASE + RS232_DIVHI, 0);
205
206        /* 8bits, no parity, one stop bit */
207        out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8);
208
209        /* DTR set, and also DSR */
210        out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR);
211        out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR);
212}
213
214static void hal_com_init()
215{
216        /* Disable all interrupts */
217        out8(RS232_COM1_BASE + RS232_IER, 0x00);
218
219        /* Set baudrate */
220        out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB);
221        out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV);
222        out8(RS232_COM1_BASE + RS232_DIVHI, 0);
223
224        /* 8bits, no parity, one stop bit */
225        out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8);
226
227        /* Enable IRQs, DTR set, and also DSR */
228        out8(RS232_COM1_BASE + RS232_IER, IER_RD|IER_RS232IN);
229        out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR);
230        out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR);
231}
232
233/* -------------------------------------------------------------------------- */
234
235size_t ioapic_pins __in_kdata = 0;
236paddr_t ioapic_pa __in_kdata = 0;
237vaddr_t ioapic_va __in_kdata = 0;
238
239#define IOREGSEL        0x00
240#define IOWIN   0x10
241
242#define IOAPICID        0x00
243#define IOAPICVER       0x01
244#define IOAPICARB       0x02
245
246#define IOREDTBL        0x10
247#       define IOREDTBL_DEL_FIXED       0x000
248#       define IOREDTBL_DEL_LOPRI       0x100
249#       define IOREDTBL_DEL_SMI         0x200
250#       define IOREDTBL_DEL_NMI         0x400
251#       define IOREDTBL_DEL_INIT        0x500
252#       define IOREDTBL_DEL_EXTINT      0x700
253#       define IOREDTBL_DEM_PHYS        0x000
254#       define IOREDTBL_DEM_LOGIC       0x800
255#       define IOREDTBL_DES_SHIFT       56
256#       define IOREDTBL_MSK             0x10000
257
258void hal_ioapic_write(uint8_t reg, uint32_t val)
259{
260        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg;
261        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val;
262}
263
264uint32_t hal_ioapic_read(uint8_t reg)
265{
266        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg;
267        return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN));
268}
269
270void hal_ioapic_disable_entry(uint8_t index)
271{
272        const uint64_t data = IOREDTBL_MSK;
273
274        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
275        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
276}
277
278void hal_ioapic_set_entry(uint8_t index, uint8_t vec, uint8_t dest)
279{
280        const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) |
281            IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | vec;
282
283        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
284        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
285}
286
287static void hal_ioapic_init()
288{
289        uint32_t ver;
290        size_t i;
291
292        ver = hal_ioapic_read(IOAPICVER);
293        ioapic_pins = ((ver >> 16) & 0xFF) + 1;
294
295        /* Explicitly disable (mask) each vector */
296        for (i = 0; i < ioapic_pins; i++) {
297                hal_ioapic_disable_entry(i);
298        }
299
300        x86_printf("IOAPICPINS: #%z\n", ioapic_pins);
301
302        /* Now, enable the com1 port and the keyboard */
303        hal_ioapic_set_entry(IRQ_COM1, IOAPIC_COM1_VECTOR, 0);
304        hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0);
305}
306
307/* -------------------------------------------------------------------------- */
308
309paddr_t lapic_pa __in_kdata = 0;
310vaddr_t lapic_va __in_kdata = 0;
311
312void hal_lapic_write(uint32_t reg, uint32_t val)
313{
314        *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val;
315}
316
317uint32_t hal_lapic_read(uint32_t reg)
318{
319        return *((volatile uint32_t *)((uint8_t *)lapic_va + reg));
320}
321
322uint32_t hal_lapic_gid()
323{
324        return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT;
325}
326
327/*
328 * Use the PIT, which has a standard clock frequency, to determine the CPU's
329 * exact bus frequency.
330 */
331static void hal_lapic_calibrate()
332{
333        uint64_t pittick, lapictick0, lapictick1;
334        uint32_t lapicticks, lapicstart;
335
336        /* Initialize the LAPIC timer to the maximum value */
337        hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF);
338
339        /* Initialize the PIT */
340        hal_pit_init();
341
342        pittick = hal_pit_timer_read() + 1;
343        while (hal_pit_timer_read() < pittick) {
344                /* Wait until start of a PIT tick */
345        }
346
347        /* Read base count from LAPIC */
348        lapictick0 = hal_lapic_read(LAPIC_CCR_TIMER);
349
350        while (hal_pit_timer_read() < pittick + (PIT_FREQUENCY + HZ/2) / HZ) {
351                /* Wait 1/HZ sec = 10ms */
352        }
353
354        /* Read final count from LAPIC */
355        lapictick1 = hal_lapic_read(LAPIC_CCR_TIMER);
356
357        /* Total number of LAPIC ticks per 1/HZ tick */
358        lapicticks = (lapictick1 - lapictick0);
359
360        /* Finally, calibrate the timer, an interrupt each 1s. */
361        lapicstart = - (lapicticks * 100);
362        hal_lapic_write(LAPIC_ICR_TIMER, lapicstart);
363}
364
365/*
366 * We have 8 interrupt sources:
367 *  - Spurious
368 *  - APIC Timer (TMR)
369 *  - Local Interrupt 0 (LINT0)
370 *  - Local Interrupt 1 (LINT1)
371 *  - Performance Monitor Counters (PMC)
372 *  - Thermal Sensors (THM)
373 *  - APIC internal error (ERR)
374 *  - Extended (Implementation dependent)
375 * Only the Spurious and APIC Timer interrupts are enabled.
376 */
377static void hal_lapic_init()
378{
379        if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) {
380                x86_panic("APICBASE and ACPI don't match!\n");
381        }
382        wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN);
383
384        hal_lapic_write(LAPIC_TPR, 0);
385        hal_lapic_write(LAPIC_EOI, 0);
386        hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|VECTOR_APIC_SPURIOU);
387
388        /* Explicitly disable (mask) each vector */
389        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M);
390        hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M);
391        hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M);
392        hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M);
393        hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M);
394        hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M);
395
396        /* Now, enable the timer in repeated mode. */
397        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M);
398        hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1);
399        hal_lapic_calibrate();
400        hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR);
401}
402
403/* -------------------------------------------------------------------------- */
404
405void hal_apic_init()
406{
407        /* Disable the PIC */
408        hal_pic_init();
409
410        /* Enable the LAPIC */
411        hal_lapic_init();
412
413        /* Enable the IOAPIC */
414        hal_ioapic_init();
415
416        /* Enable the Serial Port */
417        hal_com_init();
418}
419
Note: See TracBrowser for help on using the repository browser.