1 | /* |
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2 | * hal_apic.c - Advanced Programmable Interrupt Controller |
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3 | * |
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4 | * Copyright (c) 2017 Maxime Villard |
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5 | * |
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6 | * This file is part of ALMOS-MKH. |
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7 | * |
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8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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9 | * under the terms of the GNU General Public License as published by |
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10 | * the Free Software Foundation; version 2.0 of the License. |
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11 | * |
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12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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15 | * General Public License for more details. |
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16 | * |
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17 | * You should have received a copy of the GNU General Public License |
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18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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20 | */ |
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21 | |
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22 | #include <hal_types.h> |
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23 | #include <hal_boot.h> |
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24 | #include <hal_register.h> |
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25 | #include <hal_segmentation.h> |
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26 | #include <hal_apic.h> |
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27 | #include <hal_internal.h> |
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28 | |
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29 | #include <memcpy.h> |
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30 | #include <thread.h> |
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31 | #include <string.h> |
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32 | #include <process.h> |
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33 | #include <printk.h> |
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34 | #include <vmm.h> |
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35 | #include <core.h> |
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36 | #include <cluster.h> |
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37 | |
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38 | /* -------------------------------------------------------------------------- */ |
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39 | |
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40 | #define PIC1_CMD 0x0020 |
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41 | #define PIC1_DATA 0x0021 |
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42 | #define PIC2_CMD 0x00a0 |
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43 | #define PIC2_DATA 0x00a1 |
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44 | |
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45 | static void hal_pic_init() |
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46 | { |
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47 | /* |
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48 | * Disable the PIC (8259A). We are going to use IOAPIC instead. |
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49 | */ |
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50 | out8(PIC1_DATA, 0xff); |
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51 | out8(PIC2_DATA, 0xff); |
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52 | } |
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53 | |
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54 | /* -------------------------------------------------------------------------- */ |
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55 | |
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56 | uint64_t pit_ticks_base __in_kdata = 0; |
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57 | |
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58 | #define PIT_FREQUENCY 1193182 |
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59 | #define HZ 100 /* 1/HZ = 10ms */ |
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60 | #define muHZ 1000000 /* 1/muHZ = 1 microsecond */ |
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61 | |
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62 | #define PIT_TIMER0 0x40 |
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63 | |
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64 | #define PIT_CMD 0x43 |
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65 | # define CMD_BINARY 0x00 /* Use Binary counter values */ |
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66 | # define CMD_BCD 0x01 /* Use Binary Coded Decimal counter values */ |
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67 | # define CMD_MODE0 0x00 /* Interrupt on Terminal Count */ |
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68 | # define CMD_MODE1 0x02 /* Hardware Retriggerable One-Shot */ |
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69 | # define CMD_MODE2 0x04 /* Rate Generator */ |
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70 | # define CMD_MODE3 0x06 /* Square Wave */ |
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71 | # define CMD_MODE4 0x08 /* Software Trigerred Strobe */ |
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72 | # define CMD_MODE5 0x0a /* Hardware Trigerred Strobe */ |
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73 | # define CMD_LATCH 0x00 /* latch counter for reading */ |
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74 | # define CMD_LSB 0x10 /* LSB, 8 bits */ |
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75 | # define CMD_MSB 0x20 /* MSB, 8 bits */ |
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76 | # define CMD_16BIT 0x30 /* LSB and MSB, 16 bits */ |
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77 | # define CMD_COUNTER0 0x00 |
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78 | # define CMD_COUNTER1 0x40 |
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79 | # define CMD_COUNTER2 0x80 |
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80 | # define CMD_READBACK 0xc0 |
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81 | |
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82 | void hal_pit_reset(uint16_t val) |
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83 | { |
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84 | pit_ticks_base = 0; |
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85 | |
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86 | /* Initialize PIT clock 0 to value given. */ |
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87 | out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT); |
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88 | out8(PIT_TIMER0, (val >> 0) & 0xFF); |
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89 | out8(PIT_TIMER0, (val >> 8) & 0xFF); |
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90 | } |
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91 | |
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92 | uint64_t |
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93 | hal_pit_timer_read() |
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94 | { |
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95 | static uint16_t last; |
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96 | |
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97 | uint8_t lo, hi; |
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98 | uint16_t ctr; |
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99 | uint64_t ticks; |
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100 | |
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101 | /* Read the current timer counter. */ |
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102 | out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH); |
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103 | lo = in8(PIT_TIMER0); |
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104 | hi = in8(PIT_TIMER0); |
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105 | ctr = (hi << 8) | lo; |
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106 | |
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107 | /* If the counter has wrapped, assume we're into the next tick. */ |
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108 | if (ctr > last) |
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109 | pit_ticks_base += 0xFFFF; |
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110 | last = ctr; |
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111 | |
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112 | ticks = pit_ticks_base + (0xFFFF - ctr); |
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113 | |
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114 | return ticks; |
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115 | } |
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116 | |
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117 | /* |
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118 | * Wait approximately n microseconds. |
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119 | */ |
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120 | void |
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121 | hal_pit_delay(uint64_t n) |
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122 | { |
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123 | uint64_t nticks; |
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124 | |
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125 | nticks = 0; |
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126 | hal_pit_reset(0); |
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127 | |
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128 | while (n > 0) { |
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129 | while (hal_pit_timer_read() - nticks < (PIT_FREQUENCY + muHZ/2) / muHZ) { |
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130 | /* Wait 1/muHZ sec = 1 microsecond */ |
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131 | } |
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132 | nticks++; |
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133 | n--; |
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134 | } |
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135 | } |
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136 | |
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137 | /* -------------------------------------------------------------------------- */ |
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138 | |
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139 | #define BAUDRATE 19200 |
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140 | #define BAUDRATE_DIV (115200 / BAUDRATE) |
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141 | |
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142 | #define RS232_COM1_BASE 0x3F8 |
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143 | |
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144 | #define RS232_DATA 0x00 |
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145 | #define RS232_IER 0x01 |
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146 | # define IER_RD 0x01 |
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147 | # define IER_TBE 0x02 |
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148 | # define IER_ER_BRK 0x04 |
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149 | # define IER_RS232IN 0x08 |
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150 | #define RS232_DIVLO 0x00 /* when DLAB = 1 */ |
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151 | #define RS232_DIVHI 0x01 /* when DLAB = 1 */ |
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152 | #define RS232_IIR 0x02 |
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153 | #define RS232_LCR 0x03 |
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154 | # define LCR_DATA5 0x00 |
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155 | # define LCR_DATA6 0x01 |
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156 | # define LCR_DATA7 0x02 |
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157 | # define LCR_DATA8 0x03 |
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158 | # define LCR_TWOSTOP 0x04 |
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159 | # define LCR_PARITY 0x08 |
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160 | # define LCR_EVEN 0x10 |
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161 | # define LCR_STICK 0x20 |
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162 | # define LCR_DLAB 0x80 |
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163 | #define RS232_MCR 0x04 |
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164 | # define MCR_DTR 0x01 |
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165 | # define MCR_RTS 0x02 |
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166 | # define MCR_ELL 0x04 |
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167 | # define MCR_IR 0x40 |
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168 | #define RS232_LSR 0x05 |
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169 | # define LSR_DR 0x01 |
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170 | # define LSR_OVR 0x02 |
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171 | # define LSR_PE 0x04 |
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172 | # define LSR_FE 0x08 |
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173 | # define LSR_BRK 0x10 |
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174 | # define LSR_TBE 0x20 |
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175 | # define LSR_TE 0x40 |
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176 | #define RS232_MSR 0x06 |
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177 | # define MSR_DCTS 0x01 |
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178 | # define MSR_DDSR 0x02 |
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179 | # define MSR_DRI 0x04 |
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180 | # define MSR_DDCD 0x08 |
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181 | # define MSR_CTS 0x10 |
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182 | # define MSR_DSR 0x20 |
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183 | # define MSR_RI 0x40 |
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184 | # define MSR_DCD 0x80 |
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185 | |
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186 | #define RS232_SCRATCH 0x07 |
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187 | |
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188 | static bool_t hal_com_received() |
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189 | { |
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190 | return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_DR) != 0; |
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191 | } |
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192 | |
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193 | static bool_t hal_com_transmit_empty() |
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194 | { |
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195 | return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_TBE) != 0; |
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196 | } |
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197 | |
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198 | char hal_com_read() |
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199 | { |
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200 | while (!hal_com_received()); |
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201 | return in8(RS232_COM1_BASE + RS232_DATA); |
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202 | } |
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203 | |
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204 | void hal_com_send(uint8_t chan, char c) |
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205 | { |
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206 | uint8_t mcr = in8(RS232_COM1_BASE + RS232_MCR); |
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207 | out8(RS232_COM1_BASE + RS232_MCR, mcr | MCR_RTS); |
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208 | |
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209 | while (!hal_com_transmit_empty()); |
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210 | out8(RS232_COM1_BASE + RS232_DATA, chan | 0x80); |
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211 | out8(RS232_COM1_BASE + RS232_DATA, c); |
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212 | |
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213 | out8(RS232_COM1_BASE + RS232_MCR, mcr); |
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214 | } |
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215 | |
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216 | /* |
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217 | * Called early to provide x86-specific messages. Interrupts disabled. |
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218 | */ |
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219 | void hal_com_init_early() |
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220 | { |
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221 | /* Disable all interrupts */ |
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222 | out8(RS232_COM1_BASE + RS232_IER, 0x00); |
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223 | |
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224 | /* Set baudrate */ |
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225 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB); |
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226 | out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV); |
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227 | out8(RS232_COM1_BASE + RS232_DIVHI, 0); |
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228 | |
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229 | /* 8bits, no parity, one stop bit */ |
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230 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8); |
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231 | |
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232 | /* DTR set, and also DSR */ |
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233 | out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR); |
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234 | out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR); |
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235 | } |
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236 | |
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237 | static void hal_com_init() |
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238 | { |
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239 | /* Disable all interrupts */ |
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240 | out8(RS232_COM1_BASE + RS232_IER, 0x00); |
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241 | |
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242 | /* Set baudrate */ |
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243 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB); |
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244 | out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV); |
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245 | out8(RS232_COM1_BASE + RS232_DIVHI, 0); |
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246 | |
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247 | /* 8bits, no parity, one stop bit */ |
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248 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8); |
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249 | |
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250 | /* Enable IRQs, DTR set, and also DSR */ |
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251 | out8(RS232_COM1_BASE + RS232_IER, IER_RD|IER_RS232IN); |
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252 | out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR); |
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253 | out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR); |
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254 | } |
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255 | |
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256 | /* -------------------------------------------------------------------------- */ |
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257 | |
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258 | size_t ioapic_pins __in_kdata = 0; |
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259 | paddr_t ioapic_pa __in_kdata = 0; |
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260 | vaddr_t ioapic_va __in_kdata = 0; |
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261 | |
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262 | #define IOREGSEL 0x00 |
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263 | #define IOWIN 0x10 |
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264 | |
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265 | #define IOAPICID 0x00 |
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266 | #define IOAPICVER 0x01 |
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267 | #define IOAPICARB 0x02 |
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268 | |
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269 | #define IOREDTBL 0x10 |
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270 | # define IOREDTBL_DEL_FIXED 0x000 |
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271 | # define IOREDTBL_DEL_LOPRI 0x100 |
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272 | # define IOREDTBL_DEL_SMI 0x200 |
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273 | # define IOREDTBL_DEL_NMI 0x400 |
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274 | # define IOREDTBL_DEL_INIT 0x500 |
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275 | # define IOREDTBL_DEL_EXTINT 0x700 |
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276 | # define IOREDTBL_DEM_PHYS 0x000 |
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277 | # define IOREDTBL_DEM_LOGIC 0x800 |
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278 | # define IOREDTBL_DES_SHIFT 56 |
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279 | # define IOREDTBL_MSK 0x10000 |
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280 | |
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281 | void hal_ioapic_write(uint8_t reg, uint32_t val) |
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282 | { |
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283 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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284 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val; |
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285 | } |
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286 | |
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287 | uint32_t hal_ioapic_read(uint8_t reg) |
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288 | { |
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289 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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290 | return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)); |
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291 | } |
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292 | |
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293 | void hal_ioapic_bind_irq(uint8_t irq, uint8_t vec, uint8_t dest) |
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294 | { |
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295 | const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) | |
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296 | IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | IOREDTBL_MSK | vec; |
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297 | |
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298 | hal_ioapic_write(IOREDTBL + irq * 2, (uint32_t)(data & 0xFFFFFFFF)); |
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299 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, (uint32_t)(data >> 32)); |
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300 | } |
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301 | |
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302 | void hal_ioapic_enable_irq(uint8_t irq) |
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303 | { |
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304 | uint32_t data[2]; |
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305 | |
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306 | data[0] = hal_ioapic_read(IOREDTBL + irq * 2); |
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307 | data[1] = hal_ioapic_read(IOREDTBL + irq * 2 + 1); |
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308 | |
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309 | data[0] &= ~IOREDTBL_MSK; |
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310 | |
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311 | hal_ioapic_write(IOREDTBL + irq * 2, data[0]); |
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312 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, data[1]); |
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313 | } |
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314 | |
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315 | void hal_ioapic_disable_irq(uint8_t irq) |
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316 | { |
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317 | uint32_t data[2]; |
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318 | |
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319 | data[0] = hal_ioapic_read(IOREDTBL + irq * 2); |
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320 | data[1] = hal_ioapic_read(IOREDTBL + irq * 2 + 1); |
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321 | |
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322 | data[0] |= IOREDTBL_MSK; |
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323 | |
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324 | hal_ioapic_write(IOREDTBL + irq * 2, data[0]); |
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325 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, data[1]); |
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326 | } |
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327 | |
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328 | static void hal_ioapic_init() |
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329 | { |
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330 | uint32_t ver; |
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331 | size_t i; |
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332 | |
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333 | ver = hal_ioapic_read(IOAPICVER); |
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334 | ioapic_pins = ((ver >> 16) & 0xFF) + 1; |
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335 | |
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336 | /* Explicitly disable (mask) each vector */ |
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337 | for (i = 0; i < ioapic_pins; i++) { |
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338 | hal_ioapic_disable_irq(i); |
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339 | } |
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340 | |
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341 | x86_printf("IOAPICPINS: #%z\n", ioapic_pins); |
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342 | |
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343 | /* Now, enable the com1 port and the keyboard */ |
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344 | hal_ioapic_bind_irq(IRQ_COM1, IOAPIC_COM1_VECTOR, 0); |
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345 | hal_ioapic_enable_irq(IRQ_COM1); |
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346 | hal_ioapic_bind_irq(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0); |
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347 | hal_ioapic_enable_irq(IRQ_KEYBOARD); |
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348 | } |
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349 | |
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350 | /* -------------------------------------------------------------------------- */ |
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351 | |
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352 | paddr_t lapic_pa __in_kdata = 0; |
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353 | vaddr_t lapic_va __in_kdata = 0; |
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354 | |
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355 | void hal_lapic_write(uint32_t reg, uint32_t val) |
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356 | { |
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357 | *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val; |
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358 | } |
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359 | |
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360 | uint32_t hal_lapic_read(uint32_t reg) |
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361 | { |
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362 | return *((volatile uint32_t *)((uint8_t *)lapic_va + reg)); |
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363 | } |
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364 | |
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365 | uint32_t hal_lapic_gid() |
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366 | { |
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367 | return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT; |
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368 | } |
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369 | |
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370 | static void hal_lapic_icr_wait() |
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371 | { |
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372 | while ((hal_lapic_read(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0) { |
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373 | pause(); |
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374 | } |
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375 | } |
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376 | |
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377 | /* |
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378 | * Use the PIT, which has a standard clock frequency, to determine the CPU's |
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379 | * exact bus frequency. |
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380 | */ |
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381 | static void hal_lapic_calibrate() |
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382 | { |
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383 | uint64_t pittick, lapictick0, lapictick1; |
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384 | uint32_t lapicticks, lapicstart; |
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385 | |
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386 | /* Initialize the LAPIC timer to the maximum value */ |
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387 | hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF); |
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388 | |
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389 | /* Reset the PIT */ |
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390 | hal_pit_reset(-1); |
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391 | |
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392 | pittick = hal_pit_timer_read() + 1; |
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393 | while (hal_pit_timer_read() < pittick) { |
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394 | /* Wait until start of a PIT tick */ |
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395 | } |
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396 | |
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397 | /* Read base count from LAPIC */ |
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398 | lapictick0 = hal_lapic_read(LAPIC_CCR_TIMER); |
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399 | |
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400 | while (hal_pit_timer_read() < pittick + (PIT_FREQUENCY + HZ/2) / HZ) { |
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401 | /* Wait 1/HZ sec = 10ms */ |
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402 | } |
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403 | |
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404 | /* Read final count from LAPIC */ |
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405 | lapictick1 = hal_lapic_read(LAPIC_CCR_TIMER); |
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406 | |
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407 | /* Total number of LAPIC ticks per 1/HZ tick */ |
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408 | lapicticks = (lapictick1 - lapictick0); |
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409 | |
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410 | /* Finally, calibrate the timer, an interrupt each 1s. */ |
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411 | lapicstart = - (lapicticks * 100); |
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412 | hal_lapic_write(LAPIC_ICR_TIMER, lapicstart); |
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413 | } |
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414 | |
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415 | /* |
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416 | * We have 8 interrupt sources: |
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417 | * - Spurious |
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418 | * - APIC Timer (TMR) |
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419 | * - Local Interrupt 0 (LINT0) |
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420 | * - Local Interrupt 1 (LINT1) |
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421 | * - Performance Monitor Counters (PMC) |
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422 | * - Thermal Sensors (THM) |
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423 | * - APIC internal error (ERR) |
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424 | * - Extended (Implementation dependent) |
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425 | * Only the Spurious and APIC Timer interrupts are enabled. |
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426 | */ |
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427 | void cpu_lapic_init() |
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428 | { |
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429 | if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) { |
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430 | x86_panic("APICBASE and ACPI don't match!\n"); |
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431 | } |
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432 | wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN); |
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433 | |
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434 | hal_lapic_write(LAPIC_TPR, 0); |
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435 | hal_lapic_write(LAPIC_EOI, 0); |
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436 | hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|VECTOR_APIC_SPURIOU); |
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437 | |
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438 | /* Explicitly disable (mask) each vector */ |
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439 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M); |
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440 | hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M); |
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441 | hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M); |
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442 | hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M); |
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443 | hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M); |
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444 | hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M); |
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445 | |
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446 | /* Now, enable the timer in repeated mode. */ |
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447 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M); |
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448 | hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1); |
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449 | hal_lapic_calibrate(); |
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450 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR); |
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451 | } |
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452 | |
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453 | /* -------------------------------------------------------------------------- */ |
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454 | |
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455 | static void |
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456 | hal_ipi_init(uint32_t gid) |
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457 | { |
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458 | /* clear the error status */ |
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459 | hal_lapic_write(LAPIC_ESR, 0); |
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460 | (void)hal_lapic_read(LAPIC_ESR); |
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461 | |
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462 | /* send the IPI */ |
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463 | hal_lapic_write(LAPIC_ICRHI, gid << LAPIC_ID_SHIFT); |
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464 | hal_lapic_write(LAPIC_ICRLO, LAPIC_DLMODE_INIT | LAPIC_LEVEL_ASSERT); |
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465 | hal_lapic_icr_wait(); |
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466 | |
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467 | /* wait 10ms */ |
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468 | hal_pit_delay(10000); |
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469 | |
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470 | hal_lapic_write(LAPIC_ICRLO, |
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471 | LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT); |
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472 | hal_lapic_icr_wait(); |
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473 | } |
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474 | |
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475 | static void |
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476 | hal_ipi_startup(uint32_t gid, paddr_t pa) |
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477 | { |
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478 | /* clear the error status */ |
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479 | hal_lapic_write(LAPIC_ESR, 0); |
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480 | (void)hal_lapic_read(LAPIC_ESR); |
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481 | |
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482 | /* send the IPI */ |
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483 | hal_lapic_icr_wait(); |
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484 | hal_lapic_write(LAPIC_ICRHI, gid << LAPIC_ID_SHIFT); |
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485 | hal_lapic_write(LAPIC_ICRLO, pa | LAPIC_DLMODE_STARTUP | |
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486 | LAPIC_LEVEL_ASSERT); |
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487 | hal_lapic_icr_wait(); |
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488 | } |
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489 | |
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490 | /* -------------------------------------------------------------------------- */ |
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491 | |
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492 | int |
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493 | boot_cpuN(uint32_t gid, paddr_t pa) |
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494 | { |
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495 | /* |
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496 | * Bootstrap code must be addressable in real mode and it must be |
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497 | * page-aligned. |
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498 | */ |
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499 | XASSERT(pa < 0x10000 && pa % PAGE_SIZE == 0); |
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500 | |
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501 | /* |
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502 | * Local cache flush, in case the BIOS has left the AP with its cache |
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503 | * disabled. It may not be able to cope with MP coherency. |
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504 | */ |
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505 | wbinvd(); |
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506 | |
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507 | hal_ipi_init(gid); |
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508 | hal_pit_delay(10000); |
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509 | |
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510 | hal_ipi_startup(gid, pa / PAGE_SIZE); |
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511 | hal_pit_delay(200); |
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512 | |
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513 | hal_ipi_startup(gid, pa / PAGE_SIZE); |
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514 | hal_pit_delay(200); |
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515 | |
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516 | return 0; |
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517 | } |
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518 | |
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519 | /* -------------------------------------------------------------------------- */ |
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520 | |
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521 | void hal_apic_init() |
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522 | { |
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523 | /* Disable the PIC */ |
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524 | hal_pic_init(); |
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525 | |
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526 | /* Enable the IOAPIC */ |
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527 | hal_ioapic_init(); |
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528 | |
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529 | /* Enable the Serial Port */ |
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530 | hal_com_init(); |
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531 | } |
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532 | |
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