[29] | 1 | /* |
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| 2 | * hal_init.c - C initialization procedure for x86. |
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| 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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| 22 | #include <hal_types.h> |
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| 23 | #include <hal_boot.h> |
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[32] | 24 | #include <hal_multiboot.h> |
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[29] | 25 | #include <hal_segmentation.h> |
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[45] | 26 | #include <hal_acpi.h> |
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[82] | 27 | #include <hal_apic.h> |
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[35] | 28 | #include <hal_internal.h> |
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[72] | 29 | #include <hal_remote.h> |
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[99] | 30 | #include <hal_irqmask.h> |
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[29] | 31 | |
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| 32 | #include <memcpy.h> |
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| 33 | #include <thread.h> |
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| 34 | #include <string.h> |
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| 35 | #include <process.h> |
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| 36 | #include <printk.h> |
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| 37 | #include <vmm.h> |
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| 38 | #include <core.h> |
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| 39 | #include <cluster.h> |
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[70] | 40 | #include <chdev.h> |
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[29] | 41 | |
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[70] | 42 | #include <boot_info.h> |
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| 43 | |
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[81] | 44 | void kernel_init(boot_info_t *info); |
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| 45 | |
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[29] | 46 | static void gdt_create(); |
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| 47 | static void idt_create(); |
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| 48 | void cpu_attach(); |
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| 49 | |
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[44] | 50 | size_t mytest __in_kdata = 0; |
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[32] | 51 | |
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| 52 | struct multiboot_info mb_info __in_kdata; |
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| 53 | char mb_loader_name[PAGE_SIZE] __in_kdata; |
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| 54 | uint8_t mb_mmap[PAGE_SIZE] __in_kdata; |
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| 55 | |
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[29] | 56 | /* -------------------------------------------------------------------------- */ |
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| 57 | |
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[32] | 58 | static void |
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| 59 | dump_memmap() |
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| 60 | { |
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| 61 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 62 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 63 | size_t i; |
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| 64 | |
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| 65 | if (!(mb_info.mi_flags & MULTIBOOT_INFO_HAS_MMAP)) |
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[46] | 66 | x86_panic("No mmap"); |
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[32] | 67 | |
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| 68 | i = 0; |
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| 69 | while (i < mmap_length) { |
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| 70 | struct multiboot_mmap *mm; |
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| 71 | |
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| 72 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 73 | |
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| 74 | x86_printf("-> [%Z, %Z] %s\n", mm->mm_base_addr, |
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| 75 | mm->mm_base_addr + mm->mm_length, |
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| 76 | (mm->mm_type == 1) ? "ram" : "rsv" ); |
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| 77 | |
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| 78 | i += mm->mm_size + 4; |
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| 79 | } |
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| 80 | } |
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| 81 | |
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[135] | 82 | /* -------------------------------------------------------------------------- */ |
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| 83 | |
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| 84 | static void init_bootinfo_icu(boot_device_t *dev) |
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| 85 | { |
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[137] | 86 | extern uint32_t hwi_baseidx; |
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| 87 | extern uint32_t wti_baseidx; |
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| 88 | extern uint32_t pti_baseidx; |
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| 89 | extern size_t ioapic_pins; |
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| 90 | |
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[135] | 91 | memset(dev, 0, sizeof(boot_device_t)); |
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| 92 | |
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[137] | 93 | dev->base = 0; |
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[135] | 94 | dev->type = (DEV_FUNC_ICU << 16) | IMPL_ICU_XCU; |
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| 95 | dev->channels = 1; |
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[137] | 96 | |
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| 97 | /* |
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| 98 | * Give 20% of the pins to HWI, 80% to WTI. |
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| 99 | */ |
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| 100 | dev->param0 = (ioapic_pins * 20) / 100; /* hwi_nr */ |
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| 101 | dev->param1 = ioapic_pins - dev->param0; /* wti_nr */ |
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| 102 | |
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| 103 | /* |
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| 104 | * We always set 1 for pti_nr. On x86, timer interrupts are handled by |
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| 105 | * LAPIC, which is per-cpu and not global. Therefore, we always have one |
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| 106 | * timer for each CPU, and its IRQ number is faked to 0. |
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| 107 | */ |
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| 108 | dev->param2 = 1; /* pti_nr */ |
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| 109 | |
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[135] | 110 | dev->param3 = 0; |
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| 111 | |
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[137] | 112 | /* Set the base idx for the XCU driver */ |
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| 113 | hwi_baseidx = 0; |
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| 114 | wti_baseidx = dev->param0; |
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| 115 | pti_baseidx = 0xFFFFFFFF; |
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| 116 | |
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[135] | 117 | #ifdef NOTYET |
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| 118 | uint32_t irqs; /*! number of input IRQs */ |
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| 119 | boot_irq_t irq[32]; /*! array of input IRQS (PIC and ICU only) */ |
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| 120 | #endif |
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| 121 | } |
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| 122 | |
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[119] | 123 | static size_t init_bootinfo_pages_nr() |
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| 124 | { |
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| 125 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 126 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 127 | paddr_t maxpa, pa; |
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| 128 | size_t i; |
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| 129 | |
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| 130 | i = 0; |
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| 131 | maxpa = 0; |
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| 132 | while (i < mmap_length) { |
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| 133 | struct multiboot_mmap *mm; |
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| 134 | |
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| 135 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 136 | |
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| 137 | if (mm->mm_type == 1) { |
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| 138 | pa = mm->mm_base_addr + mm->mm_length; |
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| 139 | if (pa > maxpa) |
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| 140 | maxpa = pa; |
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| 141 | } |
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| 142 | |
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| 143 | i += mm->mm_size + 4; |
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| 144 | } |
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| 145 | |
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| 146 | return (maxpa / PAGE_SIZE); |
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| 147 | } |
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| 148 | |
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[116] | 149 | static size_t init_bootinfo_rsvd(boot_rsvd_t *rsvd) |
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| 150 | { |
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| 151 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 152 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 153 | size_t i, rsvd_nr; |
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| 154 | |
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[137] | 155 | memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD); |
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[116] | 156 | |
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| 157 | i = 0, rsvd_nr = 0; |
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| 158 | while (i < mmap_length) { |
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| 159 | struct multiboot_mmap *mm; |
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| 160 | |
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| 161 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 162 | |
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[119] | 163 | if (mm->mm_type != 1) { |
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| 164 | rsvd[rsvd_nr].first_page = |
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| 165 | rounddown(mm->mm_base_addr, PAGE_SIZE) / PAGE_SIZE; |
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| 166 | rsvd[rsvd_nr].npages = |
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| 167 | roundup(mm->mm_length, PAGE_SIZE) / PAGE_SIZE; |
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| 168 | rsvd_nr++; |
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| 169 | if (rsvd_nr == CONFIG_PPM_MAX_RSVD) |
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| 170 | x86_panic("too many memory holes"); |
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| 171 | } |
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[116] | 172 | |
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| 173 | i += mm->mm_size + 4; |
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| 174 | } |
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| 175 | |
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| 176 | return rsvd_nr; |
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| 177 | } |
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| 178 | |
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[70] | 179 | static void init_bootinfo_core(boot_core_t *core) |
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| 180 | { |
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| 181 | memset(core, 0, sizeof(boot_core_t)); |
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| 182 | |
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| 183 | core->gid = hal_lapic_gid(); |
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| 184 | core->lid = 0; |
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| 185 | core->cxy = 0; |
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| 186 | } |
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| 187 | |
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| 188 | static void init_bootinfo_txt(boot_device_t *dev) |
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| 189 | { |
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| 190 | memset(dev, 0, sizeof(boot_device_t)); |
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| 191 | |
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| 192 | dev->base = 0xB8000; |
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| 193 | dev->type = (DEV_FUNC_TXT << 16) | IMPL_TXT_X86; |
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| 194 | dev->channels = 1; |
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| 195 | dev->param0 = 0; |
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| 196 | dev->param1 = 0; |
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| 197 | dev->param2 = 0; |
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| 198 | dev->param3 = 0; |
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| 199 | |
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| 200 | #ifdef NOTYET |
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| 201 | uint32_t irqs; /*! number of input IRQs */ |
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| 202 | boot_irq_t irq[32]; /*! array of input IRQS (PIC and ICU only) */ |
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| 203 | #endif |
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| 204 | } |
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| 205 | |
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| 206 | static void init_bootinfo(boot_info_t *info) |
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| 207 | { |
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[116] | 208 | size_t offset; |
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[114] | 209 | |
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[70] | 210 | extern uint64_t __kernel_data_start; |
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| 211 | extern uint64_t __kernel_end; |
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| 212 | |
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| 213 | memset(info, 0, sizeof(boot_info_t)); |
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| 214 | |
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| 215 | info->signature = 0; |
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| 216 | |
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| 217 | info->paddr_width = 0; |
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| 218 | info->x_width = 1; |
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| 219 | info->y_width = 1; |
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| 220 | info->x_size = 1; |
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| 221 | info->y_size = 1; |
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| 222 | info->io_cxy = 0; |
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| 223 | |
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| 224 | info->ext_dev_nr = 1; |
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| 225 | init_bootinfo_txt(&info->ext_dev[0]); |
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| 226 | |
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| 227 | info->cxy = 0; |
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| 228 | info->cores_nr = 1; |
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| 229 | init_bootinfo_core(&info->core[0]); |
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| 230 | |
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[137] | 231 | info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd); |
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[70] | 232 | |
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[135] | 233 | init_bootinfo_icu(&info->dev_icu); |
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| 234 | /* TODO: dev_mmc */ |
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| 235 | /* TODO: dev_dma */ |
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| 236 | |
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[116] | 237 | offset = hal_gpt_bootstrap_uniformize(); |
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| 238 | info->pages_offset = offset / PAGE_SIZE; |
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[119] | 239 | info->pages_nr = init_bootinfo_pages_nr(); |
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[70] | 240 | |
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| 241 | info->kernel_code_start = (intptr_t)(KERNTEXTOFF - KERNBASE); |
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| 242 | info->kernel_code_end = (intptr_t)(&__kernel_data_start - KERNBASE) - 1; |
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| 243 | info->kernel_data_start = (intptr_t)(&__kernel_data_start - KERNBASE); |
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| 244 | info->kernel_code_end = (intptr_t)(&__kernel_end - KERNBASE) - 1; |
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| 245 | } |
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| 246 | |
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[29] | 247 | void init_x86_64(paddr_t firstpa) |
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| 248 | { |
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[70] | 249 | boot_info_t btinfo; |
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| 250 | |
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[29] | 251 | x86_printf("[+] init_x86_64 called\n"); |
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| 252 | |
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| 253 | /* Create the global structures */ |
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| 254 | gdt_create(); |
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| 255 | idt_create(); |
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| 256 | |
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| 257 | /* Attach cpu0 */ |
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| 258 | cpu_attach(); |
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| 259 | x86_printf("[+] cpu_attach called\n"); |
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| 260 | |
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[47] | 261 | x86_printf("[+] bootloader: '%s'\n", mb_loader_name); |
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[32] | 262 | |
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| 263 | dump_memmap(); |
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| 264 | x86_printf("[+] dump finished\n"); |
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| 265 | |
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[35] | 266 | hal_gpt_init(firstpa); |
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| 267 | x86_printf("[+] hal_gpt_init called\n"); |
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[29] | 268 | |
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[35] | 269 | hal_acpi_init(); |
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| 270 | x86_printf("[+] hal_acpi_init called\n"); |
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| 271 | |
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[45] | 272 | hal_gpt_bootstrap_reset(); |
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| 273 | x86_printf("[+] hal_gpt_bootstrap_reset called\n"); |
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| 274 | |
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[82] | 275 | hal_apic_init(); |
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| 276 | x86_printf("[+] hal_apic_init called\n"); |
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[45] | 277 | |
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[46] | 278 | hal_tls_init_cpu0(); |
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| 279 | x86_printf("[+] hal_tls_init_cpu0 called\n"); |
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| 280 | |
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[44] | 281 | x86_printf("-> mytest = %z\n", mytest); |
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[94] | 282 | void *hoho = &init_x86_64; |
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[74] | 283 | xptr_t myptr = XPTR(0, &mytest); |
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[35] | 284 | |
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[94] | 285 | hal_remote_spt(myptr, hoho); |
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| 286 | x86_printf("-> mytest = %Z\n", hal_remote_lpt(myptr)); |
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| 287 | |
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[99] | 288 | init_bootinfo(&btinfo); |
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[94] | 289 | |
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[99] | 290 | reg_t dummy; |
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| 291 | hal_enable_irq(&dummy); |
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| 292 | |
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[70] | 293 | kernel_init(&btinfo); |
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[99] | 294 | |
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[70] | 295 | x86_printf("[+] kernel_init called\n"); |
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| 296 | |
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[99] | 297 | while (1); |
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| 298 | |
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[82] | 299 | // void x86_stop(); |
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| 300 | // x86_stop(); |
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[80] | 301 | |
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[29] | 302 | int m = 0; |
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| 303 | int v = 1 / m; |
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| 304 | |
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[35] | 305 | char *buf = NULL; |
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| 306 | *buf = (char)0x01; |
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| 307 | |
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[29] | 308 | x86_printf("ALIVE!\n"); |
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| 309 | |
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| 310 | while (1); |
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| 311 | } |
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| 312 | |
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| 313 | /* -------------------------------------------------------------------------- */ |
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| 314 | |
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| 315 | uint8_t gdtstore[PAGE_SIZE] __in_kdata; |
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| 316 | uint8_t idtstore[PAGE_SIZE] __in_kdata; |
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| 317 | struct tss cpu0_tss __in_kdata; |
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| 318 | uint8_t cpu0_intr_stack[STKSIZE] __in_kdata; |
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| 319 | uint8_t cpu0_dbfl_stack[STKSIZE] __in_kdata; |
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| 320 | uint8_t cpu0_nmfl_stack[STKSIZE] __in_kdata; |
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| 321 | |
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| 322 | static void |
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| 323 | setregion(struct region_descriptor *rd, void *base, uint16_t limit) |
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| 324 | { |
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| 325 | rd->rd_limit = limit; |
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| 326 | rd->rd_base = (uint64_t)base; |
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| 327 | } |
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| 328 | |
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| 329 | /* -------------------------------------------------------------------------- */ |
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| 330 | |
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| 331 | static void |
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| 332 | gdt_set_memseg(struct gdt_memseg *sd, void *base, size_t limit, |
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| 333 | int type, int dpl, int gran, int is64) |
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| 334 | { |
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| 335 | sd->sd_lolimit = (unsigned)limit; |
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| 336 | sd->sd_lobase = (unsigned long)base; |
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| 337 | sd->sd_type = type; |
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| 338 | sd->sd_dpl = dpl; |
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| 339 | sd->sd_p = 1; |
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| 340 | sd->sd_hilimit = (unsigned)limit >> 16; |
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| 341 | sd->sd_avl = 0; |
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| 342 | sd->sd_long = is64; |
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| 343 | sd->sd_def32 = 0; |
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| 344 | sd->sd_gran = gran; |
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| 345 | sd->sd_hibase = (unsigned long)base >> 24; |
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| 346 | } |
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| 347 | |
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| 348 | static void |
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| 349 | gdt_set_sysseg(struct gdt_sysseg *sd, void *base, size_t limit, |
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| 350 | int type, int dpl, int gran) |
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| 351 | { |
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| 352 | memset(sd, 0, sizeof *sd); |
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| 353 | sd->sd_lolimit = (unsigned)limit; |
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| 354 | sd->sd_lobase = (uint64_t)base; |
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| 355 | sd->sd_type = type; |
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| 356 | sd->sd_dpl = dpl; |
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| 357 | sd->sd_p = 1; |
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| 358 | sd->sd_hilimit = (unsigned)limit >> 16; |
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| 359 | sd->sd_gran = gran; |
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| 360 | sd->sd_hibase = (uint64_t)base >> 24; |
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| 361 | } |
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| 362 | |
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| 363 | static void gdt_create() |
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| 364 | { |
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| 365 | memset(&gdtstore, 0, PAGE_SIZE); |
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| 366 | |
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| 367 | /* Flat segments */ |
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| 368 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KCODE_SEL), 0, |
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| 369 | 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1); |
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| 370 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KDATA_SEL), 0, |
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| 371 | 0xfffff, SDT_MEMRWA, SEL_KPL, 1, 1); |
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| 372 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE_SEL), 0, |
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| 373 | 0xfffff, SDT_MEMERA, SEL_UPL, 1, 1); |
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| 374 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UDATA_SEL), 0, |
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| 375 | 0xfffff, SDT_MEMRWA, SEL_UPL, 1, 1); |
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| 376 | } |
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| 377 | |
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| 378 | void cpu_load_gdt() |
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| 379 | { |
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| 380 | struct region_descriptor region; |
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| 381 | setregion(®ion, &gdtstore, PAGE_SIZE - 1); |
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| 382 | lgdt(®ion); |
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| 383 | } |
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| 384 | |
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| 385 | /* -------------------------------------------------------------------------- */ |
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| 386 | |
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| 387 | static void |
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| 388 | idt_set_seg(struct idt_seg *seg, void *func, int ist, int type, int dpl, int sel) |
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| 389 | { |
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| 390 | seg->gd_looffset = (uint64_t)func & 0xffff; |
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| 391 | seg->gd_selector = sel; |
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| 392 | seg->gd_ist = ist; |
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| 393 | seg->gd_type = type; |
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| 394 | seg->gd_dpl = dpl; |
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| 395 | seg->gd_p = 1; |
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| 396 | seg->gd_hioffset = (uint64_t)func >> 16; |
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| 397 | seg->gd_zero = 0; |
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| 398 | seg->gd_xx1 = 0; |
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| 399 | seg->gd_xx2 = 0; |
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| 400 | seg->gd_xx3 = 0; |
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| 401 | } |
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| 402 | |
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| 403 | static void idt_create() |
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| 404 | { |
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[80] | 405 | extern uint64_t x86_traps[], x86_intrs[], x86_rsvd; |
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[29] | 406 | struct idt_seg *idt; |
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| 407 | size_t i; |
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| 408 | |
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| 409 | idt = (struct idt_seg *)&idtstore; |
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[45] | 410 | |
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[80] | 411 | /* First, put a dead entry */ |
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| 412 | for (i = 0; i < NIDT; i++) { |
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| 413 | idt_set_seg(&idt[i], (void *)&x86_rsvd, 0, |
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| 414 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
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| 415 | } |
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| 416 | |
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[45] | 417 | /* General exceptions */ |
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| 418 | for (i = CPUVEC_MIN; i < CPUVEC_MAX; i++) { |
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| 419 | idt_set_seg(&idt[i], (void *)x86_traps[i - CPUVEC_MIN], 0, |
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| 420 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
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[29] | 421 | } |
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[45] | 422 | |
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| 423 | /* LAPIC interrupts */ |
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| 424 | for (i = LAPICVEC_MIN; i < LAPICVEC_MAX; i++) { |
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| 425 | idt_set_seg(&idt[i], (void *)x86_intrs[i - LAPICVEC_MIN], 0, |
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| 426 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
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| 427 | } |
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[29] | 428 | } |
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| 429 | |
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| 430 | void cpu_load_idt() |
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| 431 | { |
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| 432 | struct region_descriptor region; |
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| 433 | setregion(®ion, &idtstore, PAGE_SIZE - 1); |
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| 434 | lidt(®ion); |
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| 435 | } |
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| 436 | |
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| 437 | /* -------------------------------------------------------------------------- */ |
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| 438 | |
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| 439 | /* |
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| 440 | * The gdt bitmap must be per-cluster. |
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| 441 | */ |
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| 442 | int tss_alloc(struct tss *tss) |
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| 443 | { |
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| 444 | int slot; |
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| 445 | |
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| 446 | /* Once we have proper SMP support, we will change that */ |
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| 447 | slot = GDT_CPU0TSS_SEL; |
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| 448 | |
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| 449 | gdt_set_sysseg(GDT_ADDR_SYS(gdtstore, slot), tss, |
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| 450 | sizeof(*tss) - 1, SDT_SYS386TSS, SEL_KPL, 0); |
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| 451 | |
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| 452 | return GDT_DYNAM_SEL(slot, SEL_KPL); |
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| 453 | } |
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| 454 | |
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| 455 | void cpu_create_tss() |
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| 456 | { |
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| 457 | struct tss *tss = &cpu0_tss; |
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| 458 | int sel; |
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| 459 | |
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| 460 | /* Create the tss */ |
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| 461 | memset(tss, 0, sizeof(*tss)); |
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| 462 | tss->tss_iobase = IOMAP_INVALOFF << 16; |
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| 463 | tss->tss_ist[0] = (uint64_t)cpu0_intr_stack + STKSIZE; |
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| 464 | tss->tss_ist[1] = (uint64_t)cpu0_dbfl_stack + STKSIZE; |
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| 465 | tss->tss_ist[2] = (uint64_t)cpu0_nmfl_stack + STKSIZE; |
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| 466 | sel = tss_alloc(tss); |
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| 467 | |
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| 468 | /* Load it */ |
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| 469 | ltr(sel); |
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| 470 | } |
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| 471 | |
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| 472 | /* -------------------------------------------------------------------------- */ |
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| 473 | |
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| 474 | void cpu_attach() |
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| 475 | { |
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| 476 | cpu_load_gdt(); |
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| 477 | cpu_load_idt(); |
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| 478 | cpu_create_tss(); |
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| 479 | } |
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| 480 | |
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