[29] | 1 | /* |
---|
| 2 | * hal_init.c - C initialization procedure for x86. |
---|
| 3 | * |
---|
| 4 | * Copyright (c) 2017 Maxime Villard |
---|
| 5 | * |
---|
| 6 | * This file is part of ALMOS-MKH. |
---|
| 7 | * |
---|
| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
---|
| 9 | * under the terms of the GNU General Public License as published by |
---|
| 10 | * the Free Software Foundation; version 2.0 of the License. |
---|
| 11 | * |
---|
| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
---|
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 15 | * General Public License for more details. |
---|
| 16 | * |
---|
| 17 | * You should have received a copy of the GNU General Public License |
---|
[234] | 18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
---|
[29] | 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
---|
| 20 | */ |
---|
| 21 | |
---|
| 22 | #include <hal_types.h> |
---|
| 23 | #include <hal_boot.h> |
---|
[32] | 24 | #include <hal_multiboot.h> |
---|
[29] | 25 | #include <hal_segmentation.h> |
---|
[45] | 26 | #include <hal_acpi.h> |
---|
[82] | 27 | #include <hal_apic.h> |
---|
[35] | 28 | #include <hal_internal.h> |
---|
[166] | 29 | #include <hal_register.h> |
---|
| 30 | |
---|
[72] | 31 | #include <hal_remote.h> |
---|
[99] | 32 | #include <hal_irqmask.h> |
---|
[29] | 33 | |
---|
| 34 | #include <memcpy.h> |
---|
| 35 | #include <thread.h> |
---|
| 36 | #include <string.h> |
---|
| 37 | #include <process.h> |
---|
| 38 | #include <printk.h> |
---|
| 39 | #include <vmm.h> |
---|
| 40 | #include <core.h> |
---|
| 41 | #include <cluster.h> |
---|
[70] | 42 | #include <chdev.h> |
---|
[29] | 43 | |
---|
[70] | 44 | #include <boot_info.h> |
---|
| 45 | |
---|
[81] | 46 | void kernel_init(boot_info_t *info); |
---|
| 47 | |
---|
[29] | 48 | static void gdt_create(); |
---|
| 49 | static void idt_create(); |
---|
[168] | 50 | void cpu_tls_init(size_t lid); |
---|
[166] | 51 | void cpu_identify(); |
---|
[237] | 52 | void cpu_attach(size_t lid); |
---|
[29] | 53 | |
---|
[44] | 54 | size_t mytest __in_kdata = 0; |
---|
[32] | 55 | |
---|
| 56 | struct multiboot_info mb_info __in_kdata; |
---|
| 57 | char mb_loader_name[PAGE_SIZE] __in_kdata; |
---|
| 58 | uint8_t mb_mmap[PAGE_SIZE] __in_kdata; |
---|
| 59 | |
---|
[240] | 60 | size_t ncpu __in_kdata = 0; |
---|
| 61 | static boot_info_t btinfo __in_kdata; |
---|
| 62 | |
---|
[236] | 63 | /* x86-specific per-cluster structures */ |
---|
| 64 | uint8_t gdtstore[PAGE_SIZE] __in_kdata; |
---|
| 65 | uint8_t idtstore[PAGE_SIZE] __in_kdata; |
---|
| 66 | |
---|
| 67 | /* x86-specific per-cpu structures */ |
---|
| 68 | typedef struct { |
---|
| 69 | bool_t valid; |
---|
| 70 | struct tss tss; |
---|
| 71 | struct tls tls; |
---|
| 72 | uint8_t boot_stack[STKSIZE]; |
---|
| 73 | uint8_t intr_stack[STKSIZE]; |
---|
| 74 | uint8_t dbfl_stack[STKSIZE]; |
---|
| 75 | uint8_t nmfl_stack[STKSIZE]; |
---|
| 76 | } percpu_archdata_t; |
---|
| 77 | percpu_archdata_t cpudata[CONFIG_MAX_LOCAL_CORES] __in_kdata; |
---|
| 78 | |
---|
[29] | 79 | /* -------------------------------------------------------------------------- */ |
---|
| 80 | |
---|
[32] | 81 | static void |
---|
| 82 | dump_memmap() |
---|
| 83 | { |
---|
| 84 | size_t mmap_length = mb_info.mi_mmap_length; |
---|
| 85 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
---|
| 86 | size_t i; |
---|
| 87 | |
---|
| 88 | if (!(mb_info.mi_flags & MULTIBOOT_INFO_HAS_MMAP)) |
---|
[46] | 89 | x86_panic("No mmap"); |
---|
[32] | 90 | |
---|
| 91 | i = 0; |
---|
| 92 | while (i < mmap_length) { |
---|
| 93 | struct multiboot_mmap *mm; |
---|
| 94 | |
---|
| 95 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
---|
| 96 | |
---|
| 97 | x86_printf("-> [%Z, %Z] %s\n", mm->mm_base_addr, |
---|
| 98 | mm->mm_base_addr + mm->mm_length, |
---|
| 99 | (mm->mm_type == 1) ? "ram" : "rsv" ); |
---|
| 100 | |
---|
| 101 | i += mm->mm_size + 4; |
---|
| 102 | } |
---|
| 103 | } |
---|
| 104 | |
---|
[135] | 105 | /* -------------------------------------------------------------------------- */ |
---|
| 106 | |
---|
[119] | 107 | static size_t init_bootinfo_pages_nr() |
---|
| 108 | { |
---|
| 109 | size_t mmap_length = mb_info.mi_mmap_length; |
---|
| 110 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
---|
| 111 | paddr_t maxpa, pa; |
---|
| 112 | size_t i; |
---|
| 113 | |
---|
| 114 | i = 0; |
---|
| 115 | maxpa = 0; |
---|
| 116 | while (i < mmap_length) { |
---|
| 117 | struct multiboot_mmap *mm; |
---|
| 118 | |
---|
| 119 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
---|
| 120 | |
---|
| 121 | if (mm->mm_type == 1) { |
---|
| 122 | pa = mm->mm_base_addr + mm->mm_length; |
---|
| 123 | if (pa > maxpa) |
---|
| 124 | maxpa = pa; |
---|
| 125 | } |
---|
| 126 | |
---|
| 127 | i += mm->mm_size + 4; |
---|
| 128 | } |
---|
| 129 | |
---|
| 130 | return (maxpa / PAGE_SIZE); |
---|
| 131 | } |
---|
| 132 | |
---|
[116] | 133 | static size_t init_bootinfo_rsvd(boot_rsvd_t *rsvd) |
---|
| 134 | { |
---|
| 135 | size_t mmap_length = mb_info.mi_mmap_length; |
---|
| 136 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
---|
| 137 | size_t i, rsvd_nr; |
---|
| 138 | |
---|
[137] | 139 | memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD); |
---|
[116] | 140 | |
---|
| 141 | i = 0, rsvd_nr = 0; |
---|
| 142 | while (i < mmap_length) { |
---|
| 143 | struct multiboot_mmap *mm; |
---|
| 144 | |
---|
| 145 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
---|
| 146 | |
---|
[119] | 147 | if (mm->mm_type != 1) { |
---|
| 148 | rsvd[rsvd_nr].first_page = |
---|
| 149 | rounddown(mm->mm_base_addr, PAGE_SIZE) / PAGE_SIZE; |
---|
| 150 | rsvd[rsvd_nr].npages = |
---|
| 151 | roundup(mm->mm_length, PAGE_SIZE) / PAGE_SIZE; |
---|
| 152 | rsvd_nr++; |
---|
| 153 | if (rsvd_nr == CONFIG_PPM_MAX_RSVD) |
---|
| 154 | x86_panic("too many memory holes"); |
---|
| 155 | } |
---|
[116] | 156 | |
---|
| 157 | i += mm->mm_size + 4; |
---|
| 158 | } |
---|
| 159 | |
---|
| 160 | return rsvd_nr; |
---|
| 161 | } |
---|
| 162 | |
---|
[70] | 163 | static void init_bootinfo_core(boot_core_t *core) |
---|
| 164 | { |
---|
[240] | 165 | size_t i; |
---|
[70] | 166 | |
---|
[240] | 167 | // XXX: not necessarily contiguous |
---|
| 168 | for (i = 0; i < ncpu; i++) { |
---|
| 169 | memset(&core[i], 0, sizeof(boot_core_t)); |
---|
| 170 | |
---|
| 171 | core[i].gid = i; |
---|
| 172 | core[i].lid = i; |
---|
| 173 | core[i].cxy = 0; |
---|
| 174 | } |
---|
[70] | 175 | } |
---|
| 176 | |
---|
[195] | 177 | static void init_bootinfo_ioc(boot_device_t *dev) |
---|
| 178 | { |
---|
| 179 | memset(dev, 0, sizeof(boot_device_t)); |
---|
| 180 | |
---|
| 181 | dev->base = 0; |
---|
| 182 | dev->type = (DEV_FUNC_IOC << 16) | IMPL_IOC_BDV; |
---|
| 183 | dev->channels = 1; |
---|
| 184 | } |
---|
| 185 | |
---|
[192] | 186 | static void init_bootinfo_pic(boot_device_t *dev) |
---|
[70] | 187 | { |
---|
| 188 | memset(dev, 0, sizeof(boot_device_t)); |
---|
| 189 | |
---|
[192] | 190 | dev->base = 0; |
---|
[252] | 191 | dev->type = (DEV_FUNC_PIC << 16) | IMPL_PIC_I86; |
---|
[70] | 192 | dev->channels = 1; |
---|
| 193 | dev->param0 = 0; |
---|
| 194 | dev->param1 = 0; |
---|
| 195 | dev->param2 = 0; |
---|
| 196 | dev->param3 = 0; |
---|
| 197 | |
---|
[202] | 198 | dev->irqs = 16; |
---|
[192] | 199 | |
---|
[202] | 200 | /* ATA */ |
---|
| 201 | dev->irq[IRQ_ATA0].dev_type = (DEV_FUNC_IOC << 16) | IMPL_IOC_BDV; |
---|
| 202 | dev->irq[IRQ_ATA0].channel = 0; |
---|
| 203 | dev->irq[IRQ_ATA0].is_rx = 0; |
---|
| 204 | dev->irq[IRQ_ATA0].valid = 1; |
---|
[70] | 205 | } |
---|
| 206 | |
---|
[192] | 207 | static void init_bootinfo_txt(boot_device_t *dev) |
---|
| 208 | { |
---|
| 209 | memset(dev, 0, sizeof(boot_device_t)); |
---|
| 210 | |
---|
| 211 | dev->base = 0; |
---|
[254] | 212 | dev->type = (DEV_FUNC_TXT << 16) | IMPL_TXT_RS2; |
---|
[255] | 213 | dev->channels = 4; |
---|
[192] | 214 | dev->param0 = 0; |
---|
| 215 | dev->param1 = 0; |
---|
| 216 | dev->param2 = 0; |
---|
| 217 | dev->param3 = 0; |
---|
| 218 | } |
---|
| 219 | |
---|
[70] | 220 | static void init_bootinfo(boot_info_t *info) |
---|
| 221 | { |
---|
[116] | 222 | size_t offset; |
---|
[114] | 223 | |
---|
[70] | 224 | extern uint64_t __kernel_data_start; |
---|
| 225 | extern uint64_t __kernel_end; |
---|
| 226 | |
---|
| 227 | memset(info, 0, sizeof(boot_info_t)); |
---|
| 228 | |
---|
| 229 | info->signature = 0; |
---|
| 230 | |
---|
| 231 | info->paddr_width = 0; |
---|
| 232 | info->x_width = 1; |
---|
| 233 | info->y_width = 1; |
---|
| 234 | info->x_size = 1; |
---|
| 235 | info->y_size = 1; |
---|
| 236 | info->io_cxy = 0; |
---|
| 237 | |
---|
[195] | 238 | info->ext_dev_nr = 3; |
---|
[70] | 239 | init_bootinfo_txt(&info->ext_dev[0]); |
---|
[192] | 240 | init_bootinfo_pic(&info->ext_dev[1]); |
---|
[195] | 241 | init_bootinfo_ioc(&info->ext_dev[2]); |
---|
[70] | 242 | |
---|
| 243 | info->cxy = 0; |
---|
[240] | 244 | info->cores_nr = ncpu; |
---|
| 245 | init_bootinfo_core((boot_core_t *)&info->core); |
---|
[70] | 246 | |
---|
[137] | 247 | info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd); |
---|
[70] | 248 | |
---|
[135] | 249 | /* TODO: dev_mmc */ |
---|
| 250 | /* TODO: dev_dma */ |
---|
| 251 | |
---|
[116] | 252 | offset = hal_gpt_bootstrap_uniformize(); |
---|
| 253 | info->pages_offset = offset / PAGE_SIZE; |
---|
[119] | 254 | info->pages_nr = init_bootinfo_pages_nr(); |
---|
[70] | 255 | |
---|
| 256 | info->kernel_code_start = (intptr_t)(KERNTEXTOFF - KERNBASE); |
---|
| 257 | info->kernel_code_end = (intptr_t)(&__kernel_data_start - KERNBASE) - 1; |
---|
| 258 | info->kernel_data_start = (intptr_t)(&__kernel_data_start - KERNBASE); |
---|
| 259 | info->kernel_code_end = (intptr_t)(&__kernel_end - KERNBASE) - 1; |
---|
| 260 | } |
---|
| 261 | |
---|
[166] | 262 | /* -------------------------------------------------------------------------- */ |
---|
| 263 | |
---|
[236] | 264 | static uint32_t cpuN_booted __in_kdata; |
---|
| 265 | |
---|
| 266 | void start_secondary_cpus() |
---|
| 267 | { |
---|
| 268 | pt_entry_t flags = PG_V | PG_KW; |
---|
| 269 | extern vaddr_t cpuN_boot_trampoline; |
---|
| 270 | extern vaddr_t cpuN_boot_trampoline_end; |
---|
| 271 | extern paddr_t smp_L4pa; |
---|
| 272 | extern vaddr_t smp_stkva; |
---|
| 273 | extern paddr_t L4paddr; |
---|
| 274 | size_t i, sz; |
---|
| 275 | |
---|
| 276 | smp_L4pa = L4paddr; |
---|
| 277 | |
---|
| 278 | /* map the SMP trampoline (identity) */ |
---|
| 279 | vaddr_t trampva = (vaddr_t)SMP_TRAMPOLINE_PA; |
---|
| 280 | hal_gpt_maptree_area(trampva, trampva + PAGE_SIZE); |
---|
| 281 | hal_gpt_enter(trampva, SMP_TRAMPOLINE_PA, flags); |
---|
| 282 | |
---|
| 283 | /* copy it */ |
---|
| 284 | sz = (size_t)&cpuN_boot_trampoline_end - (size_t)&cpuN_boot_trampoline; |
---|
| 285 | memcpy((void *)trampva, (void *)&cpuN_boot_trampoline, sz); |
---|
| 286 | |
---|
| 287 | for (i = 0; i < CONFIG_MAX_LOCAL_CORES; i++) { |
---|
| 288 | if (i == 0 || !cpudata[i].valid) { |
---|
| 289 | continue; |
---|
| 290 | } |
---|
| 291 | |
---|
| 292 | smp_stkva = (vaddr_t)cpudata[i].boot_stack + STKSIZE; |
---|
| 293 | |
---|
| 294 | cpuN_booted = 0; |
---|
| 295 | boot_cpuN(i, SMP_TRAMPOLINE_PA); |
---|
| 296 | while (!hal_atomic_cas(&cpuN_booted, 1, 0)) { |
---|
| 297 | /* wait */ |
---|
| 298 | } |
---|
| 299 | } |
---|
| 300 | |
---|
| 301 | // XXX: unmap the trampoline |
---|
| 302 | } |
---|
| 303 | |
---|
| 304 | void init_x86_64_cpuN() |
---|
| 305 | { |
---|
[240] | 306 | lid_t lid; |
---|
[237] | 307 | |
---|
[240] | 308 | cli(); |
---|
| 309 | |
---|
| 310 | lid = hal_lapic_gid(); |
---|
| 311 | |
---|
[237] | 312 | cpu_attach(lid); |
---|
| 313 | x86_printf("[cpu%z] cpu_attach called\n", (uint64_t)lid); |
---|
| 314 | |
---|
| 315 | cpu_tls_init(lid); |
---|
| 316 | x86_printf("[cpu%z] cput_tls_init called\n", (uint64_t)lid); |
---|
| 317 | |
---|
| 318 | cpu_lapic_init(); |
---|
| 319 | x86_printf("[cpu%z] cpu_lapic_init called\n", (uint64_t)lid); |
---|
| 320 | |
---|
[236] | 321 | cpuN_booted = 1; |
---|
[237] | 322 | |
---|
| 323 | if (lid == 1) { |
---|
| 324 | hal_ioapic_disable_irq(IRQ_KEYBOARD); |
---|
| 325 | hal_ioapic_bind_irq(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 1); |
---|
| 326 | hal_ioapic_enable_irq(IRQ_KEYBOARD); |
---|
| 327 | } |
---|
| 328 | |
---|
[240] | 329 | kernel_init(&btinfo); |
---|
| 330 | |
---|
| 331 | reg_t dummy; |
---|
| 332 | hal_enable_irq(&dummy); |
---|
| 333 | |
---|
[236] | 334 | while (1); |
---|
| 335 | } |
---|
| 336 | |
---|
| 337 | /* -------------------------------------------------------------------------- */ |
---|
| 338 | |
---|
[199] | 339 | static void apic_map() |
---|
| 340 | { |
---|
| 341 | extern vaddr_t lapic_va, ioapic_va; |
---|
| 342 | extern paddr_t lapic_pa, ioapic_pa; |
---|
| 343 | |
---|
| 344 | lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
---|
| 345 | hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
---|
| 346 | |
---|
| 347 | ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
---|
| 348 | hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
---|
| 349 | } |
---|
| 350 | |
---|
[29] | 351 | void init_x86_64(paddr_t firstpa) |
---|
| 352 | { |
---|
[240] | 353 | cli(); |
---|
[70] | 354 | |
---|
[154] | 355 | /* Initialize the serial port */ |
---|
| 356 | hal_com_init_early(); |
---|
| 357 | |
---|
[29] | 358 | x86_printf("[+] init_x86_64 called\n"); |
---|
| 359 | |
---|
| 360 | /* Create the global structures */ |
---|
| 361 | gdt_create(); |
---|
| 362 | idt_create(); |
---|
| 363 | |
---|
[166] | 364 | /* Identify the features of the cpu */ |
---|
| 365 | cpu_identify(); |
---|
| 366 | |
---|
[29] | 367 | /* Attach cpu0 */ |
---|
[162] | 368 | cpu_attach(0); |
---|
[29] | 369 | x86_printf("[+] cpu_attach called\n"); |
---|
| 370 | |
---|
[47] | 371 | x86_printf("[+] bootloader: '%s'\n", mb_loader_name); |
---|
[32] | 372 | |
---|
| 373 | dump_memmap(); |
---|
| 374 | x86_printf("[+] dump finished\n"); |
---|
| 375 | |
---|
[35] | 376 | hal_gpt_init(firstpa); |
---|
| 377 | x86_printf("[+] hal_gpt_init called\n"); |
---|
[29] | 378 | |
---|
[35] | 379 | hal_acpi_init(); |
---|
| 380 | x86_printf("[+] hal_acpi_init called\n"); |
---|
| 381 | |
---|
[45] | 382 | hal_gpt_bootstrap_reset(); |
---|
| 383 | x86_printf("[+] hal_gpt_bootstrap_reset called\n"); |
---|
| 384 | |
---|
[199] | 385 | apic_map(); |
---|
| 386 | x86_printf("[+] apic_map called\n"); |
---|
| 387 | |
---|
[82] | 388 | hal_apic_init(); |
---|
[237] | 389 | cpu_lapic_init(); |
---|
[82] | 390 | x86_printf("[+] hal_apic_init called\n"); |
---|
[45] | 391 | |
---|
[168] | 392 | cpu_tls_init(0); |
---|
| 393 | x86_printf("[+] cput_tls_init called\n"); |
---|
[46] | 394 | |
---|
[224] | 395 | mytest = 0; |
---|
[44] | 396 | x86_printf("-> mytest = %z\n", mytest); |
---|
[94] | 397 | void *hoho = &init_x86_64; |
---|
[74] | 398 | xptr_t myptr = XPTR(0, &mytest); |
---|
[35] | 399 | |
---|
[94] | 400 | hal_remote_spt(myptr, hoho); |
---|
| 401 | x86_printf("-> mytest = %Z\n", hal_remote_lpt(myptr)); |
---|
| 402 | |
---|
[99] | 403 | init_bootinfo(&btinfo); |
---|
[94] | 404 | |
---|
[236] | 405 | start_secondary_cpus(); |
---|
| 406 | |
---|
[70] | 407 | kernel_init(&btinfo); |
---|
[99] | 408 | |
---|
[70] | 409 | x86_printf("[+] kernel_init called\n"); |
---|
[240] | 410 | |
---|
| 411 | reg_t dummy; |
---|
| 412 | hal_enable_irq(&dummy); |
---|
[192] | 413 | /* |
---|
| 414 | void *ptr; |
---|
[70] | 415 | |
---|
[192] | 416 | khm_t *khm = &LOCAL_CLUSTER->khm; |
---|
| 417 | ptr = khm_alloc(khm, 10); |
---|
| 418 | memset(ptr, 0, 10); |
---|
| 419 | khm_free(ptr); |
---|
| 420 | |
---|
| 421 | |
---|
| 422 | kcm_t *kcm = &LOCAL_CLUSTER->kcm; |
---|
| 423 | ptr = kcm_alloc(kcm); |
---|
| 424 | memset(ptr, 0, 1); |
---|
| 425 | kcm_free(ptr); |
---|
| 426 | |
---|
| 427 | ptr = ppm_alloc_pages(1); |
---|
| 428 | ppm_free_pages(ptr); |
---|
| 429 | */ |
---|
[99] | 430 | while (1); |
---|
| 431 | |
---|
[82] | 432 | // void x86_stop(); |
---|
| 433 | // x86_stop(); |
---|
[29] | 434 | } |
---|
| 435 | |
---|
| 436 | /* -------------------------------------------------------------------------- */ |
---|
| 437 | |
---|
[235] | 438 | void cpu_activate(uint32_t gid) |
---|
| 439 | { |
---|
| 440 | cpudata[gid].valid = true; |
---|
| 441 | } |
---|
| 442 | |
---|
[29] | 443 | static void |
---|
| 444 | setregion(struct region_descriptor *rd, void *base, uint16_t limit) |
---|
| 445 | { |
---|
| 446 | rd->rd_limit = limit; |
---|
| 447 | rd->rd_base = (uint64_t)base; |
---|
| 448 | } |
---|
| 449 | |
---|
| 450 | /* -------------------------------------------------------------------------- */ |
---|
| 451 | |
---|
| 452 | static void |
---|
| 453 | gdt_set_memseg(struct gdt_memseg *sd, void *base, size_t limit, |
---|
| 454 | int type, int dpl, int gran, int is64) |
---|
| 455 | { |
---|
| 456 | sd->sd_lolimit = (unsigned)limit; |
---|
| 457 | sd->sd_lobase = (unsigned long)base; |
---|
| 458 | sd->sd_type = type; |
---|
| 459 | sd->sd_dpl = dpl; |
---|
| 460 | sd->sd_p = 1; |
---|
| 461 | sd->sd_hilimit = (unsigned)limit >> 16; |
---|
| 462 | sd->sd_avl = 0; |
---|
| 463 | sd->sd_long = is64; |
---|
| 464 | sd->sd_def32 = 0; |
---|
| 465 | sd->sd_gran = gran; |
---|
| 466 | sd->sd_hibase = (unsigned long)base >> 24; |
---|
| 467 | } |
---|
| 468 | |
---|
| 469 | static void |
---|
| 470 | gdt_set_sysseg(struct gdt_sysseg *sd, void *base, size_t limit, |
---|
| 471 | int type, int dpl, int gran) |
---|
| 472 | { |
---|
| 473 | memset(sd, 0, sizeof *sd); |
---|
| 474 | sd->sd_lolimit = (unsigned)limit; |
---|
| 475 | sd->sd_lobase = (uint64_t)base; |
---|
| 476 | sd->sd_type = type; |
---|
| 477 | sd->sd_dpl = dpl; |
---|
| 478 | sd->sd_p = 1; |
---|
| 479 | sd->sd_hilimit = (unsigned)limit >> 16; |
---|
| 480 | sd->sd_gran = gran; |
---|
| 481 | sd->sd_hibase = (uint64_t)base >> 24; |
---|
| 482 | } |
---|
| 483 | |
---|
| 484 | static void gdt_create() |
---|
| 485 | { |
---|
| 486 | memset(&gdtstore, 0, PAGE_SIZE); |
---|
| 487 | |
---|
| 488 | /* Flat segments */ |
---|
| 489 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KCODE_SEL), 0, |
---|
| 490 | 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1); |
---|
| 491 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KDATA_SEL), 0, |
---|
| 492 | 0xfffff, SDT_MEMRWA, SEL_KPL, 1, 1); |
---|
| 493 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE_SEL), 0, |
---|
| 494 | 0xfffff, SDT_MEMERA, SEL_UPL, 1, 1); |
---|
| 495 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UDATA_SEL), 0, |
---|
| 496 | 0xfffff, SDT_MEMRWA, SEL_UPL, 1, 1); |
---|
| 497 | } |
---|
| 498 | |
---|
| 499 | void cpu_load_gdt() |
---|
| 500 | { |
---|
| 501 | struct region_descriptor region; |
---|
| 502 | setregion(®ion, &gdtstore, PAGE_SIZE - 1); |
---|
| 503 | lgdt(®ion); |
---|
| 504 | } |
---|
| 505 | |
---|
| 506 | /* -------------------------------------------------------------------------- */ |
---|
| 507 | |
---|
[203] | 508 | struct { |
---|
| 509 | bool_t busy[256]; |
---|
| 510 | } idt_bitmap __in_kdata; |
---|
| 511 | |
---|
| 512 | int idt_slot_alloc() |
---|
| 513 | { |
---|
| 514 | size_t i; |
---|
| 515 | |
---|
| 516 | for (i = 0; i < 256; i++) { |
---|
| 517 | if (!idt_bitmap.busy[i]) |
---|
| 518 | break; |
---|
| 519 | } |
---|
| 520 | if (i == 256) { |
---|
| 521 | return -1; |
---|
| 522 | } |
---|
| 523 | |
---|
| 524 | idt_bitmap.busy[i] = true; |
---|
| 525 | return (int)i; |
---|
| 526 | } |
---|
| 527 | |
---|
| 528 | void idt_slot_free(int slot) |
---|
| 529 | { |
---|
| 530 | idt_bitmap.busy[slot] = false; |
---|
| 531 | } |
---|
| 532 | |
---|
[29] | 533 | static void |
---|
| 534 | idt_set_seg(struct idt_seg *seg, void *func, int ist, int type, int dpl, int sel) |
---|
| 535 | { |
---|
| 536 | seg->gd_looffset = (uint64_t)func & 0xffff; |
---|
| 537 | seg->gd_selector = sel; |
---|
| 538 | seg->gd_ist = ist; |
---|
| 539 | seg->gd_type = type; |
---|
| 540 | seg->gd_dpl = dpl; |
---|
| 541 | seg->gd_p = 1; |
---|
| 542 | seg->gd_hioffset = (uint64_t)func >> 16; |
---|
| 543 | seg->gd_zero = 0; |
---|
| 544 | seg->gd_xx1 = 0; |
---|
| 545 | seg->gd_xx2 = 0; |
---|
| 546 | seg->gd_xx3 = 0; |
---|
| 547 | } |
---|
| 548 | |
---|
| 549 | static void idt_create() |
---|
| 550 | { |
---|
[80] | 551 | extern uint64_t x86_traps[], x86_intrs[], x86_rsvd; |
---|
[29] | 552 | struct idt_seg *idt; |
---|
| 553 | size_t i; |
---|
| 554 | |
---|
[203] | 555 | memset(&idt_bitmap, 0, sizeof(idt_bitmap)); |
---|
[29] | 556 | idt = (struct idt_seg *)&idtstore; |
---|
[45] | 557 | |
---|
[80] | 558 | /* First, put a dead entry */ |
---|
| 559 | for (i = 0; i < NIDT; i++) { |
---|
| 560 | idt_set_seg(&idt[i], (void *)&x86_rsvd, 0, |
---|
| 561 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
| 562 | } |
---|
| 563 | |
---|
[45] | 564 | /* General exceptions */ |
---|
| 565 | for (i = CPUVEC_MIN; i < CPUVEC_MAX; i++) { |
---|
| 566 | idt_set_seg(&idt[i], (void *)x86_traps[i - CPUVEC_MIN], 0, |
---|
| 567 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
[203] | 568 | idt_bitmap.busy[i] = true; |
---|
[29] | 569 | } |
---|
[45] | 570 | |
---|
[138] | 571 | /* Dynamically configured interrupts */ |
---|
| 572 | for (i = DYNVEC_MIN; i < DYNVEC_MAX; i++) { |
---|
| 573 | idt_set_seg(&idt[i], (void *)x86_intrs[i - DYNVEC_MIN], 0, |
---|
[45] | 574 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
[203] | 575 | idt_bitmap.busy[i] = true; |
---|
[45] | 576 | } |
---|
[29] | 577 | } |
---|
| 578 | |
---|
| 579 | void cpu_load_idt() |
---|
| 580 | { |
---|
| 581 | struct region_descriptor region; |
---|
| 582 | setregion(®ion, &idtstore, PAGE_SIZE - 1); |
---|
| 583 | lidt(®ion); |
---|
| 584 | } |
---|
| 585 | |
---|
| 586 | /* -------------------------------------------------------------------------- */ |
---|
| 587 | |
---|
[164] | 588 | int tss_alloc(struct tss *tss, size_t lid) |
---|
[29] | 589 | { |
---|
| 590 | int slot; |
---|
| 591 | |
---|
[164] | 592 | slot = GDT_CPUTSS_SEL + lid; |
---|
[29] | 593 | |
---|
| 594 | gdt_set_sysseg(GDT_ADDR_SYS(gdtstore, slot), tss, |
---|
| 595 | sizeof(*tss) - 1, SDT_SYS386TSS, SEL_KPL, 0); |
---|
| 596 | |
---|
| 597 | return GDT_DYNAM_SEL(slot, SEL_KPL); |
---|
| 598 | } |
---|
| 599 | |
---|
[162] | 600 | void cpu_create_tss(size_t lid) |
---|
[29] | 601 | { |
---|
[165] | 602 | percpu_archdata_t *data = &cpudata[lid]; |
---|
| 603 | struct tss *tss = &data->tss; |
---|
[29] | 604 | int sel; |
---|
| 605 | |
---|
| 606 | /* Create the tss */ |
---|
| 607 | memset(tss, 0, sizeof(*tss)); |
---|
[162] | 608 | |
---|
| 609 | /* tss->tss_rsp0 */ |
---|
[165] | 610 | tss->tss_ist[0] = (uint64_t)data->intr_stack[lid] + STKSIZE; |
---|
| 611 | tss->tss_ist[1] = (uint64_t)data->dbfl_stack[lid] + STKSIZE; |
---|
| 612 | tss->tss_ist[2] = (uint64_t)data->nmfl_stack[lid] + STKSIZE; |
---|
[29] | 613 | tss->tss_iobase = IOMAP_INVALOFF << 16; |
---|
[164] | 614 | sel = tss_alloc(tss, lid); |
---|
[29] | 615 | |
---|
| 616 | /* Load it */ |
---|
| 617 | ltr(sel); |
---|
| 618 | } |
---|
| 619 | |
---|
| 620 | /* -------------------------------------------------------------------------- */ |
---|
| 621 | |
---|
[168] | 622 | void cpu_tls_init(size_t lid) |
---|
| 623 | { |
---|
| 624 | percpu_archdata_t *data = &cpudata[lid]; |
---|
| 625 | tls_t *cputls = &data->tls; |
---|
| 626 | |
---|
| 627 | memset(cputls, 0, sizeof(tls_t)); |
---|
| 628 | |
---|
| 629 | cputls->tls_self = cputls; |
---|
| 630 | cputls->tls_gid = hal_lapic_gid(); |
---|
| 631 | cputls->tls_lid = lid; |
---|
[240] | 632 | cputls->tls_intr = INTRS_DISABLED; |
---|
[168] | 633 | |
---|
| 634 | wrmsr(MSR_FSBASE, 0); |
---|
| 635 | wrmsr(MSR_GSBASE, (uint64_t)cputls); |
---|
| 636 | wrmsr(MSR_KERNELGSBASE, 0); |
---|
| 637 | } |
---|
| 638 | |
---|
| 639 | /* -------------------------------------------------------------------------- */ |
---|
| 640 | |
---|
[166] | 641 | uint64_t cpu_features[4] __in_kdata; |
---|
| 642 | |
---|
| 643 | void cpu_identify() |
---|
| 644 | { |
---|
| 645 | /* |
---|
| 646 | * desc[0] = eax |
---|
| 647 | * desc[1] = ebx |
---|
| 648 | * desc[2] = ecx |
---|
| 649 | * desc[3] = edx |
---|
| 650 | */ |
---|
| 651 | uint32_t desc[4]; |
---|
| 652 | char vendor[13]; |
---|
| 653 | size_t lvl; |
---|
| 654 | |
---|
| 655 | /* |
---|
| 656 | * Get information from the standard cpuid leafs |
---|
| 657 | */ |
---|
| 658 | cpuid(0, 0, (uint32_t *)&desc); |
---|
| 659 | |
---|
| 660 | lvl = (uint64_t)desc[0]; |
---|
| 661 | x86_printf("-> cpuid standard level: %z\n", lvl); |
---|
| 662 | |
---|
| 663 | memcpy(vendor + 0, &desc[1], sizeof(uint32_t)); |
---|
| 664 | memcpy(vendor + 8, &desc[2], sizeof(uint32_t)); |
---|
| 665 | memcpy(vendor + 4, &desc[3], sizeof(uint32_t)); |
---|
| 666 | vendor[12] = '\0'; |
---|
| 667 | x86_printf("-> CPU vendor: '%s'\n", vendor); |
---|
| 668 | |
---|
| 669 | if (lvl >= 1) { |
---|
| 670 | cpuid(1, 0, (uint32_t *)&desc); |
---|
| 671 | cpu_features[0] = desc[3]; |
---|
| 672 | cpu_features[1] = desc[2]; |
---|
| 673 | } |
---|
| 674 | |
---|
| 675 | /* |
---|
| 676 | * Get information from the extended cpuid leafs |
---|
| 677 | */ |
---|
| 678 | cpuid(0x80000000, 0, desc); |
---|
| 679 | |
---|
| 680 | lvl = (uint64_t)desc[0]; |
---|
| 681 | x86_printf("-> cpuid extended level: %Z\n", lvl); |
---|
| 682 | } |
---|
| 683 | |
---|
| 684 | /* -------------------------------------------------------------------------- */ |
---|
| 685 | |
---|
[162] | 686 | void cpu_attach(size_t lid) |
---|
[29] | 687 | { |
---|
[168] | 688 | /* Per-cluster structures */ |
---|
[29] | 689 | cpu_load_gdt(); |
---|
| 690 | cpu_load_idt(); |
---|
[168] | 691 | |
---|
| 692 | /* Per-cpu structures */ |
---|
[162] | 693 | cpu_create_tss(lid); |
---|
[166] | 694 | |
---|
| 695 | if (cpu_features[0] & CPUID_PSE) { |
---|
| 696 | lcr4(rcr4() | CR4_PSE); |
---|
| 697 | tlbflushg(); |
---|
| 698 | } else { |
---|
| 699 | /* |
---|
| 700 | * amd64 supports PSE by default, if it's not here we have a |
---|
| 701 | * problem |
---|
| 702 | */ |
---|
| 703 | x86_panic("PSE not supported"); |
---|
| 704 | } |
---|
[29] | 705 | } |
---|
| 706 | |
---|