[29] | 1 | /* |
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| 2 | * hal_init.c - C initialization procedure for x86. |
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| 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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[234] | 18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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[29] | 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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| 22 | #include <hal_types.h> |
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| 23 | #include <hal_boot.h> |
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[32] | 24 | #include <hal_multiboot.h> |
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[29] | 25 | #include <hal_segmentation.h> |
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[45] | 26 | #include <hal_acpi.h> |
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[82] | 27 | #include <hal_apic.h> |
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[308] | 28 | #include <hal_kentry.h> |
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[35] | 29 | #include <hal_internal.h> |
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[166] | 30 | #include <hal_register.h> |
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| 31 | |
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[72] | 32 | #include <hal_remote.h> |
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[99] | 33 | #include <hal_irqmask.h> |
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[29] | 34 | |
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| 35 | #include <memcpy.h> |
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| 36 | #include <thread.h> |
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| 37 | #include <string.h> |
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| 38 | #include <process.h> |
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| 39 | #include <printk.h> |
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| 40 | #include <vmm.h> |
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| 41 | #include <core.h> |
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| 42 | #include <cluster.h> |
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[70] | 43 | #include <chdev.h> |
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[29] | 44 | |
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[70] | 45 | #include <boot_info.h> |
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| 46 | |
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[81] | 47 | void kernel_init(boot_info_t *info); |
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| 48 | |
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[29] | 49 | static void gdt_create(); |
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| 50 | static void idt_create(); |
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[168] | 51 | void cpu_tls_init(size_t lid); |
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[166] | 52 | void cpu_identify(); |
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[237] | 53 | void cpu_attach(size_t lid); |
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[29] | 54 | |
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[44] | 55 | size_t mytest __in_kdata = 0; |
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[32] | 56 | |
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| 57 | struct multiboot_info mb_info __in_kdata; |
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| 58 | char mb_loader_name[PAGE_SIZE] __in_kdata; |
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| 59 | uint8_t mb_mmap[PAGE_SIZE] __in_kdata; |
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| 60 | |
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[240] | 61 | size_t ncpu __in_kdata = 0; |
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| 62 | static boot_info_t btinfo __in_kdata; |
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| 63 | |
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[236] | 64 | /* x86-specific per-cluster structures */ |
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| 65 | uint8_t gdtstore[PAGE_SIZE] __in_kdata; |
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| 66 | uint8_t idtstore[PAGE_SIZE] __in_kdata; |
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| 67 | |
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| 68 | /* x86-specific per-cpu structures */ |
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| 69 | typedef struct { |
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| 70 | bool_t valid; |
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| 71 | struct tss tss; |
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| 72 | struct tls tls; |
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| 73 | uint8_t boot_stack[STKSIZE]; |
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| 74 | uint8_t intr_stack[STKSIZE]; |
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| 75 | uint8_t dbfl_stack[STKSIZE]; |
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| 76 | uint8_t nmfl_stack[STKSIZE]; |
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| 77 | } percpu_archdata_t; |
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| 78 | percpu_archdata_t cpudata[CONFIG_MAX_LOCAL_CORES] __in_kdata; |
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| 79 | |
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[29] | 80 | /* -------------------------------------------------------------------------- */ |
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| 81 | |
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[32] | 82 | static void |
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| 83 | dump_memmap() |
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| 84 | { |
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| 85 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 86 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 87 | size_t i; |
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| 88 | |
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| 89 | if (!(mb_info.mi_flags & MULTIBOOT_INFO_HAS_MMAP)) |
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[46] | 90 | x86_panic("No mmap"); |
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[32] | 91 | |
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| 92 | i = 0; |
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| 93 | while (i < mmap_length) { |
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| 94 | struct multiboot_mmap *mm; |
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| 95 | |
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| 96 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 97 | |
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| 98 | x86_printf("-> [%Z, %Z] %s\n", mm->mm_base_addr, |
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| 99 | mm->mm_base_addr + mm->mm_length, |
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| 100 | (mm->mm_type == 1) ? "ram" : "rsv" ); |
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| 101 | |
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| 102 | i += mm->mm_size + 4; |
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| 103 | } |
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| 104 | } |
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| 105 | |
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[135] | 106 | /* -------------------------------------------------------------------------- */ |
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| 107 | |
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[119] | 108 | static size_t init_bootinfo_pages_nr() |
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| 109 | { |
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| 110 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 111 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 112 | paddr_t maxpa, pa; |
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| 113 | size_t i; |
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| 114 | |
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| 115 | i = 0; |
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| 116 | maxpa = 0; |
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| 117 | while (i < mmap_length) { |
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| 118 | struct multiboot_mmap *mm; |
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| 119 | |
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| 120 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 121 | |
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| 122 | if (mm->mm_type == 1) { |
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| 123 | pa = mm->mm_base_addr + mm->mm_length; |
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| 124 | if (pa > maxpa) |
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| 125 | maxpa = pa; |
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| 126 | } |
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| 127 | |
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| 128 | i += mm->mm_size + 4; |
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| 129 | } |
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| 130 | |
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| 131 | return (maxpa / PAGE_SIZE); |
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| 132 | } |
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| 133 | |
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[116] | 134 | static size_t init_bootinfo_rsvd(boot_rsvd_t *rsvd) |
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| 135 | { |
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| 136 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 137 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 138 | size_t i, rsvd_nr; |
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| 139 | |
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[137] | 140 | memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD); |
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[116] | 141 | |
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| 142 | i = 0, rsvd_nr = 0; |
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| 143 | while (i < mmap_length) { |
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| 144 | struct multiboot_mmap *mm; |
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| 145 | |
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| 146 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 147 | |
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[119] | 148 | if (mm->mm_type != 1) { |
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| 149 | rsvd[rsvd_nr].first_page = |
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| 150 | rounddown(mm->mm_base_addr, PAGE_SIZE) / PAGE_SIZE; |
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| 151 | rsvd[rsvd_nr].npages = |
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| 152 | roundup(mm->mm_length, PAGE_SIZE) / PAGE_SIZE; |
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| 153 | rsvd_nr++; |
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| 154 | if (rsvd_nr == CONFIG_PPM_MAX_RSVD) |
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| 155 | x86_panic("too many memory holes"); |
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| 156 | } |
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[116] | 157 | |
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| 158 | i += mm->mm_size + 4; |
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| 159 | } |
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| 160 | |
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| 161 | return rsvd_nr; |
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| 162 | } |
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| 163 | |
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[70] | 164 | static void init_bootinfo_core(boot_core_t *core) |
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| 165 | { |
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[240] | 166 | size_t i; |
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[70] | 167 | |
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[240] | 168 | // XXX: not necessarily contiguous |
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| 169 | for (i = 0; i < ncpu; i++) { |
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| 170 | memset(&core[i], 0, sizeof(boot_core_t)); |
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| 171 | |
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| 172 | core[i].gid = i; |
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| 173 | core[i].lid = i; |
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| 174 | core[i].cxy = 0; |
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| 175 | } |
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[70] | 176 | } |
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| 177 | |
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[195] | 178 | static void init_bootinfo_ioc(boot_device_t *dev) |
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| 179 | { |
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| 180 | memset(dev, 0, sizeof(boot_device_t)); |
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| 181 | |
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| 182 | dev->base = 0; |
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| 183 | dev->type = (DEV_FUNC_IOC << 16) | IMPL_IOC_BDV; |
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| 184 | dev->channels = 1; |
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| 185 | } |
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| 186 | |
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[192] | 187 | static void init_bootinfo_pic(boot_device_t *dev) |
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[70] | 188 | { |
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| 189 | memset(dev, 0, sizeof(boot_device_t)); |
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| 190 | |
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[192] | 191 | dev->base = 0; |
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[252] | 192 | dev->type = (DEV_FUNC_PIC << 16) | IMPL_PIC_I86; |
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[70] | 193 | dev->channels = 1; |
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| 194 | dev->param0 = 0; |
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| 195 | dev->param1 = 0; |
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| 196 | dev->param2 = 0; |
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| 197 | dev->param3 = 0; |
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| 198 | |
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[202] | 199 | dev->irqs = 16; |
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[192] | 200 | |
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[202] | 201 | /* ATA */ |
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| 202 | dev->irq[IRQ_ATA0].dev_type = (DEV_FUNC_IOC << 16) | IMPL_IOC_BDV; |
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| 203 | dev->irq[IRQ_ATA0].channel = 0; |
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| 204 | dev->irq[IRQ_ATA0].is_rx = 0; |
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| 205 | dev->irq[IRQ_ATA0].valid = 1; |
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[70] | 206 | } |
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| 207 | |
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[192] | 208 | static void init_bootinfo_txt(boot_device_t *dev) |
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| 209 | { |
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| 210 | memset(dev, 0, sizeof(boot_device_t)); |
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| 211 | |
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| 212 | dev->base = 0; |
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[254] | 213 | dev->type = (DEV_FUNC_TXT << 16) | IMPL_TXT_RS2; |
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[255] | 214 | dev->channels = 4; |
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[192] | 215 | dev->param0 = 0; |
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| 216 | dev->param1 = 0; |
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| 217 | dev->param2 = 0; |
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| 218 | dev->param3 = 0; |
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| 219 | } |
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| 220 | |
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[70] | 221 | static void init_bootinfo(boot_info_t *info) |
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| 222 | { |
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[116] | 223 | size_t offset; |
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[114] | 224 | |
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[70] | 225 | memset(info, 0, sizeof(boot_info_t)); |
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| 226 | |
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| 227 | info->signature = 0; |
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| 228 | |
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| 229 | info->paddr_width = 0; |
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| 230 | info->x_width = 1; |
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| 231 | info->y_width = 1; |
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| 232 | info->x_size = 1; |
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| 233 | info->y_size = 1; |
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| 234 | info->io_cxy = 0; |
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| 235 | |
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[195] | 236 | info->ext_dev_nr = 3; |
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[70] | 237 | init_bootinfo_txt(&info->ext_dev[0]); |
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[192] | 238 | init_bootinfo_pic(&info->ext_dev[1]); |
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[195] | 239 | init_bootinfo_ioc(&info->ext_dev[2]); |
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[70] | 240 | |
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| 241 | info->cxy = 0; |
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[240] | 242 | info->cores_nr = ncpu; |
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| 243 | init_bootinfo_core((boot_core_t *)&info->core); |
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[70] | 244 | |
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[137] | 245 | info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd); |
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[70] | 246 | |
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[135] | 247 | /* TODO: dev_mmc */ |
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| 248 | /* TODO: dev_dma */ |
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| 249 | |
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[116] | 250 | offset = hal_gpt_bootstrap_uniformize(); |
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| 251 | info->pages_offset = offset / PAGE_SIZE; |
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[119] | 252 | info->pages_nr = init_bootinfo_pages_nr(); |
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[70] | 253 | } |
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| 254 | |
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[166] | 255 | /* -------------------------------------------------------------------------- */ |
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| 256 | |
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[236] | 257 | static uint32_t cpuN_booted __in_kdata; |
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| 258 | |
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| 259 | void start_secondary_cpus() |
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| 260 | { |
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| 261 | pt_entry_t flags = PG_V | PG_KW; |
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| 262 | extern vaddr_t cpuN_boot_trampoline; |
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| 263 | extern vaddr_t cpuN_boot_trampoline_end; |
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| 264 | extern paddr_t smp_L4pa; |
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| 265 | extern vaddr_t smp_stkva; |
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| 266 | extern paddr_t L4paddr; |
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| 267 | size_t i, sz; |
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| 268 | |
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| 269 | smp_L4pa = L4paddr; |
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| 270 | |
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| 271 | /* map the SMP trampoline (identity) */ |
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| 272 | vaddr_t trampva = (vaddr_t)SMP_TRAMPOLINE_PA; |
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| 273 | hal_gpt_maptree_area(trampva, trampva + PAGE_SIZE); |
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| 274 | hal_gpt_enter(trampva, SMP_TRAMPOLINE_PA, flags); |
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| 275 | |
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| 276 | /* copy it */ |
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| 277 | sz = (size_t)&cpuN_boot_trampoline_end - (size_t)&cpuN_boot_trampoline; |
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| 278 | memcpy((void *)trampva, (void *)&cpuN_boot_trampoline, sz); |
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| 279 | |
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| 280 | for (i = 0; i < CONFIG_MAX_LOCAL_CORES; i++) { |
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| 281 | if (i == 0 || !cpudata[i].valid) { |
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| 282 | continue; |
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| 283 | } |
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| 284 | |
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[283] | 285 | smp_stkva = ((vaddr_t)&cpudata[i].boot_stack + STKSIZE) & ~0xF; |
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[236] | 286 | |
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| 287 | cpuN_booted = 0; |
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| 288 | boot_cpuN(i, SMP_TRAMPOLINE_PA); |
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| 289 | while (!hal_atomic_cas(&cpuN_booted, 1, 0)) { |
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| 290 | /* wait */ |
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| 291 | } |
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| 292 | } |
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| 293 | |
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| 294 | // XXX: unmap the trampoline |
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| 295 | } |
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| 296 | |
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| 297 | void init_x86_64_cpuN() |
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| 298 | { |
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[240] | 299 | lid_t lid; |
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[237] | 300 | |
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[240] | 301 | cli(); |
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| 302 | |
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| 303 | lid = hal_lapic_gid(); |
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| 304 | |
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[237] | 305 | cpu_attach(lid); |
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| 306 | x86_printf("[cpu%z] cpu_attach called\n", (uint64_t)lid); |
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| 307 | |
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| 308 | cpu_tls_init(lid); |
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| 309 | x86_printf("[cpu%z] cput_tls_init called\n", (uint64_t)lid); |
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| 310 | |
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| 311 | cpu_lapic_init(); |
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| 312 | x86_printf("[cpu%z] cpu_lapic_init called\n", (uint64_t)lid); |
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| 313 | |
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[236] | 314 | cpuN_booted = 1; |
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[237] | 315 | |
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| 316 | if (lid == 1) { |
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| 317 | hal_ioapic_disable_irq(IRQ_KEYBOARD); |
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| 318 | hal_ioapic_bind_irq(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 1); |
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| 319 | hal_ioapic_enable_irq(IRQ_KEYBOARD); |
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| 320 | } |
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| 321 | |
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[240] | 322 | kernel_init(&btinfo); |
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| 323 | |
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| 324 | reg_t dummy; |
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| 325 | hal_enable_irq(&dummy); |
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| 326 | |
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[236] | 327 | while (1); |
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| 328 | } |
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| 329 | |
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| 330 | /* -------------------------------------------------------------------------- */ |
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| 331 | |
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[199] | 332 | static void apic_map() |
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| 333 | { |
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| 334 | extern vaddr_t lapic_va, ioapic_va; |
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| 335 | extern paddr_t lapic_pa, ioapic_pa; |
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| 336 | |
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| 337 | lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 338 | hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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| 339 | |
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| 340 | ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 341 | hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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| 342 | } |
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| 343 | |
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[29] | 344 | void init_x86_64(paddr_t firstpa) |
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| 345 | { |
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[240] | 346 | cli(); |
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[70] | 347 | |
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[154] | 348 | /* Initialize the serial port */ |
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| 349 | hal_com_init_early(); |
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| 350 | |
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[29] | 351 | x86_printf("[+] init_x86_64 called\n"); |
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| 352 | |
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| 353 | /* Create the global structures */ |
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| 354 | gdt_create(); |
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| 355 | idt_create(); |
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| 356 | |
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[166] | 357 | /* Identify the features of the cpu */ |
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| 358 | cpu_identify(); |
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| 359 | |
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[29] | 360 | /* Attach cpu0 */ |
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[162] | 361 | cpu_attach(0); |
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[29] | 362 | x86_printf("[+] cpu_attach called\n"); |
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| 363 | |
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[47] | 364 | x86_printf("[+] bootloader: '%s'\n", mb_loader_name); |
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[32] | 365 | |
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| 366 | dump_memmap(); |
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| 367 | x86_printf("[+] dump finished\n"); |
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| 368 | |
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[35] | 369 | hal_gpt_init(firstpa); |
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| 370 | x86_printf("[+] hal_gpt_init called\n"); |
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[29] | 371 | |
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[35] | 372 | hal_acpi_init(); |
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| 373 | x86_printf("[+] hal_acpi_init called\n"); |
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| 374 | |
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[45] | 375 | hal_gpt_bootstrap_reset(); |
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| 376 | x86_printf("[+] hal_gpt_bootstrap_reset called\n"); |
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| 377 | |
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[199] | 378 | apic_map(); |
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| 379 | x86_printf("[+] apic_map called\n"); |
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| 380 | |
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[82] | 381 | hal_apic_init(); |
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[237] | 382 | cpu_lapic_init(); |
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[82] | 383 | x86_printf("[+] hal_apic_init called\n"); |
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[45] | 384 | |
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[168] | 385 | cpu_tls_init(0); |
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| 386 | x86_printf("[+] cput_tls_init called\n"); |
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[46] | 387 | |
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[224] | 388 | mytest = 0; |
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[44] | 389 | x86_printf("-> mytest = %z\n", mytest); |
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[94] | 390 | void *hoho = &init_x86_64; |
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[74] | 391 | xptr_t myptr = XPTR(0, &mytest); |
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[35] | 392 | |
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[94] | 393 | hal_remote_spt(myptr, hoho); |
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| 394 | x86_printf("-> mytest = %Z\n", hal_remote_lpt(myptr)); |
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| 395 | |
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[99] | 396 | init_bootinfo(&btinfo); |
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[94] | 397 | |
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[236] | 398 | start_secondary_cpus(); |
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| 399 | |
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[276] | 400 | kernel_init(&btinfo); |
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| 401 | |
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| 402 | x86_printf("[+] kernel_init called\n"); |
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| 403 | |
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[274] | 404 | reg_t dummy; |
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| 405 | hal_enable_irq(&dummy); |
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| 406 | |
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| 407 | while (1); |
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| 408 | |
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[192] | 409 | /* |
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| 410 | void *ptr; |
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[70] | 411 | |
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[192] | 412 | khm_t *khm = &LOCAL_CLUSTER->khm; |
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| 413 | ptr = khm_alloc(khm, 10); |
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| 414 | memset(ptr, 0, 10); |
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| 415 | khm_free(ptr); |
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| 416 | |
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| 417 | |
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| 418 | kcm_t *kcm = &LOCAL_CLUSTER->kcm; |
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| 419 | ptr = kcm_alloc(kcm); |
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| 420 | memset(ptr, 0, 1); |
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| 421 | kcm_free(ptr); |
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| 422 | |
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| 423 | ptr = ppm_alloc_pages(1); |
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| 424 | ppm_free_pages(ptr); |
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| 425 | */ |
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[99] | 426 | |
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[274] | 427 | |
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[82] | 428 | // void x86_stop(); |
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| 429 | // x86_stop(); |
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[29] | 430 | } |
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| 431 | |
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| 432 | /* -------------------------------------------------------------------------- */ |
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| 433 | |
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[235] | 434 | void cpu_activate(uint32_t gid) |
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| 435 | { |
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| 436 | cpudata[gid].valid = true; |
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| 437 | } |
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| 438 | |
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[29] | 439 | static void |
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| 440 | setregion(struct region_descriptor *rd, void *base, uint16_t limit) |
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| 441 | { |
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| 442 | rd->rd_limit = limit; |
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| 443 | rd->rd_base = (uint64_t)base; |
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| 444 | } |
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| 445 | |
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| 446 | /* -------------------------------------------------------------------------- */ |
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| 447 | |
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| 448 | static void |
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| 449 | gdt_set_memseg(struct gdt_memseg *sd, void *base, size_t limit, |
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[308] | 450 | int type, int dpl, int gran, bool_t is64) |
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[29] | 451 | { |
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| 452 | sd->sd_lolimit = (unsigned)limit; |
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| 453 | sd->sd_lobase = (unsigned long)base; |
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| 454 | sd->sd_type = type; |
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| 455 | sd->sd_dpl = dpl; |
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| 456 | sd->sd_p = 1; |
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| 457 | sd->sd_hilimit = (unsigned)limit >> 16; |
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| 458 | sd->sd_avl = 0; |
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| 459 | sd->sd_long = is64; |
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[308] | 460 | sd->sd_def32 = !is64; |
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[29] | 461 | sd->sd_gran = gran; |
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| 462 | sd->sd_hibase = (unsigned long)base >> 24; |
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| 463 | } |
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| 464 | |
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| 465 | static void |
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| 466 | gdt_set_sysseg(struct gdt_sysseg *sd, void *base, size_t limit, |
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| 467 | int type, int dpl, int gran) |
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| 468 | { |
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| 469 | memset(sd, 0, sizeof *sd); |
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| 470 | sd->sd_lolimit = (unsigned)limit; |
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| 471 | sd->sd_lobase = (uint64_t)base; |
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| 472 | sd->sd_type = type; |
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| 473 | sd->sd_dpl = dpl; |
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| 474 | sd->sd_p = 1; |
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| 475 | sd->sd_hilimit = (unsigned)limit >> 16; |
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| 476 | sd->sd_gran = gran; |
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| 477 | sd->sd_hibase = (uint64_t)base >> 24; |
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| 478 | } |
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| 479 | |
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| 480 | static void gdt_create() |
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| 481 | { |
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| 482 | memset(&gdtstore, 0, PAGE_SIZE); |
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| 483 | |
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| 484 | /* Flat segments */ |
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| 485 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KCODE_SEL), 0, |
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[308] | 486 | 0xfffff, SDT_MEMERA, SEL_KPL, 1, true); |
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[29] | 487 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KDATA_SEL), 0, |
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[308] | 488 | 0xfffff, SDT_MEMRWA, SEL_KPL, 1, true); |
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| 489 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE32_SEL), 0, |
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| 490 | 0xfffff, SDT_MEMERA, SEL_UPL, 1, false); |
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[29] | 491 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE_SEL), 0, |
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[308] | 492 | 0xfffff, SDT_MEMERA, SEL_UPL, 1, true); |
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[29] | 493 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UDATA_SEL), 0, |
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[308] | 494 | 0xfffff, SDT_MEMRWA, SEL_UPL, 1, true); |
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[29] | 495 | } |
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| 496 | |
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| 497 | void cpu_load_gdt() |
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| 498 | { |
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| 499 | struct region_descriptor region; |
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| 500 | setregion(®ion, &gdtstore, PAGE_SIZE - 1); |
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| 501 | lgdt(®ion); |
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| 502 | } |
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| 503 | |
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| 504 | /* -------------------------------------------------------------------------- */ |
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| 505 | |
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[203] | 506 | struct { |
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| 507 | bool_t busy[256]; |
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| 508 | } idt_bitmap __in_kdata; |
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| 509 | |
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| 510 | int idt_slot_alloc() |
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| 511 | { |
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| 512 | size_t i; |
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| 513 | |
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| 514 | for (i = 0; i < 256; i++) { |
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| 515 | if (!idt_bitmap.busy[i]) |
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| 516 | break; |
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| 517 | } |
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| 518 | if (i == 256) { |
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| 519 | return -1; |
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| 520 | } |
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| 521 | |
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| 522 | idt_bitmap.busy[i] = true; |
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| 523 | return (int)i; |
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| 524 | } |
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| 525 | |
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| 526 | void idt_slot_free(int slot) |
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| 527 | { |
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| 528 | idt_bitmap.busy[slot] = false; |
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| 529 | } |
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| 530 | |
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[29] | 531 | static void |
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| 532 | idt_set_seg(struct idt_seg *seg, void *func, int ist, int type, int dpl, int sel) |
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| 533 | { |
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| 534 | seg->gd_looffset = (uint64_t)func & 0xffff; |
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| 535 | seg->gd_selector = sel; |
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| 536 | seg->gd_ist = ist; |
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| 537 | seg->gd_type = type; |
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| 538 | seg->gd_dpl = dpl; |
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| 539 | seg->gd_p = 1; |
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| 540 | seg->gd_hioffset = (uint64_t)func >> 16; |
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| 541 | seg->gd_zero = 0; |
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| 542 | seg->gd_xx1 = 0; |
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| 543 | seg->gd_xx2 = 0; |
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| 544 | seg->gd_xx3 = 0; |
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| 545 | } |
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| 546 | |
---|
| 547 | static void idt_create() |
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| 548 | { |
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[80] | 549 | extern uint64_t x86_traps[], x86_intrs[], x86_rsvd; |
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[29] | 550 | struct idt_seg *idt; |
---|
| 551 | size_t i; |
---|
[292] | 552 | int ist; |
---|
[29] | 553 | |
---|
[203] | 554 | memset(&idt_bitmap, 0, sizeof(idt_bitmap)); |
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[29] | 555 | idt = (struct idt_seg *)&idtstore; |
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[45] | 556 | |
---|
[80] | 557 | /* First, put a dead entry */ |
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| 558 | for (i = 0; i < NIDT; i++) { |
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| 559 | idt_set_seg(&idt[i], (void *)&x86_rsvd, 0, |
---|
| 560 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
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| 561 | } |
---|
| 562 | |
---|
[45] | 563 | /* General exceptions */ |
---|
| 564 | for (i = CPUVEC_MIN; i < CPUVEC_MAX; i++) { |
---|
[292] | 565 | if (i == 2) { /* NMI */ |
---|
| 566 | ist = 3; |
---|
| 567 | } else if (i == 8) { /* Double Fault */ |
---|
| 568 | ist = 2; |
---|
| 569 | } else { |
---|
| 570 | ist = 0; |
---|
| 571 | } |
---|
[293] | 572 | idt_set_seg(&idt[i], (void *)x86_traps[i - CPUVEC_MIN], ist, |
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[45] | 573 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
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[203] | 574 | idt_bitmap.busy[i] = true; |
---|
[29] | 575 | } |
---|
[45] | 576 | |
---|
[138] | 577 | /* Dynamically configured interrupts */ |
---|
| 578 | for (i = DYNVEC_MIN; i < DYNVEC_MAX; i++) { |
---|
| 579 | idt_set_seg(&idt[i], (void *)x86_intrs[i - DYNVEC_MIN], 0, |
---|
[45] | 580 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
[203] | 581 | idt_bitmap.busy[i] = true; |
---|
[45] | 582 | } |
---|
[29] | 583 | } |
---|
| 584 | |
---|
| 585 | void cpu_load_idt() |
---|
| 586 | { |
---|
| 587 | struct region_descriptor region; |
---|
| 588 | setregion(®ion, &idtstore, PAGE_SIZE - 1); |
---|
| 589 | lidt(®ion); |
---|
| 590 | } |
---|
| 591 | |
---|
| 592 | /* -------------------------------------------------------------------------- */ |
---|
| 593 | |
---|
[164] | 594 | int tss_alloc(struct tss *tss, size_t lid) |
---|
[29] | 595 | { |
---|
| 596 | int slot; |
---|
| 597 | |
---|
[164] | 598 | slot = GDT_CPUTSS_SEL + lid; |
---|
[29] | 599 | |
---|
| 600 | gdt_set_sysseg(GDT_ADDR_SYS(gdtstore, slot), tss, |
---|
| 601 | sizeof(*tss) - 1, SDT_SYS386TSS, SEL_KPL, 0); |
---|
| 602 | |
---|
| 603 | return GDT_DYNAM_SEL(slot, SEL_KPL); |
---|
| 604 | } |
---|
| 605 | |
---|
[162] | 606 | void cpu_create_tss(size_t lid) |
---|
[29] | 607 | { |
---|
[165] | 608 | percpu_archdata_t *data = &cpudata[lid]; |
---|
| 609 | struct tss *tss = &data->tss; |
---|
[29] | 610 | int sel; |
---|
| 611 | |
---|
| 612 | /* Create the tss */ |
---|
| 613 | memset(tss, 0, sizeof(*tss)); |
---|
[162] | 614 | |
---|
| 615 | /* tss->tss_rsp0 */ |
---|
[283] | 616 | tss->tss_ist[0] = ((uint64_t)&data->intr_stack + STKSIZE) & ~0xF; |
---|
| 617 | tss->tss_ist[1] = ((uint64_t)&data->dbfl_stack + STKSIZE) & ~0xF; |
---|
| 618 | tss->tss_ist[2] = ((uint64_t)&data->nmfl_stack + STKSIZE) & ~0xF; |
---|
[29] | 619 | tss->tss_iobase = IOMAP_INVALOFF << 16; |
---|
[164] | 620 | sel = tss_alloc(tss, lid); |
---|
[29] | 621 | |
---|
| 622 | /* Load it */ |
---|
| 623 | ltr(sel); |
---|
| 624 | } |
---|
| 625 | |
---|
| 626 | /* -------------------------------------------------------------------------- */ |
---|
| 627 | |
---|
[168] | 628 | void cpu_tls_init(size_t lid) |
---|
| 629 | { |
---|
[308] | 630 | extern uint64_t x86_syscall; |
---|
| 631 | extern uint64_t x86_syscall32; |
---|
| 632 | |
---|
[168] | 633 | percpu_archdata_t *data = &cpudata[lid]; |
---|
| 634 | tls_t *cputls = &data->tls; |
---|
| 635 | |
---|
| 636 | memset(cputls, 0, sizeof(tls_t)); |
---|
| 637 | |
---|
| 638 | cputls->tls_self = cputls; |
---|
| 639 | cputls->tls_gid = hal_lapic_gid(); |
---|
| 640 | cputls->tls_lid = lid; |
---|
[240] | 641 | cputls->tls_intr = INTRS_DISABLED; |
---|
[168] | 642 | |
---|
[308] | 643 | /* syscall */ |
---|
| 644 | wrmsr(MSR_STAR, |
---|
| 645 | ((uint64_t)GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL) << 32) | |
---|
| 646 | ((uint64_t)GDT_FIXED_SEL(GDT_UCODE32_SEL, SEL_UPL) << 48)); |
---|
| 647 | wrmsr(MSR_LSTAR, (uint64_t)&x86_syscall); |
---|
| 648 | wrmsr(MSR_CSTAR, (uint64_t)&x86_syscall32); |
---|
| 649 | wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); |
---|
| 650 | |
---|
| 651 | /* TLS */ |
---|
[168] | 652 | wrmsr(MSR_FSBASE, 0); |
---|
| 653 | wrmsr(MSR_GSBASE, (uint64_t)cputls); |
---|
| 654 | wrmsr(MSR_KERNELGSBASE, 0); |
---|
| 655 | } |
---|
| 656 | |
---|
| 657 | /* -------------------------------------------------------------------------- */ |
---|
| 658 | |
---|
[166] | 659 | uint64_t cpu_features[4] __in_kdata; |
---|
| 660 | |
---|
| 661 | void cpu_identify() |
---|
| 662 | { |
---|
| 663 | /* |
---|
| 664 | * desc[0] = eax |
---|
| 665 | * desc[1] = ebx |
---|
| 666 | * desc[2] = ecx |
---|
| 667 | * desc[3] = edx |
---|
| 668 | */ |
---|
| 669 | uint32_t desc[4]; |
---|
| 670 | char vendor[13]; |
---|
| 671 | size_t lvl; |
---|
| 672 | |
---|
| 673 | /* |
---|
| 674 | * Get information from the standard cpuid leafs |
---|
| 675 | */ |
---|
| 676 | cpuid(0, 0, (uint32_t *)&desc); |
---|
| 677 | |
---|
| 678 | lvl = (uint64_t)desc[0]; |
---|
| 679 | x86_printf("-> cpuid standard level: %z\n", lvl); |
---|
| 680 | |
---|
| 681 | memcpy(vendor + 0, &desc[1], sizeof(uint32_t)); |
---|
| 682 | memcpy(vendor + 8, &desc[2], sizeof(uint32_t)); |
---|
| 683 | memcpy(vendor + 4, &desc[3], sizeof(uint32_t)); |
---|
| 684 | vendor[12] = '\0'; |
---|
| 685 | x86_printf("-> CPU vendor: '%s'\n", vendor); |
---|
| 686 | |
---|
| 687 | if (lvl >= 1) { |
---|
| 688 | cpuid(1, 0, (uint32_t *)&desc); |
---|
| 689 | cpu_features[0] = desc[3]; |
---|
| 690 | cpu_features[1] = desc[2]; |
---|
| 691 | } |
---|
| 692 | |
---|
| 693 | /* |
---|
| 694 | * Get information from the extended cpuid leafs |
---|
| 695 | */ |
---|
| 696 | cpuid(0x80000000, 0, desc); |
---|
| 697 | |
---|
| 698 | lvl = (uint64_t)desc[0]; |
---|
| 699 | x86_printf("-> cpuid extended level: %Z\n", lvl); |
---|
| 700 | } |
---|
| 701 | |
---|
| 702 | /* -------------------------------------------------------------------------- */ |
---|
| 703 | |
---|
[162] | 704 | void cpu_attach(size_t lid) |
---|
[29] | 705 | { |
---|
[168] | 706 | /* Per-cluster structures */ |
---|
[29] | 707 | cpu_load_gdt(); |
---|
| 708 | cpu_load_idt(); |
---|
[168] | 709 | |
---|
| 710 | /* Per-cpu structures */ |
---|
[162] | 711 | cpu_create_tss(lid); |
---|
[166] | 712 | |
---|
| 713 | if (cpu_features[0] & CPUID_PSE) { |
---|
| 714 | lcr4(rcr4() | CR4_PSE); |
---|
| 715 | tlbflushg(); |
---|
| 716 | } else { |
---|
| 717 | /* |
---|
| 718 | * amd64 supports PSE by default, if it's not here we have a |
---|
| 719 | * problem |
---|
| 720 | */ |
---|
| 721 | x86_panic("PSE not supported"); |
---|
| 722 | } |
---|
[29] | 723 | } |
---|
| 724 | |
---|