[29] | 1 | /* |
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| 2 | * hal_init.c - C initialization procedure for x86. |
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| 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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[234] | 18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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[29] | 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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[457] | 22 | #include <hal_kernel_types.h> |
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[29] | 23 | #include <hal_boot.h> |
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[32] | 24 | #include <hal_multiboot.h> |
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[29] | 25 | #include <hal_segmentation.h> |
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[45] | 26 | #include <hal_acpi.h> |
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[82] | 27 | #include <hal_apic.h> |
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[308] | 28 | #include <hal_kentry.h> |
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[35] | 29 | #include <hal_internal.h> |
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[166] | 30 | #include <hal_register.h> |
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| 31 | |
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[72] | 32 | #include <hal_remote.h> |
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[99] | 33 | #include <hal_irqmask.h> |
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[29] | 34 | |
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| 35 | #include <memcpy.h> |
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| 36 | #include <thread.h> |
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| 37 | #include <string.h> |
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| 38 | #include <process.h> |
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| 39 | #include <printk.h> |
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| 40 | #include <vmm.h> |
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| 41 | #include <core.h> |
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| 42 | #include <cluster.h> |
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[70] | 43 | #include <chdev.h> |
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[29] | 44 | |
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[70] | 45 | #include <boot_info.h> |
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| 46 | |
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[81] | 47 | void kernel_init(boot_info_t *info); |
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| 48 | |
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[29] | 49 | static void gdt_create(); |
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| 50 | static void idt_create(); |
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[168] | 51 | void cpu_tls_init(size_t lid); |
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[166] | 52 | void cpu_identify(); |
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[237] | 53 | void cpu_attach(size_t lid); |
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[29] | 54 | |
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[44] | 55 | size_t mytest __in_kdata = 0; |
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[32] | 56 | |
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| 57 | struct multiboot_info mb_info __in_kdata; |
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| 58 | char mb_loader_name[PAGE_SIZE] __in_kdata; |
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| 59 | uint8_t mb_mmap[PAGE_SIZE] __in_kdata; |
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[312] | 60 | char mb_cmdline[PAGE_SIZE] __in_kdata; |
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[32] | 61 | |
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[312] | 62 | bool_t has_smp __in_kdata = true; |
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[240] | 63 | size_t ncpu __in_kdata = 0; |
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| 64 | static boot_info_t btinfo __in_kdata; |
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| 65 | |
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[236] | 66 | /* x86-specific per-cluster structures */ |
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| 67 | uint8_t gdtstore[PAGE_SIZE] __in_kdata; |
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| 68 | uint8_t idtstore[PAGE_SIZE] __in_kdata; |
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| 69 | |
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| 70 | /* x86-specific per-cpu structures */ |
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| 71 | typedef struct { |
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| 72 | bool_t valid; |
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| 73 | struct tss tss; |
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| 74 | struct tls tls; |
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| 75 | uint8_t boot_stack[STKSIZE]; |
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| 76 | uint8_t intr_stack[STKSIZE]; |
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| 77 | uint8_t dbfl_stack[STKSIZE]; |
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| 78 | uint8_t nmfl_stack[STKSIZE]; |
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| 79 | } percpu_archdata_t; |
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| 80 | percpu_archdata_t cpudata[CONFIG_MAX_LOCAL_CORES] __in_kdata; |
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| 81 | |
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[29] | 82 | /* -------------------------------------------------------------------------- */ |
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| 83 | |
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[323] | 84 | /* |
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| 85 | * Configure the features of the system depending on the multiboot info. |
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| 86 | */ |
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| 87 | static void multiboot_init() |
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[312] | 88 | { |
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[32] | 89 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 90 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 91 | size_t i; |
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| 92 | |
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| 93 | if (!(mb_info.mi_flags & MULTIBOOT_INFO_HAS_MMAP)) |
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[46] | 94 | x86_panic("No mmap"); |
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[32] | 95 | |
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| 96 | i = 0; |
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| 97 | while (i < mmap_length) { |
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| 98 | struct multiboot_mmap *mm; |
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| 99 | |
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| 100 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 101 | |
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| 102 | x86_printf("-> [%Z, %Z] %s\n", mm->mm_base_addr, |
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| 103 | mm->mm_base_addr + mm->mm_length, |
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| 104 | (mm->mm_type == 1) ? "ram" : "rsv" ); |
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| 105 | |
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| 106 | i += mm->mm_size + 4; |
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| 107 | } |
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[312] | 108 | |
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| 109 | if (mb_info.mi_flags & MULTIBOOT_INFO_HAS_CMDLINE) { |
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| 110 | mb_cmdline[PAGE_SIZE-1] = '\0'; |
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| 111 | if (strstr(mb_cmdline, "--no-smp")) { |
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| 112 | has_smp = false; |
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| 113 | x86_printf("[+] SMP disabled\n"); |
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| 114 | } |
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| 115 | } |
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[32] | 116 | } |
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| 117 | |
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[135] | 118 | /* -------------------------------------------------------------------------- */ |
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| 119 | |
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[119] | 120 | static size_t init_bootinfo_pages_nr() |
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| 121 | { |
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| 122 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 123 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 124 | paddr_t maxpa, pa; |
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| 125 | size_t i; |
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| 126 | |
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| 127 | i = 0; |
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| 128 | maxpa = 0; |
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| 129 | while (i < mmap_length) { |
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| 130 | struct multiboot_mmap *mm; |
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| 131 | |
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| 132 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 133 | |
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| 134 | if (mm->mm_type == 1) { |
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| 135 | pa = mm->mm_base_addr + mm->mm_length; |
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| 136 | if (pa > maxpa) |
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| 137 | maxpa = pa; |
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| 138 | } |
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| 139 | |
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| 140 | i += mm->mm_size + 4; |
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| 141 | } |
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| 142 | |
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| 143 | return (maxpa / PAGE_SIZE); |
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| 144 | } |
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| 145 | |
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[116] | 146 | static size_t init_bootinfo_rsvd(boot_rsvd_t *rsvd) |
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| 147 | { |
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| 148 | size_t mmap_length = mb_info.mi_mmap_length; |
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| 149 | uint8_t *mmap_addr = (uint8_t *)&mb_mmap; |
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| 150 | size_t i, rsvd_nr; |
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| 151 | |
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[137] | 152 | memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD); |
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[116] | 153 | |
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| 154 | i = 0, rsvd_nr = 0; |
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| 155 | while (i < mmap_length) { |
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| 156 | struct multiboot_mmap *mm; |
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| 157 | |
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| 158 | mm = (struct multiboot_mmap *)(mmap_addr + i); |
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| 159 | |
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[119] | 160 | if (mm->mm_type != 1) { |
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| 161 | rsvd[rsvd_nr].first_page = |
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| 162 | rounddown(mm->mm_base_addr, PAGE_SIZE) / PAGE_SIZE; |
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| 163 | rsvd[rsvd_nr].npages = |
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| 164 | roundup(mm->mm_length, PAGE_SIZE) / PAGE_SIZE; |
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| 165 | rsvd_nr++; |
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| 166 | if (rsvd_nr == CONFIG_PPM_MAX_RSVD) |
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| 167 | x86_panic("too many memory holes"); |
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| 168 | } |
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[116] | 169 | |
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| 170 | i += mm->mm_size + 4; |
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| 171 | } |
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| 172 | |
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| 173 | return rsvd_nr; |
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| 174 | } |
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| 175 | |
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[312] | 176 | static void init_bootinfo_core(boot_core_t *core, size_t n) |
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[70] | 177 | { |
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[240] | 178 | size_t i; |
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[70] | 179 | |
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[240] | 180 | // XXX: not necessarily contiguous |
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[312] | 181 | for (i = 0; i < n; i++) { |
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[240] | 182 | memset(&core[i], 0, sizeof(boot_core_t)); |
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| 183 | |
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| 184 | core[i].gid = i; |
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| 185 | core[i].lid = i; |
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| 186 | core[i].cxy = 0; |
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| 187 | } |
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[70] | 188 | } |
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| 189 | |
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[195] | 190 | static void init_bootinfo_ioc(boot_device_t *dev) |
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| 191 | { |
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| 192 | memset(dev, 0, sizeof(boot_device_t)); |
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| 193 | |
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| 194 | dev->base = 0; |
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| 195 | dev->type = (DEV_FUNC_IOC << 16) | IMPL_IOC_BDV; |
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| 196 | dev->channels = 1; |
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| 197 | } |
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| 198 | |
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[192] | 199 | static void init_bootinfo_pic(boot_device_t *dev) |
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[70] | 200 | { |
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| 201 | memset(dev, 0, sizeof(boot_device_t)); |
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| 202 | |
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[192] | 203 | dev->base = 0; |
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[252] | 204 | dev->type = (DEV_FUNC_PIC << 16) | IMPL_PIC_I86; |
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[70] | 205 | dev->channels = 1; |
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| 206 | dev->param0 = 0; |
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| 207 | dev->param1 = 0; |
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| 208 | dev->param2 = 0; |
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| 209 | dev->param3 = 0; |
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| 210 | |
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[202] | 211 | dev->irqs = 16; |
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[192] | 212 | |
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[202] | 213 | /* ATA */ |
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| 214 | dev->irq[IRQ_ATA0].dev_type = (DEV_FUNC_IOC << 16) | IMPL_IOC_BDV; |
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| 215 | dev->irq[IRQ_ATA0].channel = 0; |
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| 216 | dev->irq[IRQ_ATA0].is_rx = 0; |
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| 217 | dev->irq[IRQ_ATA0].valid = 1; |
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[70] | 218 | } |
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| 219 | |
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[192] | 220 | static void init_bootinfo_txt(boot_device_t *dev) |
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| 221 | { |
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| 222 | memset(dev, 0, sizeof(boot_device_t)); |
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| 223 | |
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| 224 | dev->base = 0; |
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[254] | 225 | dev->type = (DEV_FUNC_TXT << 16) | IMPL_TXT_RS2; |
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[255] | 226 | dev->channels = 4; |
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[192] | 227 | dev->param0 = 0; |
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| 228 | dev->param1 = 0; |
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| 229 | dev->param2 = 0; |
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| 230 | dev->param3 = 0; |
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| 231 | } |
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| 232 | |
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[70] | 233 | static void init_bootinfo(boot_info_t *info) |
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| 234 | { |
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[116] | 235 | size_t offset; |
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[114] | 236 | |
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[70] | 237 | memset(info, 0, sizeof(boot_info_t)); |
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| 238 | |
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| 239 | info->signature = 0; |
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| 240 | |
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| 241 | info->paddr_width = 0; |
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| 242 | info->x_width = 1; |
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| 243 | info->y_width = 1; |
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| 244 | info->x_size = 1; |
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| 245 | info->y_size = 1; |
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| 246 | info->io_cxy = 0; |
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| 247 | |
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[195] | 248 | info->ext_dev_nr = 3; |
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[70] | 249 | init_bootinfo_txt(&info->ext_dev[0]); |
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[192] | 250 | init_bootinfo_pic(&info->ext_dev[1]); |
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[195] | 251 | init_bootinfo_ioc(&info->ext_dev[2]); |
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[70] | 252 | |
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| 253 | info->cxy = 0; |
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[312] | 254 | if (has_smp) { |
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| 255 | info->cores_nr = ncpu; |
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| 256 | } else { |
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| 257 | info->cores_nr = 1; |
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| 258 | } |
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| 259 | init_bootinfo_core((boot_core_t *)&info->core, info->cores_nr); |
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[70] | 260 | |
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[137] | 261 | info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd); |
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[70] | 262 | |
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[135] | 263 | /* TODO: dev_mmc */ |
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| 264 | /* TODO: dev_dma */ |
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| 265 | |
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[116] | 266 | offset = hal_gpt_bootstrap_uniformize(); |
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| 267 | info->pages_offset = offset / PAGE_SIZE; |
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[119] | 268 | info->pages_nr = init_bootinfo_pages_nr(); |
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[70] | 269 | } |
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| 270 | |
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[166] | 271 | /* -------------------------------------------------------------------------- */ |
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| 272 | |
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[236] | 273 | static uint32_t cpuN_booted __in_kdata; |
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| 274 | |
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| 275 | void start_secondary_cpus() |
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| 276 | { |
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| 277 | pt_entry_t flags = PG_V | PG_KW; |
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| 278 | extern vaddr_t cpuN_boot_trampoline; |
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| 279 | extern vaddr_t cpuN_boot_trampoline_end; |
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| 280 | extern paddr_t smp_L4pa; |
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| 281 | extern vaddr_t smp_stkva; |
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| 282 | extern paddr_t L4paddr; |
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| 283 | size_t i, sz; |
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| 284 | |
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| 285 | smp_L4pa = L4paddr; |
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| 286 | |
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| 287 | /* map the SMP trampoline (identity) */ |
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| 288 | vaddr_t trampva = (vaddr_t)SMP_TRAMPOLINE_PA; |
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| 289 | hal_gpt_maptree_area(trampva, trampva + PAGE_SIZE); |
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| 290 | hal_gpt_enter(trampva, SMP_TRAMPOLINE_PA, flags); |
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| 291 | |
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| 292 | /* copy it */ |
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| 293 | sz = (size_t)&cpuN_boot_trampoline_end - (size_t)&cpuN_boot_trampoline; |
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| 294 | memcpy((void *)trampva, (void *)&cpuN_boot_trampoline, sz); |
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| 295 | |
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| 296 | for (i = 0; i < CONFIG_MAX_LOCAL_CORES; i++) { |
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| 297 | if (i == 0 || !cpudata[i].valid) { |
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| 298 | continue; |
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| 299 | } |
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| 300 | |
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[283] | 301 | smp_stkva = ((vaddr_t)&cpudata[i].boot_stack + STKSIZE) & ~0xF; |
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[236] | 302 | |
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| 303 | cpuN_booted = 0; |
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| 304 | boot_cpuN(i, SMP_TRAMPOLINE_PA); |
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| 305 | while (!hal_atomic_cas(&cpuN_booted, 1, 0)) { |
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[310] | 306 | pause(); |
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[236] | 307 | } |
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| 308 | } |
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| 309 | |
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| 310 | // XXX: unmap the trampoline |
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| 311 | } |
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| 312 | |
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| 313 | void init_x86_64_cpuN() |
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| 314 | { |
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[240] | 315 | lid_t lid; |
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[237] | 316 | |
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[240] | 317 | cli(); |
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| 318 | |
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| 319 | lid = hal_lapic_gid(); |
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| 320 | |
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[237] | 321 | cpu_attach(lid); |
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| 322 | x86_printf("[cpu%z] cpu_attach called\n", (uint64_t)lid); |
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| 323 | |
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| 324 | cpu_tls_init(lid); |
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| 325 | x86_printf("[cpu%z] cput_tls_init called\n", (uint64_t)lid); |
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| 326 | |
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| 327 | cpu_lapic_init(); |
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| 328 | x86_printf("[cpu%z] cpu_lapic_init called\n", (uint64_t)lid); |
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| 329 | |
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[236] | 330 | cpuN_booted = 1; |
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[237] | 331 | |
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| 332 | if (lid == 1) { |
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| 333 | hal_ioapic_disable_irq(IRQ_KEYBOARD); |
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| 334 | hal_ioapic_bind_irq(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 1); |
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| 335 | hal_ioapic_enable_irq(IRQ_KEYBOARD); |
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| 336 | } |
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| 337 | |
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[240] | 338 | kernel_init(&btinfo); |
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| 339 | |
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| 340 | reg_t dummy; |
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| 341 | hal_enable_irq(&dummy); |
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| 342 | |
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[236] | 343 | while (1); |
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| 344 | } |
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| 345 | |
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| 346 | /* -------------------------------------------------------------------------- */ |
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| 347 | |
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[199] | 348 | static void apic_map() |
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| 349 | { |
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| 350 | extern vaddr_t lapic_va, ioapic_va; |
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| 351 | extern paddr_t lapic_pa, ioapic_pa; |
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| 352 | |
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| 353 | lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 354 | hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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| 355 | |
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| 356 | ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
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| 357 | hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
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| 358 | } |
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| 359 | |
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[29] | 360 | void init_x86_64(paddr_t firstpa) |
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| 361 | { |
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[240] | 362 | cli(); |
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[70] | 363 | |
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[154] | 364 | /* Initialize the serial port */ |
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| 365 | hal_com_init_early(); |
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| 366 | |
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[29] | 367 | x86_printf("[+] init_x86_64 called\n"); |
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| 368 | |
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| 369 | /* Create the global structures */ |
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| 370 | gdt_create(); |
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| 371 | idt_create(); |
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| 372 | |
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[166] | 373 | /* Identify the features of the cpu */ |
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| 374 | cpu_identify(); |
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| 375 | |
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[29] | 376 | /* Attach cpu0 */ |
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[162] | 377 | cpu_attach(0); |
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[29] | 378 | x86_printf("[+] cpu_attach called\n"); |
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| 379 | |
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[47] | 380 | x86_printf("[+] bootloader: '%s'\n", mb_loader_name); |
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[32] | 381 | |
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[323] | 382 | multiboot_init(); |
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| 383 | x86_printf("[+] multiboot_init called\n"); |
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[32] | 384 | |
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[35] | 385 | hal_gpt_init(firstpa); |
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| 386 | x86_printf("[+] hal_gpt_init called\n"); |
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[29] | 387 | |
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[35] | 388 | hal_acpi_init(); |
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| 389 | x86_printf("[+] hal_acpi_init called\n"); |
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| 390 | |
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[45] | 391 | hal_gpt_bootstrap_reset(); |
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| 392 | x86_printf("[+] hal_gpt_bootstrap_reset called\n"); |
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| 393 | |
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[199] | 394 | apic_map(); |
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| 395 | x86_printf("[+] apic_map called\n"); |
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| 396 | |
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[82] | 397 | hal_apic_init(); |
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[237] | 398 | cpu_lapic_init(); |
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[82] | 399 | x86_printf("[+] hal_apic_init called\n"); |
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[45] | 400 | |
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[168] | 401 | cpu_tls_init(0); |
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| 402 | x86_printf("[+] cput_tls_init called\n"); |
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[46] | 403 | |
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[224] | 404 | mytest = 0; |
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[44] | 405 | x86_printf("-> mytest = %z\n", mytest); |
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[94] | 406 | void *hoho = &init_x86_64; |
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[74] | 407 | xptr_t myptr = XPTR(0, &mytest); |
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[35] | 408 | |
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[94] | 409 | hal_remote_spt(myptr, hoho); |
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| 410 | x86_printf("-> mytest = %Z\n", hal_remote_lpt(myptr)); |
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| 411 | |
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[99] | 412 | init_bootinfo(&btinfo); |
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[94] | 413 | |
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[312] | 414 | if (has_smp) { |
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| 415 | start_secondary_cpus(); |
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| 416 | } |
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[236] | 417 | |
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[276] | 418 | kernel_init(&btinfo); |
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| 419 | |
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| 420 | x86_printf("[+] kernel_init called\n"); |
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| 421 | |
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[274] | 422 | reg_t dummy; |
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| 423 | hal_enable_irq(&dummy); |
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| 424 | |
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| 425 | while (1); |
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| 426 | |
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[192] | 427 | /* |
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| 428 | void *ptr; |
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[70] | 429 | |
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[192] | 430 | khm_t *khm = &LOCAL_CLUSTER->khm; |
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| 431 | ptr = khm_alloc(khm, 10); |
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| 432 | memset(ptr, 0, 10); |
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| 433 | khm_free(ptr); |
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| 434 | |
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| 435 | |
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| 436 | kcm_t *kcm = &LOCAL_CLUSTER->kcm; |
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| 437 | ptr = kcm_alloc(kcm); |
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| 438 | memset(ptr, 0, 1); |
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| 439 | kcm_free(ptr); |
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| 440 | |
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| 441 | ptr = ppm_alloc_pages(1); |
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| 442 | ppm_free_pages(ptr); |
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| 443 | */ |
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[29] | 444 | } |
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| 445 | |
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| 446 | /* -------------------------------------------------------------------------- */ |
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| 447 | |
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[235] | 448 | void cpu_activate(uint32_t gid) |
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| 449 | { |
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| 450 | cpudata[gid].valid = true; |
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| 451 | } |
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| 452 | |
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[323] | 453 | static void setregion(struct region_descriptor *rd, void *base, uint16_t limit) |
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[29] | 454 | { |
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| 455 | rd->rd_limit = limit; |
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| 456 | rd->rd_base = (uint64_t)base; |
---|
| 457 | } |
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| 458 | |
---|
| 459 | /* -------------------------------------------------------------------------- */ |
---|
| 460 | |
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[323] | 461 | static void gdt_set_memseg(struct gdt_memseg *sd, void *base, size_t limit, |
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[308] | 462 | int type, int dpl, int gran, bool_t is64) |
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[29] | 463 | { |
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| 464 | sd->sd_lolimit = (unsigned)limit; |
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| 465 | sd->sd_lobase = (unsigned long)base; |
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| 466 | sd->sd_type = type; |
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| 467 | sd->sd_dpl = dpl; |
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| 468 | sd->sd_p = 1; |
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| 469 | sd->sd_hilimit = (unsigned)limit >> 16; |
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| 470 | sd->sd_avl = 0; |
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| 471 | sd->sd_long = is64; |
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[308] | 472 | sd->sd_def32 = !is64; |
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[29] | 473 | sd->sd_gran = gran; |
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| 474 | sd->sd_hibase = (unsigned long)base >> 24; |
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| 475 | } |
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| 476 | |
---|
[323] | 477 | static void gdt_set_sysseg(struct gdt_sysseg *sd, void *base, size_t limit, |
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[29] | 478 | int type, int dpl, int gran) |
---|
| 479 | { |
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| 480 | memset(sd, 0, sizeof *sd); |
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| 481 | sd->sd_lolimit = (unsigned)limit; |
---|
| 482 | sd->sd_lobase = (uint64_t)base; |
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| 483 | sd->sd_type = type; |
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| 484 | sd->sd_dpl = dpl; |
---|
| 485 | sd->sd_p = 1; |
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| 486 | sd->sd_hilimit = (unsigned)limit >> 16; |
---|
| 487 | sd->sd_gran = gran; |
---|
| 488 | sd->sd_hibase = (uint64_t)base >> 24; |
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| 489 | } |
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| 490 | |
---|
| 491 | static void gdt_create() |
---|
| 492 | { |
---|
| 493 | memset(&gdtstore, 0, PAGE_SIZE); |
---|
| 494 | |
---|
| 495 | /* Flat segments */ |
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| 496 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KCODE_SEL), 0, |
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[308] | 497 | 0xfffff, SDT_MEMERA, SEL_KPL, 1, true); |
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[29] | 498 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_KDATA_SEL), 0, |
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[308] | 499 | 0xfffff, SDT_MEMRWA, SEL_KPL, 1, true); |
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| 500 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE32_SEL), 0, |
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| 501 | 0xfffff, SDT_MEMERA, SEL_UPL, 1, false); |
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[29] | 502 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UCODE_SEL), 0, |
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[308] | 503 | 0xfffff, SDT_MEMERA, SEL_UPL, 1, true); |
---|
[29] | 504 | gdt_set_memseg(GDT_ADDR_MEM(gdtstore, GDT_UDATA_SEL), 0, |
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[308] | 505 | 0xfffff, SDT_MEMRWA, SEL_UPL, 1, true); |
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[29] | 506 | } |
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| 507 | |
---|
| 508 | void cpu_load_gdt() |
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| 509 | { |
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| 510 | struct region_descriptor region; |
---|
| 511 | setregion(®ion, &gdtstore, PAGE_SIZE - 1); |
---|
| 512 | lgdt(®ion); |
---|
| 513 | } |
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| 514 | |
---|
| 515 | /* -------------------------------------------------------------------------- */ |
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| 516 | |
---|
[203] | 517 | struct { |
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| 518 | bool_t busy[256]; |
---|
| 519 | } idt_bitmap __in_kdata; |
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| 520 | |
---|
| 521 | int idt_slot_alloc() |
---|
| 522 | { |
---|
| 523 | size_t i; |
---|
| 524 | |
---|
| 525 | for (i = 0; i < 256; i++) { |
---|
| 526 | if (!idt_bitmap.busy[i]) |
---|
| 527 | break; |
---|
| 528 | } |
---|
| 529 | if (i == 256) { |
---|
| 530 | return -1; |
---|
| 531 | } |
---|
| 532 | |
---|
| 533 | idt_bitmap.busy[i] = true; |
---|
| 534 | return (int)i; |
---|
| 535 | } |
---|
| 536 | |
---|
| 537 | void idt_slot_free(int slot) |
---|
| 538 | { |
---|
| 539 | idt_bitmap.busy[slot] = false; |
---|
| 540 | } |
---|
| 541 | |
---|
[323] | 542 | static void idt_set_seg(struct idt_seg *seg, void *func, int ist, int type, |
---|
| 543 | int dpl, int sel) |
---|
[29] | 544 | { |
---|
| 545 | seg->gd_looffset = (uint64_t)func & 0xffff; |
---|
| 546 | seg->gd_selector = sel; |
---|
| 547 | seg->gd_ist = ist; |
---|
| 548 | seg->gd_type = type; |
---|
| 549 | seg->gd_dpl = dpl; |
---|
| 550 | seg->gd_p = 1; |
---|
| 551 | seg->gd_hioffset = (uint64_t)func >> 16; |
---|
| 552 | seg->gd_zero = 0; |
---|
| 553 | seg->gd_xx1 = 0; |
---|
| 554 | seg->gd_xx2 = 0; |
---|
| 555 | seg->gd_xx3 = 0; |
---|
| 556 | } |
---|
| 557 | |
---|
| 558 | static void idt_create() |
---|
| 559 | { |
---|
[80] | 560 | extern uint64_t x86_traps[], x86_intrs[], x86_rsvd; |
---|
[29] | 561 | struct idt_seg *idt; |
---|
| 562 | size_t i; |
---|
[292] | 563 | int ist; |
---|
[29] | 564 | |
---|
[203] | 565 | memset(&idt_bitmap, 0, sizeof(idt_bitmap)); |
---|
[29] | 566 | idt = (struct idt_seg *)&idtstore; |
---|
[45] | 567 | |
---|
[80] | 568 | /* First, put a dead entry */ |
---|
| 569 | for (i = 0; i < NIDT; i++) { |
---|
| 570 | idt_set_seg(&idt[i], (void *)&x86_rsvd, 0, |
---|
| 571 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
| 572 | } |
---|
| 573 | |
---|
[45] | 574 | /* General exceptions */ |
---|
| 575 | for (i = CPUVEC_MIN; i < CPUVEC_MAX; i++) { |
---|
[292] | 576 | if (i == 2) { /* NMI */ |
---|
| 577 | ist = 3; |
---|
| 578 | } else if (i == 8) { /* Double Fault */ |
---|
| 579 | ist = 2; |
---|
| 580 | } else { |
---|
| 581 | ist = 0; |
---|
| 582 | } |
---|
[293] | 583 | idt_set_seg(&idt[i], (void *)x86_traps[i - CPUVEC_MIN], ist, |
---|
[45] | 584 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
[203] | 585 | idt_bitmap.busy[i] = true; |
---|
[29] | 586 | } |
---|
[45] | 587 | |
---|
[138] | 588 | /* Dynamically configured interrupts */ |
---|
| 589 | for (i = DYNVEC_MIN; i < DYNVEC_MAX; i++) { |
---|
| 590 | idt_set_seg(&idt[i], (void *)x86_intrs[i - DYNVEC_MIN], 0, |
---|
[45] | 591 | SDT_SYS386IGT, SEL_KPL, GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL)); |
---|
[203] | 592 | idt_bitmap.busy[i] = true; |
---|
[45] | 593 | } |
---|
[29] | 594 | } |
---|
| 595 | |
---|
| 596 | void cpu_load_idt() |
---|
| 597 | { |
---|
| 598 | struct region_descriptor region; |
---|
| 599 | setregion(®ion, &idtstore, PAGE_SIZE - 1); |
---|
| 600 | lidt(®ion); |
---|
| 601 | } |
---|
| 602 | |
---|
| 603 | /* -------------------------------------------------------------------------- */ |
---|
| 604 | |
---|
[164] | 605 | int tss_alloc(struct tss *tss, size_t lid) |
---|
[29] | 606 | { |
---|
| 607 | int slot; |
---|
| 608 | |
---|
[164] | 609 | slot = GDT_CPUTSS_SEL + lid; |
---|
[29] | 610 | |
---|
| 611 | gdt_set_sysseg(GDT_ADDR_SYS(gdtstore, slot), tss, |
---|
| 612 | sizeof(*tss) - 1, SDT_SYS386TSS, SEL_KPL, 0); |
---|
| 613 | |
---|
| 614 | return GDT_DYNAM_SEL(slot, SEL_KPL); |
---|
| 615 | } |
---|
| 616 | |
---|
[162] | 617 | void cpu_create_tss(size_t lid) |
---|
[29] | 618 | { |
---|
[165] | 619 | percpu_archdata_t *data = &cpudata[lid]; |
---|
| 620 | struct tss *tss = &data->tss; |
---|
[29] | 621 | int sel; |
---|
| 622 | |
---|
| 623 | /* Create the tss */ |
---|
| 624 | memset(tss, 0, sizeof(*tss)); |
---|
[162] | 625 | |
---|
[345] | 626 | tss->tss_rsp0 = ((uint64_t)&data->boot_stack + STKSIZE) & ~0xF; |
---|
[283] | 627 | tss->tss_ist[0] = ((uint64_t)&data->intr_stack + STKSIZE) & ~0xF; |
---|
| 628 | tss->tss_ist[1] = ((uint64_t)&data->dbfl_stack + STKSIZE) & ~0xF; |
---|
| 629 | tss->tss_ist[2] = ((uint64_t)&data->nmfl_stack + STKSIZE) & ~0xF; |
---|
[29] | 630 | tss->tss_iobase = IOMAP_INVALOFF << 16; |
---|
[164] | 631 | sel = tss_alloc(tss, lid); |
---|
[29] | 632 | |
---|
| 633 | /* Load it */ |
---|
| 634 | ltr(sel); |
---|
| 635 | } |
---|
| 636 | |
---|
| 637 | /* -------------------------------------------------------------------------- */ |
---|
| 638 | |
---|
[168] | 639 | void cpu_tls_init(size_t lid) |
---|
| 640 | { |
---|
[308] | 641 | extern uint64_t x86_syscall; |
---|
| 642 | extern uint64_t x86_syscall32; |
---|
| 643 | |
---|
[168] | 644 | percpu_archdata_t *data = &cpudata[lid]; |
---|
| 645 | tls_t *cputls = &data->tls; |
---|
| 646 | |
---|
| 647 | memset(cputls, 0, sizeof(tls_t)); |
---|
| 648 | |
---|
| 649 | cputls->tls_self = cputls; |
---|
| 650 | cputls->tls_gid = hal_lapic_gid(); |
---|
| 651 | cputls->tls_lid = lid; |
---|
[345] | 652 | cputls->tls_rsp0 = (uint64_t)&data->tss.tss_rsp0; |
---|
[240] | 653 | cputls->tls_intr = INTRS_DISABLED; |
---|
[168] | 654 | |
---|
[308] | 655 | /* syscall */ |
---|
| 656 | wrmsr(MSR_STAR, |
---|
| 657 | ((uint64_t)GDT_FIXED_SEL(GDT_KCODE_SEL, SEL_KPL) << 32) | |
---|
| 658 | ((uint64_t)GDT_FIXED_SEL(GDT_UCODE32_SEL, SEL_UPL) << 48)); |
---|
| 659 | wrmsr(MSR_LSTAR, (uint64_t)&x86_syscall); |
---|
| 660 | wrmsr(MSR_CSTAR, (uint64_t)&x86_syscall32); |
---|
| 661 | wrmsr(MSR_SFMASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); |
---|
| 662 | |
---|
| 663 | /* TLS */ |
---|
[168] | 664 | wrmsr(MSR_FSBASE, 0); |
---|
| 665 | wrmsr(MSR_GSBASE, (uint64_t)cputls); |
---|
| 666 | wrmsr(MSR_KERNELGSBASE, 0); |
---|
| 667 | } |
---|
| 668 | |
---|
| 669 | /* -------------------------------------------------------------------------- */ |
---|
| 670 | |
---|
[166] | 671 | uint64_t cpu_features[4] __in_kdata; |
---|
| 672 | |
---|
| 673 | void cpu_identify() |
---|
| 674 | { |
---|
| 675 | /* |
---|
| 676 | * desc[0] = eax |
---|
| 677 | * desc[1] = ebx |
---|
| 678 | * desc[2] = ecx |
---|
| 679 | * desc[3] = edx |
---|
| 680 | */ |
---|
| 681 | uint32_t desc[4]; |
---|
| 682 | char vendor[13]; |
---|
| 683 | size_t lvl; |
---|
| 684 | |
---|
| 685 | /* |
---|
| 686 | * Get information from the standard cpuid leafs |
---|
| 687 | */ |
---|
| 688 | cpuid(0, 0, (uint32_t *)&desc); |
---|
| 689 | |
---|
| 690 | lvl = (uint64_t)desc[0]; |
---|
| 691 | x86_printf("-> cpuid standard level: %z\n", lvl); |
---|
| 692 | |
---|
| 693 | memcpy(vendor + 0, &desc[1], sizeof(uint32_t)); |
---|
| 694 | memcpy(vendor + 8, &desc[2], sizeof(uint32_t)); |
---|
| 695 | memcpy(vendor + 4, &desc[3], sizeof(uint32_t)); |
---|
| 696 | vendor[12] = '\0'; |
---|
| 697 | x86_printf("-> CPU vendor: '%s'\n", vendor); |
---|
| 698 | |
---|
| 699 | if (lvl >= 1) { |
---|
| 700 | cpuid(1, 0, (uint32_t *)&desc); |
---|
| 701 | cpu_features[0] = desc[3]; |
---|
| 702 | cpu_features[1] = desc[2]; |
---|
| 703 | } |
---|
| 704 | |
---|
| 705 | /* |
---|
| 706 | * Get information from the extended cpuid leafs |
---|
| 707 | */ |
---|
| 708 | cpuid(0x80000000, 0, desc); |
---|
| 709 | |
---|
| 710 | lvl = (uint64_t)desc[0]; |
---|
| 711 | x86_printf("-> cpuid extended level: %Z\n", lvl); |
---|
| 712 | } |
---|
| 713 | |
---|
| 714 | /* -------------------------------------------------------------------------- */ |
---|
| 715 | |
---|
[162] | 716 | void cpu_attach(size_t lid) |
---|
[29] | 717 | { |
---|
[168] | 718 | /* Per-cluster structures */ |
---|
[29] | 719 | cpu_load_gdt(); |
---|
| 720 | cpu_load_idt(); |
---|
[168] | 721 | |
---|
| 722 | /* Per-cpu structures */ |
---|
[162] | 723 | cpu_create_tss(lid); |
---|
[166] | 724 | |
---|
| 725 | if (cpu_features[0] & CPUID_PSE) { |
---|
| 726 | lcr4(rcr4() | CR4_PSE); |
---|
| 727 | tlbflushg(); |
---|
| 728 | } else { |
---|
| 729 | /* |
---|
| 730 | * amd64 supports PSE by default, if it's not here we have a |
---|
| 731 | * problem |
---|
| 732 | */ |
---|
| 733 | x86_panic("PSE not supported"); |
---|
| 734 | } |
---|
[29] | 735 | } |
---|
| 736 | |
---|