| 1 | /* |
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| 2 | * hal_kentry.h - General values used in the different kernel entries |
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| 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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| 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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| 22 | #define T_PRIVINFLT 0 /* privileged instruction */ |
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| 23 | #define T_BPTFLT 1 /* breakpoint trap */ |
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| 24 | #define T_ARITHTRAP 2 /* arithmetic trap */ |
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| 25 | #define T_ASTFLT 3 /* asynchronous system trap */ |
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| 26 | #define T_PROTFLT 4 /* protection fault */ |
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| 27 | #define T_TRCTRAP 5 /* trace trap */ |
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| 28 | #define T_PAGEFLT 6 /* page fault */ |
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| 29 | #define T_ALIGNFLT 7 /* alignment fault */ |
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| 30 | #define T_DIVIDE 8 /* integer divide fault */ |
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| 31 | #define T_NMI 9 /* non-maskable interrupt */ |
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| 32 | #define T_OFLOW 10 /* overflow trap */ |
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| 33 | #define T_BOUND 11 /* bounds check fault */ |
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| 34 | #define T_DNA 12 /* device not available fault */ |
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| 35 | #define T_DOUBLEFLT 13 /* double fault */ |
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| 36 | #define T_FPOPFLT 14 /* fp coprocessor operand fetch fault */ |
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| 37 | #define T_TSSFLT 15 /* invalid tss fault */ |
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| 38 | #define T_SEGNPFLT 16 /* segment not present fault */ |
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| 39 | #define T_STKFLT 17 /* stack fault */ |
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| 40 | #define T_MCA 18 /* machine check */ |
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| 41 | #define T_XMM 19 /* SSE FP exception */ |
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| 42 | #define T_RESERVED 20 /* reserved fault base */ |
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| 43 | |
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| 44 | /* Trap's coming from user mode */ |
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| 45 | #define T_USER 0x100 |
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| 46 | |
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| 47 | #define TLSVAR(off) %gs:TLS_ ## off |
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| 48 | |
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| 49 | /* |
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| 50 | * Processor Status Longword. |
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| 51 | */ |
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| 52 | #define PSL_C 0x00000001 /* carry flag */ |
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| 53 | #define PSL_PF 0x00000004 /* parity flag */ |
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| 54 | #define PSL_AF 0x00000010 /* auxiliary carry flag */ |
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| 55 | #define PSL_Z 0x00000040 /* zero flag */ |
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| 56 | #define PSL_N 0x00000080 /* sign flag */ |
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| 57 | #define PSL_T 0x00000100 /* trap flag */ |
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| 58 | #define PSL_I 0x00000200 /* interrupt enable flag */ |
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| 59 | #define PSL_D 0x00000400 /* direction flag */ |
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| 60 | #define PSL_V 0x00000800 /* overflow flag */ |
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| 61 | #define PSL_IOPL 0x00003000 /* i/o privilege level */ |
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| 62 | #define PSL_NT 0x00004000 /* nested task */ |
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| 63 | #define PSL_RF 0x00010000 /* resume flag */ |
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| 64 | #define PSL_VM 0x00020000 /* virtual 8086 mode */ |
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| 65 | #define PSL_AC 0x00040000 /* alignment check flag */ |
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| 66 | #define PSL_VIF 0x00080000 /* virtual interrupt enable flag */ |
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| 67 | #define PSL_VIP 0x00100000 /* virtual interrupt pending flag */ |
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| 68 | #define PSL_ID 0x00200000 /* identification flag */ |
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| 69 | |
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| 70 | #define PSL_MBO 0x00000002 /* must be one bits */ |
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| 71 | #define PSL_MBZ 0xffc08028 /* must be zero bits */ |
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| 72 | |
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| 73 | #define PSL_USERSET (PSL_MBO | PSL_I) |
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| 74 | |
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| 75 | /* |
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| 76 | * Trap frame |
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| 77 | */ |
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| 78 | |
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| 79 | #define TF_REGSIZE (19 * 8) |
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| 80 | |
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| 81 | #define INTR_SAVE_REGS \ |
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| 82 | subq $TF_REGSIZE,%rsp ; \ |
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| 83 | movq %rax,TF_RAX(%rsp) ; \ |
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| 84 | movq %rbx,TF_RBX(%rsp) ; \ |
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| 85 | movq %rcx,TF_RCX(%rsp) ; \ |
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| 86 | movq %rdx,TF_RDX(%rsp) ; \ |
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| 87 | movq %rbp,TF_RBP(%rsp) ; \ |
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| 88 | movq %rdi,TF_RDI(%rsp) ; \ |
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| 89 | movq %rsi,TF_RSI(%rsp) ; \ |
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| 90 | movq %r8,TF_R8(%rsp) ; \ |
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| 91 | movq %r9,TF_R9(%rsp) ; \ |
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| 92 | movq %r10,TF_R10(%rsp) ; \ |
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| 93 | movq %r11,TF_R11(%rsp) ; \ |
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| 94 | movq %r12,TF_R12(%rsp) ; \ |
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| 95 | movq %r13,TF_R13(%rsp) ; \ |
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| 96 | movq %r14,TF_R14(%rsp) ; \ |
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| 97 | movq %r15,TF_R15(%rsp) ; \ |
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| 98 | /* movw %gs,TF_GS(%rsp) */ ; \ |
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| 99 | movw %fs,TF_FS(%rsp) ; \ |
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| 100 | movw %es,TF_ES(%rsp) ; \ |
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| 101 | movw %ds,TF_DS(%rsp) ; \ |
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| 102 | cld |
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| 103 | |
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| 104 | #define INTR_RESTORE_REGS \ |
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| 105 | movq TF_RAX(%rsp),%rax ; \ |
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| 106 | movq TF_RBX(%rsp),%rbx ; \ |
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| 107 | movq TF_RCX(%rsp),%rcx ; \ |
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| 108 | movq TF_RDX(%rsp),%rdx ; \ |
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| 109 | movq TF_RBP(%rsp),%rbp ; \ |
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| 110 | movq TF_RDI(%rsp),%rdi ; \ |
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| 111 | movq TF_RSI(%rsp),%rsi ; \ |
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| 112 | movq TF_R8(%rsp),%r8 ; \ |
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| 113 | movq TF_R9(%rsp),%r9 ; \ |
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| 114 | movq TF_R10(%rsp),%r10 ; \ |
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| 115 | movq TF_R11(%rsp),%r11 ; \ |
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| 116 | movq TF_R12(%rsp),%r12 ; \ |
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| 117 | movq TF_R13(%rsp),%r13 ; \ |
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| 118 | movq TF_R14(%rsp),%r14 ; \ |
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| 119 | movq TF_R15(%rsp),%r15 ; \ |
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| 120 | /* movw TF_GS(%rsp),%gs */ ; \ |
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| 121 | movw TF_FS(%rsp),%fs ; \ |
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| 122 | movw TF_ES(%rsp),%es ; \ |
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| 123 | movw TF_DS(%rsp),%ds ; \ |
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| 124 | addq $TF_REGSIZE,%rsp ; \ |
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| 125 | cld |
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| 126 | |
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| 127 | #ifndef x86_ASM |
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| 128 | |
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| 129 | /* |
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| 130 | * The x86_64 CPU trap frame. !!WARNING!! The size of this structure must be |
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| 131 | * exactly TF_SIZE. |
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| 132 | */ |
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| 133 | typedef struct hal_trapframe_s { |
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| 134 | /* Pushed by INTR_SAVE_REGS */ |
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| 135 | uint64_t tf_rax; |
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| 136 | uint64_t tf_rbx; |
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| 137 | uint64_t tf_rcx; |
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| 138 | uint64_t tf_rdx; |
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| 139 | uint64_t tf_rdi; |
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| 140 | uint64_t tf_rsi; |
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| 141 | uint64_t tf_rbp; |
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| 142 | uint64_t tf_r8; |
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| 143 | uint64_t tf_r9; |
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| 144 | uint64_t tf_r10; |
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| 145 | uint64_t tf_r11; |
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| 146 | uint64_t tf_r12; |
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| 147 | uint64_t tf_r13; |
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| 148 | uint64_t tf_r14; |
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| 149 | uint64_t tf_r15; |
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| 150 | uint64_t tf_gs; |
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| 151 | uint64_t tf_fs; |
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| 152 | uint64_t tf_es; |
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| 153 | uint64_t tf_ds; |
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| 154 | |
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| 155 | /* Pushed by the ISR */ |
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| 156 | uint64_t tf_trapno; |
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| 157 | |
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| 158 | /* Pushed by the hardware if exception */ |
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| 159 | uint64_t tf_err; /* in fact, this one may not... */ |
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| 160 | uint64_t tf_rip; |
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| 161 | uint64_t tf_cs; |
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| 162 | uint64_t tf_rflags; |
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| 163 | |
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| 164 | /* Always pushed by the hardware */ |
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| 165 | uint64_t tf_rsp; |
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| 166 | uint64_t tf_ss; |
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| 167 | } hal_trapframe_t; |
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| 168 | |
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| 169 | typedef struct hal_cpu_context_s { |
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| 170 | uint64_t ctx_rsp0; |
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| 171 | uint64_t ctx_tf; |
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| 172 | uint64_t ctx_intr; |
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| 173 | hal_trapframe_t ctx_hidden_tf; |
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| 174 | } hal_cpu_context_t; |
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| 175 | |
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| 176 | #else |
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| 177 | |
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| 178 | /* Offsets in the trapframe structure */ |
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| 179 | #define TF_RAX 0 |
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| 180 | #define TF_RBX 8 |
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| 181 | #define TF_RCX 16 |
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| 182 | #define TF_RDX 24 |
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| 183 | #define TF_RDI 32 |
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| 184 | #define TF_RSI 40 |
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| 185 | #define TF_RBP 48 |
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| 186 | #define TF_R8 56 |
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| 187 | #define TF_R9 64 |
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| 188 | #define TF_R10 72 |
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| 189 | #define TF_R11 80 |
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| 190 | #define TF_R12 88 |
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| 191 | #define TF_R13 96 |
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| 192 | #define TF_R14 104 |
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| 193 | #define TF_R15 112 |
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| 194 | #define TF_GS 120 |
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| 195 | #define TF_FS 128 |
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| 196 | #define TF_ES 136 |
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| 197 | #define TF_DS 144 |
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| 198 | |
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| 199 | /* Size of the trapframe structure */ |
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| 200 | #define TF_SIZE 208 |
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| 201 | |
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| 202 | /* Offsets in the context structure */ |
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| 203 | #define CTX_RSP0 0 |
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| 204 | #define CTX_TF 8 |
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| 205 | #define CTX_INTR 16 |
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| 206 | |
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| 207 | #endif |
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| 208 | |
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