[25] | 1 | /* |
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[46] | 2 | * hal_special.c - implementation of TLS API for x86_64 |
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[71] | 3 | * |
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[46] | 4 | * Copyright (c) 2017 Maxime Villard |
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[71] | 5 | * |
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[46] | 6 | * This file is part of ALMOS-MKH. |
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[25] | 7 | * |
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[46] | 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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[25] | 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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[46] | 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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[25] | 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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| 18 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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| 22 | #include <hal_types.h> |
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[82] | 23 | #include <hal_apic.h> |
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[25] | 24 | #include <hal_special.h> |
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[46] | 25 | #include <hal_register.h> |
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| 26 | #include <hal_internal.h> |
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[25] | 27 | |
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[102] | 28 | #include <core.h> |
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| 29 | #include <thread.h> |
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| 30 | |
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[25] | 31 | struct thread_s; |
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| 32 | |
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[138] | 33 | struct cpu_info { |
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[46] | 34 | void *ci_self; |
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[138] | 35 | uint64_t apic_fake_status; |
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[46] | 36 | uint32_t ci_gid; |
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| 37 | uint32_t ci_lid; |
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| 38 | struct thread_s *ci_thr; |
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[138] | 39 | } __packed; |
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| 40 | typedef struct cpu_info cpu_info_t; |
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[46] | 41 | |
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| 42 | cpu_info_t cpu0 __in_kdata; |
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| 43 | |
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| 44 | cpu_info_t *curcpu() |
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| 45 | { |
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| 46 | cpu_info_t *ci; |
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| 47 | |
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| 48 | __asm volatile("movq %%gs:%1, %0" : |
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| 49 | "=r" (ci) : |
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| 50 | "m" |
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| 51 | (*(cpu_info_t * const *)offsetof(cpu_info_t, ci_self))); |
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| 52 | return ci; |
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| 53 | } |
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| 54 | |
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| 55 | static void hal_tls_load_cpu(cpu_info_t *ci) |
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| 56 | { |
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| 57 | wrmsr(MSR_FSBASE, 0); |
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| 58 | wrmsr(MSR_GSBASE, (uint64_t)ci); |
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| 59 | wrmsr(MSR_KERNELGSBASE, 0); |
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| 60 | } |
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| 61 | |
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| 62 | void hal_tls_init_cpu0() |
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| 63 | { |
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| 64 | cpu_info_t *ci = &cpu0; |
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| 65 | |
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| 66 | memset(ci, 0, sizeof(cpu_info_t)); |
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| 67 | |
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| 68 | ci->ci_self = ci; |
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| 69 | ci->ci_gid = hal_lapic_gid(); |
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| 70 | ci->ci_lid = 0; /* XXX */ |
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| 71 | |
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| 72 | hal_tls_load_cpu(ci); |
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| 73 | } |
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| 74 | |
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[25] | 75 | gid_t hal_get_gid() |
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| 76 | { |
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[46] | 77 | return curcpu()->ci_gid; |
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[25] | 78 | } |
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| 79 | |
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[125] | 80 | cycle_t hal_time_stamp() |
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| 81 | { |
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| 82 | return rdtsc(); |
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| 83 | } |
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| 84 | |
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[102] | 85 | uint64_t hal_get_cycles() |
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[25] | 86 | { |
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[102] | 87 | uint64_t cycles; |
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| 88 | core_t *core = CURRENT_THREAD->core; |
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| 89 | |
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| 90 | /* |
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| 91 | * Put the value of the TSC everywhere |
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| 92 | */ |
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| 93 | cycles = rdtsc(); |
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| 94 | core->time_stamp = cycles; |
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| 95 | core->cycles = cycles; |
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| 96 | |
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| 97 | return cycles; |
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[25] | 98 | } |
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| 99 | |
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[102] | 100 | struct thread_s *hal_get_current_thread() |
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[25] | 101 | { |
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[46] | 102 | return curcpu()->ci_thr; |
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[25] | 103 | } |
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| 104 | |
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| 105 | void hal_set_current_thread( struct thread_s * thread ) |
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[71] | 106 | { |
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[46] | 107 | curcpu()->ci_thr = thread; |
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[25] | 108 | } |
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| 109 | |
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[138] | 110 | uint8_t hal_get_apic_fake_status() |
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| 111 | { |
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| 112 | return curcpu()->apic_fake_status; |
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| 113 | } |
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| 114 | |
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[46] | 115 | /* -------------------------------------------------------------------------- */ |
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| 116 | |
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[25] | 117 | void hal_fpu_enable() |
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| 118 | { |
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[46] | 119 | x86_panic((char *)__func__); |
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[25] | 120 | } |
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| 121 | |
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| 122 | void hal_fpu_disable() |
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| 123 | { |
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[46] | 124 | x86_panic((char *)__func__); |
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[25] | 125 | } |
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| 126 | |
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| 127 | uint32_t hal_get_stack() |
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| 128 | { |
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[46] | 129 | x86_panic((char *)__func__); |
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[25] | 130 | return 0; |
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| 131 | } |
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| 132 | |
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| 133 | uint32_t hal_set_stack( void * new_val ) |
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| 134 | { |
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[46] | 135 | x86_panic((char *)__func__); |
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[25] | 136 | return 0; |
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| 137 | } |
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| 138 | |
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| 139 | uint32_t hal_get_bad_vaddr() |
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| 140 | { |
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[46] | 141 | x86_panic((char *)__func__); |
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[25] | 142 | return 0; |
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| 143 | } |
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| 144 | |
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| 145 | uint32_t hal_uncached_read( uint32_t * ptr ) |
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| 146 | { |
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[46] | 147 | x86_panic((char *)__func__); |
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[25] | 148 | return 0; |
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| 149 | } |
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| 150 | |
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| 151 | void hal_invalid_dcache_line( void * ptr ) |
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| 152 | { |
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[46] | 153 | x86_panic((char *)__func__); |
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[25] | 154 | } |
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| 155 | |
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[124] | 156 | void hal_fence() |
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[25] | 157 | { |
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[125] | 158 | mfence(); |
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[25] | 159 | } |
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| 160 | |
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| 161 | void hal_rdbar() |
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| 162 | { |
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[46] | 163 | x86_panic((char *)__func__); |
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[25] | 164 | } |
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| 165 | |
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| 166 | void hal_core_sleep() |
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| 167 | { |
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[46] | 168 | x86_panic((char *)__func__); |
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[25] | 169 | } |
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| 170 | |
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| 171 | void hal_fixed_delay( uint32_t delay ) |
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[71] | 172 | { |
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[46] | 173 | x86_panic((char *)__func__); |
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[25] | 174 | } |
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| 175 | |
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| 176 | void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code, |
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| 177 | intptr_t * mmu_ins_bad_vaddr, |
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| 178 | intptr_t * mmu_dat_excp_code, |
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| 179 | intptr_t * mmu_dat_bad_vaddr ) |
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| 180 | { |
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[46] | 181 | x86_panic((char *)__func__); |
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[25] | 182 | } |
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