1 | /* |
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2 | * soclib_bdv.c - soclib simple block device driver implementation. |
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3 | * |
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4 | * Author Alain Greiner (2016) |
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5 | * |
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6 | * Copyright (c) UPMC Sorbonne Universites |
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7 | * |
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8 | * This file is part of ALMOS-MKH. |
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9 | * |
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10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License as published by |
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12 | * the Free Software Foundation; version 2.0 of the License. |
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13 | * |
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14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU General Public License |
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20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 | */ |
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23 | |
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24 | #include <chdev.h> |
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25 | #include <dev_ioc.h> |
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26 | #include <soclib_bdv.h> |
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27 | #include <thread.h> |
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28 | #include <spinlock.h> |
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29 | |
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30 | #include <hal_internal.h> |
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31 | |
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32 | #define PIO_ATA_CBR_BASE 0x1F0 |
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33 | # define ATA_DATA 0x000 |
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34 | # define ATA_ERRFEAT 0x001 /* two regs */ |
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35 | # define ATA_SCR 0x002 |
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36 | # define ATA_SNR 0x003 /* lba0 */ |
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37 | # define ATA_CLR 0x004 /* lba1 */ |
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38 | # define ATA_CHR 0x005 /* lba2 */ |
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39 | # define ATA_DHR 0x006 /* drive | lba3 */ |
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40 | # define ATA_SR 0x007 |
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41 | # define ATA_SR_ERR 0x01 |
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42 | # define ATA_SR_IDX 0x02 |
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43 | # define ATA_SR_CORR 0x04 |
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44 | # define ATA_SR_DRQ 0x08 |
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45 | # define ATA_SR_DSC 0x10 |
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46 | # define ATA_SR_DF 0x20 |
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47 | # define ATA_SR_DRDY 0x40 |
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48 | # define ATA_SR_BSY 0x80 |
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49 | # define ATA_CR 0x007 /* two regs */ |
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50 | |
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51 | #define ATA_CMD_READ_SECTORS_RETRY 0x20 |
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52 | #define ATA_CMD_READ_SECTORS_NORETRY 0x21 |
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53 | #define ATA_CMD_WRITE_SECTORS_RETRY 0x30 |
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54 | #define ATA_CMD_WRITE_SECTORS_NORETRY 0x31 |
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55 | #define ATA_CMD_IDENTIFY 0xEC |
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56 | |
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57 | static inline uint16_t ata_data_read() |
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58 | { |
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59 | return in16(PIO_ATA_CBR_BASE + ATA_DATA); |
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60 | } |
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61 | |
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62 | static inline void ata_data_write(uint16_t val) |
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63 | { |
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64 | out16(PIO_ATA_CBR_BASE + ATA_DATA, val); |
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65 | } |
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66 | |
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67 | static inline uint8_t ata_cbr_read(uint32_t reg) |
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68 | { |
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69 | return in8(PIO_ATA_CBR_BASE + reg); |
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70 | } |
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71 | |
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72 | static inline void ata_cbr_write(uint32_t reg, uint8_t val) |
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73 | { |
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74 | out8(PIO_ATA_CBR_BASE + reg, val); |
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75 | } |
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76 | |
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77 | static inline int ata_wait() |
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78 | { |
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79 | uint8_t status; |
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80 | |
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81 | while (!(ata_cbr_read(ATA_SR) & ATA_SR_DRQ)); |
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82 | status = ata_cbr_read(ATA_SR); |
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83 | return ((status & ATA_SR_ERR) ? -1 : 0); |
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84 | } |
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85 | |
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86 | static void ata_prepare(uint8_t slave, uint32_t lba, uint8_t count) |
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87 | { |
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88 | ata_cbr_write(ATA_ERRFEAT, 0x00); /* NULL byte to port 0x1F1 */ |
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89 | ata_cbr_write(ATA_SCR, count); /* sector count */ |
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90 | |
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91 | /* set the lba */ |
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92 | ata_cbr_write(ATA_SNR, (lba >> 0) & 0xFF); |
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93 | ata_cbr_write(ATA_CLR, (lba >> 8) & 0xFF); |
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94 | ata_cbr_write(ATA_CHR, (lba >> 16)& 0xFF); |
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95 | |
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96 | /* set the drive and lba3 */ |
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97 | ata_cbr_write(ATA_DHR, 0xE0 | (slave << 4) | ((lba >> 24) & 0x0F)); |
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98 | } |
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99 | |
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100 | static int ata_read(uint8_t count, char *buf) |
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101 | { |
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102 | uint16_t tmpword; |
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103 | int idx; |
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104 | |
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105 | /* wait for the drive to signal that it's ready */ |
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106 | if (ata_wait() == -1) |
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107 | return -1; |
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108 | |
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109 | for (idx = 0; idx < 256 * count; idx++) { |
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110 | tmpword = ata_data_read(); |
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111 | buf[idx * 2] = (uint8_t)(tmpword & 0xFF); |
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112 | buf[idx * 2 + 1] = (uint8_t)(tmpword >> 8); |
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113 | } |
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114 | |
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115 | return 0; |
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116 | } |
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117 | |
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118 | static int ata_write(uint8_t count, char *buf) |
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119 | { |
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120 | uint16_t tmpword; |
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121 | int idx; |
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122 | |
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123 | /* wait for the drive to signal that it's ready */ |
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124 | if (ata_wait() == -1) |
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125 | return -1; |
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126 | |
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127 | for (idx = 0; idx < 256 * count; idx++) { |
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128 | tmpword = (buf[idx * 2 + 1] << 8) | buf[idx * 2]; |
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129 | ata_data_write(tmpword); |
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130 | } |
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131 | |
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132 | return 0; |
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133 | } |
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134 | |
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135 | static uint16_t bswap16(uint16_t x) |
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136 | { |
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137 | return ((x << 8) & 0xFF00) | ((x >> 8) & 0x00FF); |
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138 | } |
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139 | |
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140 | static void ata_init() |
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141 | { |
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142 | uint8_t id[512]; |
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143 | uint16_t tmpw, *p; |
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144 | size_t idx; |
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145 | char *model; |
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146 | uint8_t ncyl; |
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147 | int ret; |
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148 | |
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149 | ata_prepare(0, 0, 0); |
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150 | ata_cbr_write(ATA_CR, ATA_CMD_IDENTIFY); |
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151 | |
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152 | /* wait for the drive to signal that it's ready */ |
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153 | ret = ata_wait(); |
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154 | if (ret == -1) |
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155 | x86_printf("-> unable to identify ATA\n"); |
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156 | |
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157 | for (idx = 0; idx < 256; idx++) { |
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158 | tmpw = ata_data_read(); |
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159 | id[idx * 2] = (uint8_t)((tmpw >> 0) & 0xFF); |
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160 | id[idx * 2 + 1] = (uint8_t)((tmpw >> 8) & 0xFF); |
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161 | } |
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162 | |
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163 | ncyl = id[0] & 0x1; |
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164 | x86_printf("-> cyl: %z\n", (uint64_t)ncyl); |
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165 | |
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166 | for (idx = 27*2; idx < 46*2; idx += 2) { |
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167 | p = (uint16_t *)(&id[idx]); |
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168 | *p = bswap16(*p); |
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169 | } |
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170 | |
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171 | model = &id[27*2]; |
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172 | id[46*2] = '\0'; |
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173 | x86_printf("-> ATA model: '%s'\n", model); |
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174 | } |
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175 | |
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176 | /* -------------------------------------------------------------------------- */ |
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177 | |
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178 | |
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179 | void soclib_bdv_init( chdev_t * chdev ) |
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180 | { |
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181 | ata_init(); |
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182 | } |
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183 | |
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184 | void __attribute__ ((noinline)) soclib_bdv_cmd( xptr_t th_xp ) |
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185 | { |
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186 | |
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187 | x86_panic("myshit!\n"); |
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188 | |
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189 | uint32_t cmd_type; // IOC_READ / IOC_WRITE / IOC_SYNC_READ |
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190 | uint32_t lba; // command argument |
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191 | uint32_t count; // command argument |
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192 | xptr_t buf_xp; // command argument |
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193 | |
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194 | // get client thread cluster and local pointer |
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195 | cxy_t th_cxy = GET_CXY( th_xp ); |
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196 | thread_t * th_ptr = (thread_t *)GET_PTR( th_xp ); |
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197 | |
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198 | // get command arguments and extended pointer on IOC device |
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199 | cmd_type = hal_remote_lw ( XPTR( th_cxy , &th_ptr->command.ioc.type ) ); |
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200 | lba = hal_remote_lw ( XPTR( th_cxy , &th_ptr->command.ioc.lba ) ); |
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201 | count = hal_remote_lw ( XPTR( th_cxy , &th_ptr->command.ioc.count ) ); |
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202 | buf_xp = (xptr_t)hal_remote_lwd( XPTR( th_cxy , &th_ptr->command.ioc.buf_xp ) ); |
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203 | |
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204 | /* execute operation */ |
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205 | ata_prepare(0, lba, count); |
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206 | if (cmd_type == IOC_WRITE) { |
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207 | ata_cbr_write(ATA_CR, ATA_CMD_WRITE_SECTORS_RETRY); |
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208 | } else { |
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209 | ata_cbr_write(ATA_CR, ATA_CMD_READ_SECTORS_RETRY); |
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210 | } |
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211 | |
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212 | /* waiting policy depends on the command type */ |
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213 | if (cmd_type == IOC_SYNC_READ) { |
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214 | ata_read(count, (char *)buf_xp); |
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215 | } else { |
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216 | x86_panic("!IOC_SYNC_READ not supported"); |
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217 | } |
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218 | } |
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219 | |
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220 | void __attribute__ ((noinline)) soclib_bdv_isr( chdev_t * chdev ) |
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221 | { |
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222 | |
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223 | } |
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224 | |
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