source: trunk/hal/x86_64/hal_boot.h @ 36

Last change on this file since 36 was 35, checked in by max@…, 7 years ago

Update:

  • Introduce a basic VM manager in hal_gpt.c, to create the initial page tree for cluster0.
  • Locate the ACPI RSDP table, which involves entering the PA into cluster0's VA space.

The definitions are still a bit messy, but they will be reorganized later.
File size: 4.5 KB
RevLine 
[25]1/*
2 * hal_boot.h - General values used by the boot procedure
3 *
[29]4 * Copyright (c) 2017 Maxime Villard
[25]5 *
[29]6 * This file is part of ALMOS-MKH.
[25]7 *
[29]8 * ALMOS-MKH is free software; you can redistribute it and/or modify it
[25]9 * under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2.0 of the License.
11 *
[29]12 * ALMOS-MKH is distributed in the hope that it will be useful, but
[25]13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
[29]18 * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
[25]19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#define PAGE_SIZE       4096
23#define PGOFSET         (PAGE_SIZE-1)
24#define PGSHIFT         12
25
26#define KERNBASE        0xffffffff80000000
27#define KERNBASE_HI     0xffffffff
28#define KERNBASE_LO     0x80000000
29
30#define KERNTEXTOFF     0xffffffff80200000
31#define KERNTEXTOFF_HI  0xffffffff
32#define KERNTEXTOFF_LO  0x80200000
33
34/* -------------------------------------------------------------------------- */
35
[29]36#define ASM_ALIGN_TEXT  .align 16
37#define ASM_ENTRY(x) \
38        .text; ASM_ALIGN_TEXT; .globl x; .type x,@function; x:
39
40/* -------------------------------------------------------------------------- */
41
[25]42#define PSL_MBO         0x00000002
43
44#define STKPAGES        4
[29]45#define STKSIZE         (PAGE_SIZE * STKPAGES)
[25]46
47#define NKL4_KIMG_ENTRIES       1
48#define NKL3_KIMG_ENTRIES       1
49#define NKL2_KIMG_ENTRIES       32
50
51/* -------------------------------------------------------------------------- */
52
53#define L1_SHIFT        12
54#define L2_SHIFT        21
55#define L3_SHIFT        30
56#define L4_SHIFT        39
57#define NBPD_L1         (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
58#define NBPD_L2         (1UL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
59#define NBPD_L3         (1UL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
60#define NBPD_L4         (1UL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
61
62#define L4_MASK         0x0000ff8000000000
63#define L3_MASK         0x0000007fc0000000
64#define L2_MASK         0x000000003fe00000
65#define L1_MASK         0x00000000001ff000
66
67#define L4_FRAME        L4_MASK
68#define L3_FRAME        (L4_FRAME|L3_MASK)
69#define L2_FRAME        (L3_FRAME|L2_MASK)
70#define L1_FRAME        (L2_FRAME|L1_MASK)
71
72#define PDE_SIZE        8
73
74/* PDE/PTE bits. */
75#define PG_V            0x0000000000000001      /* valid */
76#define PG_RO           0x0000000000000000      /* read-only */
77#define PG_RW           0x0000000000000002      /* read-write */
78#define PG_u            0x0000000000000004      /* user accessible */
79#define PG_PROT         0x0000000000000006
80#define PG_WT           0x0000000000000008      /* write-through */
81#define PG_N            0x0000000000000010      /* non-cacheable */
82#define PG_U            0x0000000000000020      /* used */
83#define PG_M            0x0000000000000040      /* modified */
84#define PG_PAT          0x0000000000000080      /* PAT (on pte) */
85#define PG_PS           0x0000000000000080      /* 2MB page size (on pde) */
86#define PG_G            0x0000000000000100      /* not flushed */
87#define PG_AVAIL1       0x0000000000000200
88#define PG_AVAIL2       0x0000000000000400
89#define PG_AVAIL3       0x0000000000000800
90#define PG_LGPAT        0x0000000000001000      /* PAT on large pages */
91#define PG_FRAME        0x000ffffffffff000
92#define PG_NX           0x8000000000000000
93
94#define PG_2MFRAME      0x000fffffffe00000      /* large (2M) page frame mask */
95#define PG_1GFRAME      0x000fffffc0000000      /* large (1G) page frame mask */
96#define PG_LGFRAME      PG_2MFRAME
97
98/* Short forms of protection codes. */
99#define PG_KR           0x0000000000000000      /* kernel read-only */
100#define PG_KW           0x0000000000000002      /* kernel read-write */
101
102/* -------------------------------------------------------------------------- */
103
104#define IOM_BEGIN       0x0a0000                /* Start of I/O Memory "hole" */
105#define IOM_END         0x100000                /* End of I/O Memory "hole" */
106#define IOM_SIZE        (IOM_END - IOM_BEGIN)
107
108/* -------------------------------------------------------------------------- */
109
110#define L4_SLOT_PTE             255
111#define L4_SLOT_KERN            256
112#define L4_SLOT_KERNBASE        511
113
[29]114/*
115 * L3 = (KERNBASE % NBPD_L4) / NBPD_L3
116 * L2 = (KERNBASE % NBPD_L3) / NBPD_L2
117 */
118#define L3_SLOT_KERNBASE        510
119#define L2_SLOT_KERNBASE        0
120
[25]121#define PDIR_SLOT_KERN  L4_SLOT_KERN
122#define PDIR_SLOT_PTE   L4_SLOT_PTE
123
[35]124#define PTE_BASE        ((pt_entry_t *)(L4_SLOT_PTE * NBPD_L4))
125#define L1_BASE PTE_BASE
126#define L2_BASE ((pt_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
127#define L3_BASE ((pt_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
128#define L4_BASE ((pt_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
129
130#define NPDPG   (PAGE_SIZE / sizeof (pt_entry_t))
131
132#define CLUSTER0_MIN_VA 0xffff800000000000
133#define CLUSTER0_MAX_VA 0xffff800100000000 /* MIN + 4GB */
134
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