1 | /* |
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2 | * hal_devices_init.c - Devices intialization operations for the TSAR architecture |
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3 | * |
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4 | * Authors Ghassan Almaless (2008,2009,2010,2011,2012) |
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5 | * Mohamed Lamine Karaoui (2015) |
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6 | * Alain Greiner (2016) |
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7 | |
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8 | * Copyright (c) UPMC Sorbonne Universites |
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9 | * |
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10 | * This file is part of ALMOS-MKH. |
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11 | * |
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12 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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13 | * under the terms of the GNU General Public License as published by |
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14 | * the Free Software Foundation; version 2.0 of the License. |
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15 | * |
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16 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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19 | * General Public License for more details. |
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20 | * |
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21 | * You should have received a copy of the GNU General Public License |
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22 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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23 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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24 | */ |
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25 | |
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26 | #include <config.h> |
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27 | #include <types.h> |
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28 | #include <list.h> |
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29 | #include <bits.h> |
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30 | #include <cpu.h> |
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31 | #include <system.h> |
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32 | #include <cluster.h> |
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33 | #include <chdev.h> |
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34 | #include <driver.h> |
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35 | #include <thread.h> |
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36 | #include <process.h> |
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37 | #include <kmem.h> |
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38 | #include <ppm.h> |
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39 | #include <pmm.h> |
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40 | #include <page.h> |
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41 | #include <kdmsg.h> |
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42 | #include <devfs.h> |
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43 | #include <drvdb.h> |
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44 | #include <boot-info.h> |
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45 | #include <soclib_xicu.h> |
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46 | #include <soclib_iopic.h> |
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47 | #define _ARCH_BIB_SIGNATURE_ |
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48 | #include <arch-bib.h> |
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49 | |
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50 | #define die(args...) do {boot_dmsg(args); while(1);} while(0) |
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51 | |
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52 | #define ICU_MASK 0xFFFFFFFF // interrupt enabled for first 32 devices |
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53 | #define KATTR (PMM_HUGE | PMM_READ | PMM_WRITE | PMM_EXECUTE | PMM_CACHED | PMM_GLOBAL | PMM_DIRTY | PMM_ACCESSED) |
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54 | #define KDEV_ATTR (PMM_READ | PMM_WRITE | PMM_GLOBAL | PMM_DIRTY | PMM_ACCESSED) |
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55 | |
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56 | |
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57 | /********************************************************************************************* |
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58 | * This function set the various masks for the XCU device in the local cluster. |
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59 | * It should be executed by core[0] after the local cluster manager initialisation, |
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60 | * and after devices initialisation. The général policy is the following: |
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61 | * - PTI : it routes one PTI per core (with index = lid) for TICK. |
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62 | * - WTI : it routes one WTI per core (with index = lid) for wakup. |
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63 | * - HWI : it routes all local HWI to core[0]. |
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64 | ********************************************************************************************/ |
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65 | void hal_xcu_set_mask() |
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66 | { |
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67 | uint32_t lid; |
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68 | cluster_t * cluster; // pointer on local cluster manager |
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69 | uint32_t cores; // number of cores in cluster |
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70 | device_t * xcu; // pointer on local XCU device descriptor |
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71 | uint32_t hwi_mask; // HWI mask for XCU |
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72 | uint32_t hwi_index; // HWI index in XCU |
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73 | list_entry_t * iter; // iterator to scan the device list |
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74 | device_t * dev; // pointer on local device descriptor |
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75 | dev_type_t type; // device type |
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76 | |
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77 | cluster = LOCAL_CLUSTER; |
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78 | cores = cluster->cores_nr; |
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79 | xcu = cluster->xcu; |
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80 | |
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81 | // loop on all local devices to compute the hwi_mask |
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82 | hwi_mask = 0; |
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83 | hwi_index = 0; |
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84 | LIST_FOREACH( cluster->devlist , iter ) |
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85 | { |
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86 | dev = LIST_ELEMENT( iter , device_t , list ); |
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87 | type = dev->type; |
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88 | |
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89 | // only replicated devices MMC and MWR generate HWI |
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90 | if( (type == DEV_TYPE_MMC) || (type == DEV_TYPE_MWR) ) |
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91 | { |
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92 | hwi_mask = hwi_mask |= (1<<hwi_index); |
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93 | hwi_index++; |
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94 | } |
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95 | } |
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96 | |
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97 | // set the three XCU masks |
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98 | for( lid = 0 ; lid < cores ; lid++ ) |
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99 | { |
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100 | xcu_set_mask( xcu , (1<<lid) , XCU_PTI_TYPE , lid ); |
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101 | xcu_set_mask( xcu , (1<<lid) , XCU_WTI_TYPE , lid ); |
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102 | if( lid == 0 ) |
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103 | { |
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104 | xcu_set_mask( xcu , hwi_mask , XCU_HWI_TYPE , lid ); |
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105 | } |
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106 | } |
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107 | } // end hal_xcu_set_mask() |
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108 | |
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109 | |
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110 | /********************************************************************************************* |
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111 | * This function returns a pointer on a cluster descriptor from the drvid. |
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112 | ********************************************************************************************/ |
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113 | device_t * hal_dev_locate( list_entry_t * devlist_root, |
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114 | uint32_t drvid ) |
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115 | { |
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116 | struct list_entry *iter; |
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117 | struct device_s *dev; |
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118 | |
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119 | list_foreach(devlist_root, iter) |
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120 | { |
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121 | dev = list_element(iter, struct device_s, list); |
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122 | if(dev->op.drvid == drvid) |
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123 | return dev; |
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124 | } |
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125 | |
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126 | return NULL; |
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127 | } |
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128 | |
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129 | /********************************************************************************************* |
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130 | * This function register all detected devices in given cluster. |
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131 | ********************************************************************************************/ |
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132 | void hal_dev_register( cluster_t * cluster, |
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133 | cluster_entry_s * entry ) |
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134 | { |
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135 | device_t * xicu; |
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136 | list_entry_t * iter; |
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137 | device_t * dev; |
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138 | cpu_t * cpu_ptr; |
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139 | uint32_t cpu; |
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140 | error_t err; |
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141 | |
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142 | xicu = hal_dev_locate(&entry->devlist, SOCLIB_XICU_ID); |
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143 | dev = hal_dev_locate(&entry->devlist, SOCLIB_DMA_ID); |
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144 | |
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145 | hal_entrys[entry->cxy].xicu = xicu; |
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146 | hal_entrys[entry->cxy].dma = dev; |
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147 | |
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148 | if((cluster->id == entry->cxy) && (xicu == NULL)) |
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149 | die("[ERROR]\tNo XICU is found for cluster %d\n", entry->cxy); |
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150 | |
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151 | //only local cluster get to set the irq |
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152 | if(cluster->id != entry->cxy) |
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153 | return; |
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154 | |
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155 | list_foreach((&entry->devlist), iter) |
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156 | { |
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157 | dev = list_element(iter, struct device_s, list); |
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158 | |
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159 | if((dev != xicu) && (dev->irq != -1)) |
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160 | { |
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161 | err = xicu->op.icu.bind(xicu, dev); |
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162 | |
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163 | if(err) |
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164 | die("[ERROR]\tFailed to bind device %s, irq %d, on xicu %s @%x [ err %d ]\n", |
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165 | dev->name, dev->irq, xicu->name, xicu, err); |
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166 | } |
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167 | |
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168 | } |
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169 | |
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170 | if(cluster->id != entry->cxy) |
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171 | return; |
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172 | |
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173 | hal_xicu_set_mask(cluster, xicu); |
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174 | |
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175 | for(cpu = 0; cpu < cluster->cpu_nr; cpu++) |
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176 | { |
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177 | cpu_ptr = &cluster->cpu_tbl[cpu]; |
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178 | hal_cpu_set_irq_entry(cpu_ptr, 0, &xicu->action); |
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179 | } |
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180 | } // end hal_dev_register() |
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181 | |
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182 | ////////////////////////////////////////////////// |
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183 | void hal_dev_iopic_register( cluster_t * cluster, |
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184 | struct cluster_entry_s *entry); |
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185 | |
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186 | /** HAL-ARCH CPUs & Clusters counters */ |
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187 | static global_t hal_onln_cpus_nr; |
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188 | static global_t hal_cpus_per_cluster; |
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189 | static global_t hal_onln_clusters_nr; |
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190 | static global_t hal_boot_cxy_; |
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191 | |
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192 | /**/ |
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193 | struct hal_entry_s hal_entrys[CLUSTER_NR]; |
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194 | global_t __current_cxy; |
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195 | |
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196 | /** Return Platform CPUs Online Number */ |
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197 | inline uint32_t hal_onln_cpu_nr(void) |
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198 | { |
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199 | return hal_onln_cpus_nr.value; |
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200 | } |
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201 | |
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202 | /** Return Platform Clsuters Online Number */ |
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203 | inline uint32_t hal_onln_cluster_nr(void) |
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204 | { |
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205 | return hal_onln_clusters_nr.value; |
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206 | } |
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207 | |
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208 | inline uint32_t hal_cpu_per_cluster(void) |
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209 | { |
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210 | return hal_cpus_per_cluster.value; |
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211 | } |
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212 | |
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213 | inline cxy_t hal_boot_cxy(void) |
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214 | { |
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215 | return hal_boot_cxy_.value; |
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216 | } |
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217 | |
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218 | extern uint32_t cpu_gid_tbl[CPU_PER_CLUSTER] CACHELINE; |
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219 | |
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220 | inline void cpu_gid_tbl_init(struct boot_info_s *info) |
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221 | { |
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222 | uint32_t i; |
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223 | uint32_t cpu_nr; |
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224 | |
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225 | cpu_nr = info->local_onln_cpu_nr; |
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226 | |
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227 | if(CPU_PER_CLUSTER < cpu_nr) |
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228 | while(1);//die("ERROR: This Kernel Is Compiled For only %d cpus per cluster\n", CPU_PER_CLUSTER); |
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229 | |
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230 | for(i=0; i < cpu_nr; i++) |
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231 | cpu_gid_tbl[i] = hal_cpu_gid(info->local_cluster_id, i); |
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232 | } |
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233 | |
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234 | cxy_t Arch_cxy_To_Almos_cxy[CLUSTER_NR]; //address of info->hal_cxy_to_cxy array |
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235 | |
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236 | static void fill_hal_cxy_to_almos_array(struct hal_bib_header_s *header) |
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237 | { |
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238 | int i; |
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239 | cluster_info_t *cluster_tbl; |
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240 | |
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241 | cluster_tbl = (cluster_info_t*)((uint32_t)header + sizeof(header_info_t)); |
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242 | assert(CLUSTER_NR >= header->onln_clstr_nr); |
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243 | |
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244 | for(i = 0; i < header->onln_clstr_nr; i++) |
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245 | { |
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246 | if(cluster_tbl[i].hal_cxy >= CLUSTER_NR) |
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247 | continue; |
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248 | Arch_cxy_To_Almos_cxy[cluster_tbl[i].hal_cxy] = cluster_tbl[i].cxy; |
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249 | |
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250 | } |
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251 | } |
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252 | |
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253 | /********************************************************************************************* |
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254 | * This function makes the kernel virtual mapping of all hardware memory banks. |
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255 | * Initialize the boot table entries. |
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256 | ********************************************************************************************/ |
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257 | void hal_state_init( boot_info_t * info ) |
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258 | { |
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259 | struct process_s *process; |
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260 | struct thread_s *this; |
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261 | header_info_t *header; |
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262 | cluster_info_t *clusters; |
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263 | cluster_info_t *cluster_ptr; |
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264 | dev_info_t *dev_tbl; |
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265 | uint32_t vaddr_start; |
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266 | uint32_t vaddr_limit; |
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267 | uint32_t size; |
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268 | uint32_t cxy; |
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269 | uint32_t i; |
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270 | |
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271 | header = (header_info_t*) info->hal_info; |
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272 | |
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273 | |
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274 | clusters = (cluster_info_t*) ((uint32_t)header + sizeof(header_info_t)); |
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275 | cluster_ptr = &clusters[info->local_cluster_id]; |
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276 | dev_tbl = (dev_info_t*)(cluster_ptr->offset + (uint32_t)header); |
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277 | cxy = cluster_ptr->cxy; |
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278 | |
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279 | /* Global variables init */ |
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280 | hal_onln_clusters_nr.value = header->onln_clstr_nr; |
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281 | hal_onln_cpus_nr.value = header->onln_cpu_nr; |
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282 | hal_cpus_per_cluster.value = header->cpu_nr; |
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283 | hal_boot_cxy_.value = info->boot_cluster_id; |
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284 | __current_cxy.value = cxy; |
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285 | fill_hal_cxy_to_almos_array(header); |
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286 | |
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287 | //used by remote_sb->hal_cxy_... |
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288 | for(i = 0; i < info->onln_clstr_nr; i++) |
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289 | { |
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290 | cluster_ptr = &clusters[i]; |
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291 | cxy = cluster_ptr->cxy; |
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292 | hal_entrys[cxy].hal_cxy = cluster_ptr->hal_cxy; |
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293 | } |
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294 | |
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295 | cpu_gid_tbl_init(info); |
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296 | kboot_tty_init(info); |
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297 | |
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298 | size = dev_tbl[0].size; |
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299 | |
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300 | if(size == 0) |
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301 | die("[ERROR]\t%s: Unexpected memory size for cluster %u\n", \ |
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302 | __FUNCTION__, cxy); |
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303 | |
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304 | this = CURRENT_THREAD; |
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305 | process = this->process; |
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306 | |
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307 | /* TODO: deal with offline clusters as well */ |
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308 | for(i = 0; i < info->onln_clstr_nr; i++) |
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309 | { |
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310 | cluster_ptr = &clusters[i]; |
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311 | cxy = cluster_ptr->cxy; |
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312 | |
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313 | if(cxy >= CLUSTER_NR) |
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314 | { |
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315 | die("\n[ERROR]\t%s: This kernel version support up to %d clusters, found %d\n", \ |
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316 | __FUNCTION__, CLUSTER_NR, cxy); |
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317 | } |
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318 | |
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319 | dev_tbl = (dev_info_t*)(cluster_ptr->offset + (uint32_t)header); |
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320 | if(dev_tbl[0].id == SOCLIB_RAM_ID) |
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321 | { |
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322 | vaddr_start = dev_tbl[0].base; |
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323 | size = dev_tbl[0].size; |
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324 | }else |
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325 | { |
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326 | vaddr_start = 0; |
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327 | size = 0; |
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328 | } |
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329 | |
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330 | if((cluster_ptr->cpu_nr != 0) && (size == 0)) |
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331 | die("\n[ERROR]\t%s: This Kernel Version Do Not Support CPU-Only Clusters, cxy %d\n", \ |
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332 | __FUNCTION__, cxy); |
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333 | |
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334 | vaddr_limit = vaddr_start + size; |
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335 | |
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336 | if(cxy == info->local_cluster_id) |
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337 | { |
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338 | process->vmm.limit_addr = vaddr_limit; |
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339 | } |
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340 | |
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341 | |
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342 | boot_dmsg("[INFO]\tHardware initialization of cluster %u\t\t\t\t[ %d ]\n", \ |
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343 | cxy, cpu_time_stamp()); |
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344 | |
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345 | cluster_entry_init(cxy, vaddr_start, size); |
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346 | } |
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347 | } |
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348 | |
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349 | /********************************************************************************************* |
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350 | * This function makes the architecture specific initialisation. |
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351 | * It makes the local cluster initialisation, dynamically detects the cluster devices, |
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352 | * and associates the appropriate drivers. |
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353 | ********************************************************************************************/ |
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354 | void hal_init( boot_info_t * info ) |
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355 | { |
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356 | cluster_t * cluster; |
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357 | header_info_t * header; |
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358 | cluster_info_t * clusters; |
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359 | cluster_info_t * cluster_ptr; |
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360 | dev_info_t * dev_tbl; |
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361 | cxy_t iopic_cxy; // should be the IO_cluster |
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362 | bool_t iopic_found; |
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363 | error_t error; |
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364 | uint32_t rcxy; |
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365 | cxy_t cxy; |
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366 | uint32_t i; |
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367 | |
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368 | /* Local variables init |
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369 | header = (header_info_t *)info->hal_info; |
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370 | |
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371 | if( strncmp( header->signature , hal_bib_signature , 16 ) ) |
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372 | { |
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373 | while(1); // TODO no TTY yet ??? [AG] |
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374 | } |
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375 | if( strncmp( header->arch , "TSAR" , 16)) |
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376 | { |
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377 | while(1); // TODO no TTY yet ??? [AG] |
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378 | } |
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379 | */ |
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380 | iopic_found = false; |
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381 | iopic_cxy = 0; |
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382 | clusters = (cluster_info_t*)((uint32_t)header + sizeof(header_info_t)); |
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383 | cluster_ptr = &clusters[info->local_cluster_id]; |
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384 | dev_tbl = (dev_info_t*)(cluster_ptr->offset + (uint32_t)header); |
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385 | cxy = cluster_ptr->cxy; |
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386 | |
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387 | hal_state_init(info); |
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388 | |
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389 | /* init cluster: also init current_{cxy, cluster} macros */ |
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390 | error = cluster_init(info, |
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391 | dev_tbl[0].base, |
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392 | dev_tbl[0].base + dev_tbl[0].size, |
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393 | clusters_tbl[cxy].vmem_start); |
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394 | |
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395 | if(err) |
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396 | die("ERROR: Failed To Initialize Cluster %d, Err %d\n", cxy, err); |
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397 | |
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398 | cluster = current_cluster; |
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399 | //TODO: move it to cluster.c |
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400 | //!!! THis value include the io_cluster ! |
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401 | cluster->clstr_nr = info->onln_clstr_nr; // TODO: headr->x_max * header->y_max; |
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402 | |
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403 | for(i = 0; i < info->onln_clstr_nr; i++) |
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404 | { |
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405 | cluster_ptr = &clusters[i]; |
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406 | |
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407 | dev_tbl = (dev_info_t*)(cluster_ptr->offset + (uint32_t)header); |
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408 | |
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409 | rcxy = cluster_ptr->cxy; |
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410 | |
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411 | boot_dmsg("\n[INFO]\tDevices initialization for cluster %d\t\t\t\t[ %d ]\n", \ |
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412 | rcxy, cpu_time_stamp()); |
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413 | |
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414 | if(hal_dev_init(cluster, &clusters_tbl[rcxy], dev_tbl, cluster_ptr)) |
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415 | { |
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416 | iopic = true; |
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417 | iopic_cxy = rcxy; |
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418 | } |
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419 | } |
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420 | |
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421 | if(iopic) //&& (cluster->io_clstr == cluster->id)) // Now it's dynamique |
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422 | hal_dev_iopic_register(cluster, &clusters_tbl[iopic_cxy]); |
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423 | |
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424 | } // end hal_init() |
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425 | |
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426 | |
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427 | /********************************************************************************************* |
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428 | * This function initialises all devices descriptors associated to peripherals |
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429 | * contained in the local cluster, as specified by the boot_info structure. |
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430 | ********************************************************************************************* |
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431 | * @ info : pointer on the local boot-info structure. |
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432 | * @ returns 0 if success / returns ENOMEM or EINVAL if error |
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433 | ********************************************************************************************/ |
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434 | error_t hal_devices_init( boot_info_t * info ) |
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435 | { |
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436 | drvdb_entry_t * entry; |
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437 | list_entry_t * devlist; |
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438 | |
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439 | boot_device_t * dev_tbl; // pointer on array of devices in boot_info |
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440 | uint32_t dev_nr; // actual number of devices in this cluster |
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441 | cluster_t * cluster; // pointer on local cluster manager |
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442 | cxy_t local_cxy; // local cluster identifier |
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443 | cxy-t target_cxy; // target cluster identifier |
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444 | device_t * device; // pointer on current device descriptor |
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445 | xptr_t base; // remote pointer on segment base |
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446 | uint32_t size; // segment size (bytes) |
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447 | dev_type_t type; // device type |
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448 | |
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449 | uint32_t i; |
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450 | bool_t pic_found; |
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451 | driver_t * driver; |
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452 | error_t error; |
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453 | |
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454 | // get local cluster pointer and identifier |
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455 | cluster = LOCAL_CLUSTER; |
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456 | cxy = cluster->cxy; |
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457 | |
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458 | // get number of peripherals |
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459 | dev_nr = info->devices_nr; |
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460 | dev_tbl = info->dev; |
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461 | |
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462 | // loop on all peripherals in cluster |
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463 | for( i = 0 ; i < dev_nr ; i++ ) |
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464 | { |
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465 | type = dev_tbl[i].type; |
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466 | |
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467 | // skip RAM and ROM |
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468 | if( (type == DEV_TYPE_RAM) || (type == DEV_TYPE_ROM) ) continue; |
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469 | |
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470 | // test PIC |
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471 | if( dev_tbl[i].type == DEV_TYPE_PIC ) pic_found = true; |
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472 | |
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473 | // replicated |
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474 | if( (type == DEV_TYPE_XCU ) || (type == DEV_TYPE_MMC) || (type == DEV_TYPE_MWR) ) |
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475 | { |
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476 | device = device_alloc( local); |
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477 | if( device == NULL ) |
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478 | { |
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479 | printk(PANIC,"%s failed to allocate device descriptor in cluster %x\n", |
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480 | __FUNCTION__ , cxy ); |
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481 | return ENOMEM; |
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482 | } |
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483 | } |
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484 | else |
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485 | { |
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486 | |
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487 | driver = drvdb_entry_get_driver(entry); |
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488 | |
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489 | // initialise device descriptor from boot_info |
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490 | spinlock_init( &device->lock ); |
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491 | |
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492 | device->type = dev_tbl[i].type; |
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493 | device->base = dev_tbl[i].base; |
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494 | device->size = dev_tbl[i].size; |
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495 | device->isr = dev_tbl[i].irq; |
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496 | |
---|
497 | error = driver->init( dev ); |
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498 | |
---|
499 | if( error ) |
---|
500 | { |
---|
501 | die("[ERROR]\tFailed To Initialize Device %s [Cluster %d, Dev %d, Err %d]\n", |
---|
502 | drvdb_entry_get_name(entry), rcxy, i, err); |
---|
503 | } |
---|
504 | |
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505 | devfs_register( dev ); |
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506 | list_add_last( devlist , &dev->list); |
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507 | |
---|
508 | boot_dmsg("[INFO]\tFound Device: %s\t\t\t\t\t\t[ %d ]\n[INFO]\t\tBase <0x%x> cxy %d Size <0x%x> Irq <%d>\t\t[ %d ]\n", \ |
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509 | drvdb_entry_get_name(entry), cpu_time_stamp(), (uint32_t)dev_base, \ |
---|
510 | rcxy, dev_tbl[i].size, dev_tbl[i].irq, cpu_time_stamp()); |
---|
511 | } // end loop on peripherals |
---|
512 | |
---|
513 | // register device descriptor in global list ??? |
---|
514 | hal_dev_register( cluster , centry ); // TODO ??? |
---|
515 | |
---|
516 | return iopic_clstr; |
---|
517 | |
---|
518 | } // end hal_devices_init() |
---|
519 | |
---|
520 | |
---|
521 | |
---|
522 | /********************************************************************************************* |
---|
523 | ********************************************************************************************/ |
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524 | void hal_xicu_set_wti(struct device_s *xicu, |
---|
525 | uint32_t cpu_inter, uint32_t wti_index, |
---|
526 | struct irq_action_s *action, |
---|
527 | struct device_s *dev) |
---|
528 | { |
---|
529 | uint64_t mailbox; |
---|
530 | uint32_t irq_out; |
---|
531 | error_t err; |
---|
532 | |
---|
533 | mailbox = xicu->base_paddr + (wti_index << 2); |
---|
534 | irq_out = cpu_inter*OUTPUT_IRQ_PER_PROC; |
---|
535 | |
---|
536 | |
---|
537 | xicu->op.icu.set_mask(xicu, |
---|
538 | (1 << wti_index), |
---|
539 | XICU_MSK_WTI_ENABLE, |
---|
540 | irq_out); |
---|
541 | |
---|
542 | boot_dmsg("[INFO]\t\t WTI %d <-> CPU %d (mailbox 0x%x%x)\t\t\t[ %d ]\n", \ |
---|
543 | wti_index, cpu_inter, MSB(mailbox), LSB(mailbox), \ |
---|
544 | cpu_time_stamp()); |
---|
545 | |
---|
546 | err = xicu->op.icu.bind_wti(xicu, action, wti_index); |
---|
547 | |
---|
548 | |
---|
549 | if(err != 0) |
---|
550 | die("[ERROR]\tFailed to bind %s via wti_mailbox 0x%x:%x , on xicu %s @%x [ err %d ]\n", \ |
---|
551 | dev ? dev->name : "IPI", MSB(mailbox),LSB(mailbox), xicu->name, xicu, err); |
---|
552 | |
---|
553 | if(dev) |
---|
554 | dev->mailbox = mailbox; |
---|
555 | //The binding is (to be) done dynamically in the peripheral |
---|
556 | //iopic->op.iopic.bind_wti_and_irq(iopic, mailbox, dev->irq); |
---|
557 | |
---|
558 | } |
---|
559 | |
---|
560 | //TODO: distibute iopic devices on multiple cluster ? |
---|
561 | //For now all the devices of the IOPIC_Cluster (cluster |
---|
562 | //without cpus) and there IRQs are handled by the IO_Cluster. |
---|
563 | void hal_dev_iopic_register(struct cluster_s *cluster, |
---|
564 | struct cluster_entry_s *entry) |
---|
565 | { |
---|
566 | struct list_entry *iter; |
---|
567 | struct device_s *iopic; |
---|
568 | struct device_s *xicu; |
---|
569 | struct device_s *dev; |
---|
570 | uint32_t device_index; |
---|
571 | uint32_t wti_index; |
---|
572 | uint32_t cpu_inter; |
---|
573 | uint32_t cpu_nr; |
---|
574 | //error_t err; |
---|
575 | |
---|
576 | cpu_inter = 0; |
---|
577 | device_index = 0; |
---|
578 | cpu_nr = cluster->cpu_nr; |
---|
579 | wti_index = cpu_nr;//Leave one WTI per proc for IPI |
---|
580 | |
---|
581 | xicu = hal_entrys[cluster->id].xicu; |
---|
582 | iopic = hal_dev_locate(&entry->devlist, SOCLIB_IOPIC_ID); |
---|
583 | |
---|
584 | if(xicu == NULL) |
---|
585 | die("[ERROR]\tNo XICU Is Found for IOPIC cluster %d\n", \ |
---|
586 | entry->cxy); |
---|
587 | |
---|
588 | boot_dmsg("\n[INFO]\tIOPIC cluster configuration: cxy %d <0x%x,0x%x>\t[ %d ]\n", \ |
---|
589 | entry->cxy, iopic->base, (iopic->base+iopic->size), cpu_time_stamp()); |
---|
590 | |
---|
591 | list_foreach(&entry->devlist, iter) |
---|
592 | { |
---|
593 | dev = list_element(iter, struct device_s, list); |
---|
594 | |
---|
595 | if(wti_index > (IOPIC_WTI_PER_CLSTR - cpu_nr)) |
---|
596 | die("[ERROR]\tNo enough WTI in cluster %d\n", cluster->id); |
---|
597 | |
---|
598 | |
---|
599 | if((dev != iopic) && (dev->irq != -1)) |
---|
600 | { |
---|
601 | boot_dmsg("[INFO]\tLinking device %s to XICU on cluster %d through IOPIC cluster\t[ %d ]\n", \ |
---|
602 | dev->name, xicu->cxy, cpu_time_stamp()); |
---|
603 | |
---|
604 | hal_xicu_set_wti(xicu, device_index%cpu_nr, wti_index, &dev->action, dev); |
---|
605 | |
---|
606 | dev->iopic = iopic; |
---|
607 | |
---|
608 | wti_index++; |
---|
609 | device_index++; |
---|
610 | } |
---|
611 | |
---|
612 | devfs_register(dev); |
---|
613 | } |
---|
614 | } // end hal_xcu_set_wti() |
---|
615 | |
---|
616 | |
---|