1 | /* |
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2 | * mmu-info.c - TSAR MMU exceptions related informations |
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3 | * |
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4 | * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless |
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5 | * Copyright (c) 2011,2012 UPMC Sorbonne Universites |
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6 | * |
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7 | * This file is part of ALMOS-kernel. |
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8 | * |
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9 | * ALMOS-kernel is free software; you can redistribute it and/or modify it |
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10 | * under the terms of the GNU General Public License as published by |
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11 | * the Free Software Foundation; version 2.0 of the License. |
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12 | * |
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13 | * ALMOS-kernel is distributed in the hope that it will be useful, but |
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14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 | * General Public License for more details. |
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17 | * |
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18 | * You should have received a copy of the GNU General Public License |
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19 | * along with ALMOS-kernel; if not, write to the Free Software Foundation, |
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20 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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21 | */ |
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22 | |
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23 | #define _USE_MMU_INFO_H_ |
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24 | #include <mmu-info.h> |
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25 | #include <bits.h> |
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26 | |
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27 | #define MMU_UNKNOWN_ERR 0x0000 |
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28 | |
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29 | static mmu_except_info_t mmu_except_db[] = |
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30 | {{0x0001, "MMU_WRITE_PT1_UNMAPPED", "Write access : Page fault on Table 1 (invalid PTE)", "Non Fatal Error"}, |
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31 | {0x0002, "MMU_WRITE_PT2_UNMAPPED", "Write access : Page fault on Table 2 (invalid PTE)", "Non Fatal Error"}, |
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32 | {0x0004, "MMU_WRITE_PRIVILEGE_VIOLATION", "Write access : Protected access in user mode", "User Error"}, |
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33 | {0x0008, "MMU_WRITE_ACCES_VIOLATION","Write access : Write to a non writable page", "User error"}, |
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34 | {0x0020, "MMU_WRITE_UNDEFINED_XTN","Write access : Undefined external access address","User error"}, |
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35 | {0x0040, "MMU_WRITE_PT1_ILLEGAL_ACCESS","Write access : Bus Error in Table1 access","Kernel error"}, |
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36 | {0x0080, "MMU_WRITE_PT2_ILLEGAL_ACCESS","Write access : Bus Error in Table2 access","Kernel error"}, |
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37 | {0x0100, "MMU_WRITE_DATA_ILLEGAL_ACCESS","Write access : Bus Error during the cache access","Kernel error"}, |
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38 | {0x1001, "MMU_READ_PT1_UNMAPPED","Read access : Page fault on Table1 (invalid PTE)","non fatal error"}, |
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39 | {0x1002, "MMU_READ_PT2_UNMAPPED","Read access : Page fault on Table 2 (invalid PTE)","non fatal error"}, |
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40 | {0x1004, "MMU_READ_PRIVILEGE_VIOLATION","Read access : Protected access in user mode","User error"}, |
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41 | {0x1010, "MMU_READ_EXEC_VIOLATION","Read access : Exec access to a non exec page","User error"}, |
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42 | {0x1020, "MMU_READ_UNDEFINED_XTN","Read access : Undefined external access address","User error"}, |
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43 | {0x1040, "MMU_READ_PT1_ILLEGAL_ACCESS","Read access : Bus Error in Table1 access","Kernel error"}, |
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44 | {0x1080, "MMU_READ_PT2_ILLEGAL_ACCESS","Read access : Bus Error in Table2 access","Kernel error"}, |
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45 | {0x1100, "MMU_READ_DATA_ILLEGAL_ACCESS","Read access : Bus Error during the cache access","Kernel error"}, |
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46 | {MMU_UNKNOWN_ERR, "UNKNOWN", "Exception Detected but no MMU Error code has been found", "Disfunction of MMU's Error Report"}}; |
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47 | |
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48 | |
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49 | |
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50 | inline mmu_except_info_t* mmu_except_get_entry(uint_t mmu_err_val) |
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51 | { |
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52 | uint_t entry = 0; |
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53 | |
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54 | while(mmu_except_db[entry].err != MMU_UNKNOWN_ERR) |
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55 | { |
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56 | if(mmu_except_db[entry].err == mmu_err_val) |
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57 | break; |
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58 | |
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59 | entry ++; |
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60 | } |
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61 | |
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62 | return &mmu_except_db[entry]; |
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63 | } |
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