| 1 | /* |
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| 2 | * pci.c - PCI bus related registers and access functions |
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| 3 | * |
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| 4 | * Copyright (c) 2008,2009,2010,2011,2012 Ghassan Almaless |
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| 5 | * Copyright (c) 2011,2012 UPMC Sorbonne Universites |
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| 6 | * |
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| 7 | * This file is part of ALMOS-kernel. |
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| 8 | * |
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| 9 | * ALMOS-kernel is free software; you can redistribute it and/or modify it |
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| 10 | * under the terms of the GNU General Public License as published by |
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| 11 | * the Free Software Foundation; version 2.0 of the License. |
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| 12 | * |
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| 13 | * ALMOS-kernel is distributed in the hope that it will be useful, but |
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| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 16 | * General Public License for more details. |
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| 17 | * |
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| 18 | * You should have received a copy of the GNU General Public License |
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| 19 | * along with ALMOS-kernel; if not, write to the Free Software Foundation, |
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| 20 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef _PCI_BUS_H_ |
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| 24 | #define _PCI_BUS_H_ |
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| 25 | |
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| 26 | #include <types.h> |
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| 27 | #include <cpu-io.h> |
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| 28 | |
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| 29 | #define PCI_TGT_MAX_CONFIG_SPACE 256 |
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| 30 | #define PCI_TGT_MAX_CONFIG_REG 64 |
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| 31 | #define PCI_BUS_MAX_NR 255 |
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| 32 | #define PCI_BUS_DEV_MAX_NR 32 |
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| 33 | #define PCI_DEV_FUNC_MAX_NR 8 |
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| 34 | |
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| 35 | #define PCI_CONFIG_ADDR 0xCF8 |
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| 36 | #define PCI_CONFIG_DATA 0xCFC |
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| 37 | |
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| 38 | #define PCI_STD_DEV_TYPE 0x00 |
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| 39 | #define PCI_BRIDGE_TYPE 0x01 |
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| 40 | #define PCI_CARDBUS_BRIDGE_TYPE 0x02 |
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| 41 | |
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| 42 | #define PCI_VENDOR_ID 0x00 |
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| 43 | #define PCI_DEVCIE_ID 0x02 |
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| 44 | #define PCI_CMD_REG 0x04 |
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| 45 | #define PCI_STATUS_REG 0x06 |
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| 46 | #define PCI_REVISION_ID 0x08 |
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| 47 | |
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| 48 | #define PCI_CLASS_ID 0x0A |
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| 49 | #define PCI_HEADER_TYPE 0x0E |
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| 50 | |
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| 51 | #define PCI_BAR0 0x10 |
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| 52 | #define PCI_BAR1 0x14 |
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| 53 | #define PCI_BAR2 0x18 |
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| 54 | #define PCI_BAR3 0x1C |
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| 55 | #define PCI_BAR4 0x20 |
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| 56 | #define PCI_BAR5 0x24 |
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| 57 | |
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| 58 | #define PCI_INT_INFO 0x3C |
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| 59 | |
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| 60 | #define pci_mkconfig1_addr(_bus,_dev,_func,_offset) \ |
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| 61 | ((uint32_t)(0x80000000 | ((_bus) << 16) | \ |
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| 62 | ((_dev) << 11) | ((_func) << 8) | \ |
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| 63 | ((_offset) & 0xfc))) |
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| 64 | |
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| 65 | |
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| 66 | static inline uint16_t pci_config_read(uint_t bus, uint_t slot, uint_t func, uint_t offset) |
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| 67 | { |
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| 68 | uint32_t addr; |
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| 69 | uint32_t val; |
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| 70 | |
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| 71 | addr = pci_mkconfig1_addr(bus,slot,func,offset); |
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| 72 | |
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| 73 | cpu_io_out32(PCI_CONFIG_ADDR, addr); |
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| 74 | val = cpu_io_in32(PCI_CONFIG_DATA); |
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| 75 | |
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| 76 | return val >> ((offset & 3) * 8); |
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| 77 | } |
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| 78 | |
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| 79 | #endif /* _PCI_BUS_H_ */ |
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