1 | /* |
---|
2 | * soclib_hba.h - soclib AHCI block device driver definition. |
---|
3 | * |
---|
4 | * Author Alain Greiner (2016) |
---|
5 | * |
---|
6 | * Copyright (c) UPMC Sorbonne Universites |
---|
7 | * |
---|
8 | * This file is part of ALMOS-MKH. |
---|
9 | * |
---|
10 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
---|
11 | * under the terms of the GNU General Public License as published by |
---|
12 | * the Free Software Foundation; version 2.0 of the License. |
---|
13 | * |
---|
14 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
---|
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
17 | * General Public License for more details. |
---|
18 | * |
---|
19 | * You should have received a copy of the GNU General Public License |
---|
20 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
---|
21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
---|
22 | */ |
---|
23 | |
---|
24 | #ifndef _SOCLIB_HBA_H_ |
---|
25 | #define _SOCLIB_HBA_H_ |
---|
26 | |
---|
27 | #include <chdev.h> |
---|
28 | #include <hal_types.h> |
---|
29 | |
---|
30 | /***************************************************************************************** |
---|
31 | * This driver supports the SocLib VciMultiAhci component, that is a multi-channels, |
---|
32 | * block oriented, external storage controler, respecting the AHCI standard. |
---|
33 | * |
---|
34 | * 1. Each HBA channel define an independant physical disk, but this driver |
---|
35 | * supports only channel 0, because ALMOS-MKH uses only one physical disk. |
---|
36 | * |
---|
37 | * 2. The SOCLIB HBA component support split memory buffers (several physical |
---|
38 | * buffers for one single command), but this driver supports only one |
---|
39 | * single buffer I/O operation. |
---|
40 | * |
---|
41 | * 3. The "command list" can register up to 32 independant commands, posted |
---|
42 | * by different user threads. The command list is filled by the server |
---|
43 | * thread associated to the device, using one free slot per command, until the |
---|
44 | * device waiting queue of client threads is empty. |
---|
45 | * |
---|
46 | * 4. As there is only one interrupt, and the registered I/O operation can complete |
---|
47 | * in any order, this interrupt is not linked to a specific I/O operation. |
---|
48 | * The associated HBA_ISR unblock all client threads that have a completed command, |
---|
49 | * using the "hba_active_slots" and "hba_owner_thread[32]" global variables. |
---|
50 | ****************************************************************************************/ |
---|
51 | |
---|
52 | /***************************************************************************************** |
---|
53 | * HBA component registers offsets |
---|
54 | ****************************************************************************************/ |
---|
55 | |
---|
56 | enum SoclibMultiAhciRegisters |
---|
57 | { |
---|
58 | HBA_PXCLB_REG = 0, // command list base address 32 LSB bits |
---|
59 | HBA_PXCLBU_REG = 1, // command list base address 32 MSB bits |
---|
60 | HBA_PXIS_REG = 4, // interrupt status |
---|
61 | HBA_PXIE_REG = 5, // interrupt enable |
---|
62 | HBA_PXCMD_REG = 6, // run |
---|
63 | HBA_BLOCK_SIZE_REG = 7, // number of bytes per block |
---|
64 | HBA_BLOCK_COUNT_REG = 8, // number of blocks |
---|
65 | HBA_PXCI_REG = 14, // command bit-vector |
---|
66 | |
---|
67 | }; |
---|
68 | |
---|
69 | /***************************************************************************************** |
---|
70 | * This structure defines the command header (16 bytes) |
---|
71 | ****************************************************************************************/ |
---|
72 | |
---|
73 | typedef struct hba_cmd_header_s |
---|
74 | { |
---|
75 | unsigned int res0; // reserved |
---|
76 | unsigned char lba0; // LBA 7:0 |
---|
77 | unsigned char lba1; // LBA 15:8 |
---|
78 | unsigned char lba2; // LBA 23:16 |
---|
79 | unsigned char res1; // reserved |
---|
80 | unsigned char lba3; // LBA 31:24 |
---|
81 | unsigned char lba4; // LBA 39:32 |
---|
82 | unsigned char lba5; // LBA 47:40 |
---|
83 | unsigned char res2; // reserved |
---|
84 | unsigned int res3; // reserved |
---|
85 | |
---|
86 | } |
---|
87 | hba_cmd_header_t; |
---|
88 | |
---|
89 | /***************************************************************************************** |
---|
90 | * This structure defines the command buffer (16 bytes) |
---|
91 | ****************************************************************************************/ |
---|
92 | |
---|
93 | typedef struct hba_cmd_buffer_s |
---|
94 | { |
---|
95 | unsigned int dba; // Buffer base address 32 LSB bits |
---|
96 | unsigned int dbau; // Buffer base address 32 MSB bits |
---|
97 | unsigned int res0; // reserved |
---|
98 | unsigned int dbc; // Buffer byte count |
---|
99 | } |
---|
100 | hba_cmd_buffer_t; |
---|
101 | |
---|
102 | /***************************************************************************************** |
---|
103 | * This structure defines a command table (32 bytes, because we support only one buffer) |
---|
104 | ****************************************************************************************/ |
---|
105 | |
---|
106 | typedef struct hba_cmd_table_s |
---|
107 | { |
---|
108 | hba_cmd_header_t header; // contains LBA |
---|
109 | hba_cmd_buffer_t buffer; // only one physical buffer |
---|
110 | } |
---|
111 | hba_cmd_table_t; |
---|
112 | |
---|
113 | /***************************************************************************************** |
---|
114 | * This structure defines a command descriptor (16 bytes) |
---|
115 | ****************************************************************************************/ |
---|
116 | |
---|
117 | typedef struct hba_cmd_desc_s |
---|
118 | { |
---|
119 | unsigned char flag[2]; // W in bit 6 of flag[0] |
---|
120 | unsigned char prdtl[2]; // Number of buffers |
---|
121 | unsigned int prdbc; // Number of bytes actually transfered |
---|
122 | unsigned int ctba; // Command Table base address 32 LSB bits |
---|
123 | unsigned int ctbau; // Command Table base address 32 MSB bits |
---|
124 | } |
---|
125 | hba_cmd_desc_t; |
---|
126 | |
---|
127 | /******************************************************************************************** |
---|
128 | * This function access the SOCLIB_HBA hardware registers to get the block size and the |
---|
129 | * number of blocks, and initialises the "extension" field of the IOC device descriptor. |
---|
130 | ******************************************************************************************** |
---|
131 | * @ chdev : local pointer on the generic IOC chdev descriptor. |
---|
132 | *******************************************************************************************/ |
---|
133 | extern void soclib_hba_init( chdev_t * chdev ); |
---|
134 | |
---|
135 | /******************************************************************************************** |
---|
136 | * This function is called by the server thread associated to the IOC device. |
---|
137 | * It decodes the IOC device command embedded in the calling thread descriptor, |
---|
138 | * (format defined in the dev_ioc.h file) and starts execution of this generic command, |
---|
139 | * accessing the relevant SOCLIB_HBA hardware registers. |
---|
140 | * It registers the command in the SOCLIB_HBA device and returns without blocking |
---|
141 | * because this AHCI component supports up to 32 concurrent I/O operations. |
---|
142 | * It simply deschedules without blocking if the number of registered I/O operations |
---|
143 | * becomes larger than 32, which should be a rare event. |
---|
144 | ******************************************************************************************** |
---|
145 | * @ xp_thread : extended pointer on the client thread. |
---|
146 | *******************************************************************************************/ |
---|
147 | extern void soclib_hba_command( xptr_t thread_xp ); |
---|
148 | |
---|
149 | /******************************************************************************************** |
---|
150 | * This Interrupt Service Routine is executed when the IRQ signaling the completion of |
---|
151 | * one or several I/O operations registered in the SOCLIB_AHCI device is received. |
---|
152 | * It acknowledges the IRQ by accessing the proper SOCLIB_HBA register, and unblock |
---|
153 | * all client thread that have an I/O operation completed. |
---|
154 | ******************************************************************************************** |
---|
155 | * @ chdev : local pointer on the generic IOC device descriptor. |
---|
156 | *******************************************************************************************/ |
---|
157 | extern void soclib_hba_isr( chdev_t * chdev ); |
---|
158 | |
---|
159 | |
---|
160 | #endif /* _SOCLIB_HBA_H_ */ |
---|