1 | /* |
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2 | * soclib_xcu.c - soclib XCU driver API implementation. |
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3 | * |
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4 | * Authors Alain Greiner (2016) |
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5 | * |
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6 | * Copyright (c) UPMC Sorbonne Universites |
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7 | * |
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8 | * This file is part of ALMOS-MKH. |
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9 | * |
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10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License as published by |
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12 | * the Free Software Foundation; version 2.0 of the License. |
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13 | * |
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14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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17 | * General Public License for more details. |
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18 | * |
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19 | * You should have received a copy of the GNU General Public License |
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20 | * along with ALMOS-kernel; if not, write to the Free Software Foundation, |
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21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 | */ |
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23 | |
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24 | #include <soclib_xcu.h> |
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25 | #include <hal_types.h> |
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26 | #include <core.h> |
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27 | #include <chdev.h> |
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28 | |
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29 | |
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30 | |
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31 | //////////////////////////////////// |
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32 | void soclib_xcu_init( chdev_t * icu, |
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33 | lid_t lid ) |
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34 | { |
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35 | // get local ICU segment base address |
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36 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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37 | |
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38 | // disable all IRQs |
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39 | base[XCU_MSK_HWI_DISABLE << 5 | lid] = 0xFFFFFFFF; |
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40 | base[XCU_MSK_WTI_DISABLE << 5 | lid] = 0xFFFFFFFF; |
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41 | base[XCU_MSK_PTI_DISABLE << 5 | lid] = 0xFFFFFFFF; |
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42 | } |
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43 | |
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44 | //////////////////////////////////////////// |
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45 | void soclib_xcu_disable_irq( chdev_t * icu, |
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46 | uint32_t mask, |
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47 | uint32_t type, |
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48 | lid_t lid ) |
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49 | { |
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50 | // get XCU segment base address |
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51 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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52 | |
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53 | // write into register |
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54 | if ( type == WTI_TYPE ) base[XCU_MSK_WTI_DISABLE << 5 | lid] = mask; |
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55 | else if( type == HWI_TYPE ) base[XCU_MSK_HWI_DISABLE << 5 | lid] = mask; |
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56 | else base[XCU_MSK_PTI_DISABLE << 5 | lid] = mask; |
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57 | } |
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58 | |
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59 | /////////////////////////////////////////// |
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60 | void soclib_xcu_enable_irq( chdev_t * icu, |
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61 | uint32_t mask, |
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62 | uint32_t type, |
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63 | lid_t lid ) |
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64 | { |
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65 | // get XCU segment base address |
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66 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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67 | |
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68 | // write into register |
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69 | if ( type == WTI_TYPE ) base[XCU_MSK_WTI_ENABLE << 5 | lid] = mask; |
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70 | else if( type == HWI_TYPE ) base[XCU_MSK_HWI_ENABLE << 5 | lid] = mask; |
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71 | else base[XCU_MSK_PTI_ENABLE << 5 | lid] = mask; |
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72 | } |
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73 | |
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74 | /////////////////////////////////////////// |
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75 | void soclib_xcu_get_masks( chdev_t * icu, |
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76 | lid_t lid, |
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77 | uint32_t * hwi_mask, |
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78 | uint32_t * wti_mask, |
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79 | uint32_t * pti_mask ) |
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80 | { |
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81 | // get XCU segment base address |
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82 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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83 | |
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84 | // get values from registers |
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85 | *hwi_mask = base[XCU_MSK_HWI << 5 | lid]; |
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86 | *wti_mask = base[XCU_MSK_WTI << 5 | lid]; |
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87 | *pti_mask = base[XCU_MSK_PTI << 5 | lid]; |
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88 | } |
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89 | |
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90 | ////////////////////////////////////////// |
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91 | void soclib_xcu_set_period( chdev_t * icu, |
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92 | uint32_t index, |
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93 | uint32_t period ) |
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94 | { |
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95 | // get local ICU segment base address |
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96 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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97 | |
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98 | // write into register |
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99 | base[XCU_PTI_PER << 5 | index] = period; |
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100 | } |
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101 | |
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102 | ///////////////////////////////////////////// |
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103 | uint32_t soclib_xcu_ack_timer( chdev_t * icu, |
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104 | uint32_t index ) |
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105 | { |
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106 | // get local ICU segment base address |
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107 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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108 | |
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109 | // read from register |
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110 | return base[XCU_PTI_ACK << 5 | index]; |
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111 | } |
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112 | |
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113 | /////////////////////////////////////////// |
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114 | void soclib_xcu_get_status( chdev_t * icu, |
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115 | lid_t lid, |
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116 | uint32_t * hwi_status, |
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117 | uint32_t * wti_status, |
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118 | uint32_t * pti_status ) |
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119 | { |
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120 | // get local ICU segment base address |
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121 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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122 | |
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123 | // read PRIO register |
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124 | uint32_t prio = base[XCU_PRIO << 5 | lid]; |
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125 | |
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126 | *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0; |
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127 | *hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0; |
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128 | *pti_status = (prio & 0x1) ? (((prio >> 8) & 0x1F) + 1) : 0; |
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129 | } |
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130 | |
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131 | ///////////////////////////////////////// |
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132 | void soclib_xcu_send_ipi( xptr_t icu_xp, |
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133 | lid_t lid ) |
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134 | { |
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135 | // get target ICU device cluster and local pointer |
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136 | cxy_t cxy_icu = GET_CXY( icu_xp ); |
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137 | chdev_t * ptr_icu = (chdev_t *)GET_PTR( icu_xp ); |
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138 | |
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139 | // get extended pointer on target ICU segment base |
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140 | xptr_t xp_base = (xptr_t)hal_remote_lwd( XPTR( cxy_icu , &ptr_icu->base ) ); |
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141 | |
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142 | // get remote ICU segment local pointer |
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143 | uint32_t * base = (uint32_t *)GET_PTR( xp_base ); |
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144 | |
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145 | // send IPI to remote core |
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146 | hal_remote_sw( XPTR( cxy_icu , &base[XCU_WTI_REG << 5 | lid] ) , 0 ); |
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147 | } |
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148 | |
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149 | ////////////////////////////////////////////// |
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150 | uint32_t * soclib_xcu_wti_ptr( chdev_t * icu, |
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151 | uint32_t index ) |
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152 | { |
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153 | uint32_t * base = (uint32_t *)GET_PTR( icu->base ); |
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154 | |
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155 | return &base[XCU_WTI_REG << 5 | index]; |
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156 | } |
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