| [444] | 1 | /* This file defines the interface between the d10v simulator and gdb. |
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| 2 | |
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| 3 | Copyright 1999-2013 Free Software Foundation, Inc. |
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| 4 | |
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| 5 | This file is part of GDB. |
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| 6 | |
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| 7 | This program is free software; you can redistribute it and/or modify |
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| 8 | it under the terms of the GNU General Public License as published by |
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| 9 | the Free Software Foundation; either version 3 of the License, or |
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| 10 | (at your option) any later version. |
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| 11 | |
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| 12 | This program is distributed in the hope that it will be useful, |
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| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 15 | GNU General Public License for more details. |
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| 16 | |
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| 17 | You should have received a copy of the GNU General Public License |
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| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
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| 19 | |
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| 20 | #if !defined (SIM_D10V_H) |
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| 21 | #define SIM_D10V_H |
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| 22 | |
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| 23 | #ifdef __cplusplus |
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| 24 | extern "C" { // } |
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| 25 | #endif |
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| 26 | |
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| 27 | /* GDB interprets addresses as: |
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| 28 | |
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| 29 | 0x00xxxxxx: Physical unified memory segment (Unified memory) |
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| 30 | 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) |
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| 31 | 0x02xxxxxx: Physical data memory segment (On-chip data memory) |
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| 32 | 0x10xxxxxx: Logical data address segment (DMAP translated memory) |
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| 33 | 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) |
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| 34 | |
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| 35 | The remote d10v board interprets addresses as: |
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| 36 | |
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| 37 | 0x00xxxxxx: Physical unified memory segment (Unified memory) |
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| 38 | 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) |
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| 39 | 0x02xxxxxx: Physical data memory segment (On-chip data memory) |
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| 40 | |
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| 41 | The following translate a virtual DMAP/IMAP offset into a physical |
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| 42 | memory segment assigning the translated address to PHYS. Since a |
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| 43 | memory access may cross a page boundrary the number of bytes for |
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| 44 | which the translation is applicable (or 0 for an invalid virtual |
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| 45 | offset) is returned. */ |
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| 46 | |
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| 47 | enum |
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| 48 | { |
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| 49 | SIM_D10V_MEMORY_UNIFIED = 0x00000000, |
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| 50 | SIM_D10V_MEMORY_INSN = 0x01000000, |
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| 51 | SIM_D10V_MEMORY_DATA = 0x02000000, |
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| 52 | SIM_D10V_MEMORY_DMAP = 0x10000000, |
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| 53 | SIM_D10V_MEMORY_IMAP = 0x11000000 |
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| 54 | }; |
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| 55 | |
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| 56 | extern unsigned long sim_d10v_translate_dmap_addr |
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| 57 | (unsigned long offset, |
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| 58 | int nr_bytes, |
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| 59 | unsigned long *phys, |
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| 60 | void *regcache, |
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| 61 | unsigned long (*dmap_register) (void *regcache, int reg_nr)); |
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| 62 | |
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| 63 | extern unsigned long sim_d10v_translate_imap_addr |
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| 64 | (unsigned long offset, |
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| 65 | int nr_bytes, |
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| 66 | unsigned long *phys, |
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| 67 | void *regcache, |
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| 68 | unsigned long (*imap_register) (void *regcache, int reg_nr)); |
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| 69 | |
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| 70 | extern unsigned long sim_d10v_translate_addr |
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| 71 | (unsigned long vaddr, |
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| 72 | int nr_bytes, |
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| 73 | unsigned long *phys, |
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| 74 | void *regcache, |
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| 75 | unsigned long (*dmap_register) (void *regcache, int reg_nr), |
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| 76 | unsigned long (*imap_register) (void *regcache, int reg_nr)); |
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| 77 | |
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| 78 | |
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| 79 | /* The simulator makes use of the following register information. */ |
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| 80 | |
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| 81 | enum sim_d10v_regs |
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| 82 | { |
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| 83 | SIM_D10V_R0_REGNUM, |
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| 84 | SIM_D10V_R1_REGNUM, |
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| 85 | SIM_D10V_R2_REGNUM, |
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| 86 | SIM_D10V_R3_REGNUM, |
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| 87 | SIM_D10V_R4_REGNUM, |
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| 88 | SIM_D10V_R5_REGNUM, |
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| 89 | SIM_D10V_R6_REGNUM, |
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| 90 | SIM_D10V_R7_REGNUM, |
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| 91 | SIM_D10V_R8_REGNUM, |
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| 92 | SIM_D10V_R9_REGNUM, |
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| 93 | SIM_D10V_R10_REGNUM, |
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| 94 | SIM_D10V_R11_REGNUM, |
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| 95 | SIM_D10V_R12_REGNUM, |
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| 96 | SIM_D10V_R13_REGNUM, |
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| 97 | SIM_D10V_R14_REGNUM, |
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| 98 | SIM_D10V_R15_REGNUM, |
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| 99 | SIM_D10V_CR0_REGNUM, |
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| 100 | SIM_D10V_CR1_REGNUM, |
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| 101 | SIM_D10V_CR2_REGNUM, |
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| 102 | SIM_D10V_CR3_REGNUM, |
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| 103 | SIM_D10V_CR4_REGNUM, |
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| 104 | SIM_D10V_CR5_REGNUM, |
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| 105 | SIM_D10V_CR6_REGNUM, |
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| 106 | SIM_D10V_CR7_REGNUM, |
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| 107 | SIM_D10V_CR8_REGNUM, |
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| 108 | SIM_D10V_CR9_REGNUM, |
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| 109 | SIM_D10V_CR10_REGNUM, |
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| 110 | SIM_D10V_CR11_REGNUM, |
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| 111 | SIM_D10V_CR12_REGNUM, |
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| 112 | SIM_D10V_CR13_REGNUM, |
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| 113 | SIM_D10V_CR14_REGNUM, |
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| 114 | SIM_D10V_CR15_REGNUM, |
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| 115 | SIM_D10V_A0_REGNUM, |
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| 116 | SIM_D10V_A1_REGNUM, |
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| 117 | SIM_D10V_SPI_REGNUM, |
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| 118 | SIM_D10V_SPU_REGNUM, |
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| 119 | SIM_D10V_IMAP0_REGNUM, |
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| 120 | SIM_D10V_IMAP1_REGNUM, |
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| 121 | SIM_D10V_DMAP0_REGNUM, |
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| 122 | SIM_D10V_DMAP1_REGNUM, |
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| 123 | SIM_D10V_DMAP2_REGNUM, |
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| 124 | SIM_D10V_DMAP3_REGNUM, |
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| 125 | SIM_D10V_TS2_DMAP_REGNUM |
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| 126 | }; |
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| 127 | |
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| 128 | enum |
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| 129 | { |
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| 130 | SIM_D10V_NR_R_REGS = 16, |
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| 131 | SIM_D10V_NR_A_REGS = 2, |
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| 132 | SIM_D10V_NR_IMAP_REGS = 2, |
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| 133 | SIM_D10V_NR_DMAP_REGS = 4, |
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| 134 | SIM_D10V_NR_CR_REGS = 16 |
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| 135 | }; |
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| 136 | |
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| 137 | #ifdef __cplusplus |
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| 138 | } |
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| 139 | #endif |
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| 140 | |
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| 141 | #endif |
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