source: trunk/libs/newlib/src/include/opcode/aarch64.h @ 551

Last change on this file since 551 was 444, checked in by satin@…, 7 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc
File size: 27.9 KB
Line 
1/* AArch64 assembler/disassembler support.
2
3   Copyright 2009, 2010, 2011, 2012, 2013  Free Software Foundation, Inc.
4   Contributed by ARM Ltd.
5
6   This file is part of GNU Binutils.
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 3 of the license, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program; see the file COPYING3. If not,
20   see <http://www.gnu.org/licenses/>.  */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
30/* The offset for pc-relative addressing is currently defined to be 0.  */
31#define AARCH64_PCREL_OFFSET            0
32
33typedef uint32_t aarch64_insn;
34
35/* The following bitmasks control CPU features.  */
36#define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
37#define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
38#define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
39#define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
40#define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
41
42/* Architectures are the sum of the base and extensions.  */
43#define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
44                                                 AARCH64_FEATURE_FP  \
45                                                 | AARCH64_FEATURE_SIMD)
46#define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
47#define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
48
49/* CPU-specific features.  */
50typedef unsigned long aarch64_feature_set;
51
52#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
53  (((CPU) & (FEAT)) != 0)
54
55#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
56  do                                            \
57    {                                           \
58      (TARG) = (F1) | (F2);                     \
59    }                                           \
60  while (0)
61
62#define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
63  do                                            \
64    {                                           \
65      (TARG) = (F1) &~ (F2);                    \
66    }                                           \
67  while (0)
68
69#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
70
71#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
72  (((OPC) & (FEAT)) != 0)
73
74enum aarch64_operand_class
75{
76  AARCH64_OPND_CLASS_NIL,
77  AARCH64_OPND_CLASS_INT_REG,
78  AARCH64_OPND_CLASS_MODIFIED_REG,
79  AARCH64_OPND_CLASS_FP_REG,
80  AARCH64_OPND_CLASS_SIMD_REG,
81  AARCH64_OPND_CLASS_SIMD_ELEMENT,
82  AARCH64_OPND_CLASS_SISD_REG,
83  AARCH64_OPND_CLASS_SIMD_REGLIST,
84  AARCH64_OPND_CLASS_CP_REG,
85  AARCH64_OPND_CLASS_ADDRESS,
86  AARCH64_OPND_CLASS_IMMEDIATE,
87  AARCH64_OPND_CLASS_SYSTEM,
88};
89
90/* Operand code that helps both parsing and coding.
91   Keep AARCH64_OPERANDS synced.  */
92
93enum aarch64_opnd
94{
95  AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
96
97  AARCH64_OPND_Rd,      /* Integer register as destination.  */
98  AARCH64_OPND_Rn,      /* Integer register as source.  */
99  AARCH64_OPND_Rm,      /* Integer register as source.  */
100  AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
101  AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
102  AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
103  AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
104  AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
105
106  AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
107  AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
108  AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
109  AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
110
111  AARCH64_OPND_Fd,      /* Floating-point Fd.  */
112  AARCH64_OPND_Fn,      /* Floating-point Fn.  */
113  AARCH64_OPND_Fm,      /* Floating-point Fm.  */
114  AARCH64_OPND_Fa,      /* Floating-point Fa.  */
115  AARCH64_OPND_Ft,      /* Floating-point Ft.  */
116  AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
117
118  AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
119  AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
120  AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
121
122  AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
123  AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
124  AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
125  AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
126  AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
127  AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
128  AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
129  AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
130  AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
131  AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
132  AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
133                           structure to all lanes.  */
134  AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
135
136  AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
137  AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
138
139  AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
140  AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
141  AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
142  AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
143  AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
144  AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
145  AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
146                           (no encoding).  */
147  AARCH64_OPND_IMM0,    /* Immediate for #0.  */
148  AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
149  AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
150  AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
151  AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
152  AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
153  AARCH64_OPND_IMM,     /* Immediate.  */
154  AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
155  AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
156  AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
157  AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
158  AARCH64_OPND_BIT_NUM, /* Immediate.  */
159  AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
160  AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
161  AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
162                           each condition flag.  */
163
164  AARCH64_OPND_LIMM,    /* Logical Immediate.  */
165  AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
166  AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
167  AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
168  AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
169
170  AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
171
172  AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
173  AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
174  AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
175  AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
176  AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
177
178  AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
179  AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
180  AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
181  AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
182  AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
183                                   negative or unaligned and there is
184                                   no writeback allowed.  This operand code
185                                   is only used to support the programmer-
186                                   friendly feature of using LDR/STR as the
187                                   the mnemonic name for LDUR/STUR instructions
188                                   wherever there is no ambiguity.  */
189  AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
190  AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
191  AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
192
193  AARCH64_OPND_SYSREG,          /* System register operand.  */
194  AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
195  AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
196  AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
197  AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
198  AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
199  AARCH64_OPND_BARRIER,         /* Barrier operand.  */
200  AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
201  AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
202};
203
204/* Qualifier constrains an operand.  It either specifies a variant of an
205   operand type or limits values available to an operand type.
206
207   N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
208
209enum aarch64_opnd_qualifier
210{
211  /* Indicating no further qualification on an operand.  */
212  AARCH64_OPND_QLF_NIL,
213
214  /* Qualifying an operand which is a general purpose (integer) register;
215     indicating the operand data size or a specific register.  */
216  AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
217  AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
218  AARCH64_OPND_QLF_WSP, /* WSP.  */
219  AARCH64_OPND_QLF_SP,  /* SP.  */
220
221  /* Qualifying an operand which is a floating-point register, a SIMD
222     vector element or a SIMD vector element list; indicating operand data
223     size or the size of each SIMD vector element in the case of a SIMD
224     vector element list.
225     These qualifiers are also used to qualify an address operand to
226     indicate the size of data element a load/store instruction is
227     accessing.
228     They are also used for the immediate shift operand in e.g. SSHR.  Such
229     a use is only for the ease of operand encoding/decoding and qualifier
230     sequence matching; such a use should not be applied widely; use the value
231     constraint qualifiers for immediate operands wherever possible.  */
232  AARCH64_OPND_QLF_S_B,
233  AARCH64_OPND_QLF_S_H,
234  AARCH64_OPND_QLF_S_S,
235  AARCH64_OPND_QLF_S_D,
236  AARCH64_OPND_QLF_S_Q,
237
238  /* Qualifying an operand which is a SIMD vector register or a SIMD vector
239     register list; indicating register shape.
240     They are also used for the immediate shift operand in e.g. SSHR.  Such
241     a use is only for the ease of operand encoding/decoding and qualifier
242     sequence matching; such a use should not be applied widely; use the value
243     constraint qualifiers for immediate operands wherever possible.  */
244  AARCH64_OPND_QLF_V_8B,
245  AARCH64_OPND_QLF_V_16B,
246  AARCH64_OPND_QLF_V_4H,
247  AARCH64_OPND_QLF_V_8H,
248  AARCH64_OPND_QLF_V_2S,
249  AARCH64_OPND_QLF_V_4S,
250  AARCH64_OPND_QLF_V_1D,
251  AARCH64_OPND_QLF_V_2D,
252  AARCH64_OPND_QLF_V_1Q,
253
254  /* Constraint on value.  */
255  AARCH64_OPND_QLF_imm_0_7,
256  AARCH64_OPND_QLF_imm_0_15,
257  AARCH64_OPND_QLF_imm_0_31,
258  AARCH64_OPND_QLF_imm_0_63,
259  AARCH64_OPND_QLF_imm_1_32,
260  AARCH64_OPND_QLF_imm_1_64,
261
262  /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
263     or shift-ones.  */
264  AARCH64_OPND_QLF_LSL,
265  AARCH64_OPND_QLF_MSL,
266
267  /* Special qualifier helping retrieve qualifier information during the
268     decoding time (currently not in use).  */
269  AARCH64_OPND_QLF_RETRIEVE,
270};
271
272/* Instruction class.  */
273
274enum aarch64_insn_class
275{
276  addsub_carry,
277  addsub_ext,
278  addsub_imm,
279  addsub_shift,
280  asimdall,
281  asimddiff,
282  asimdelem,
283  asimdext,
284  asimdimm,
285  asimdins,
286  asimdmisc,
287  asimdperm,
288  asimdsame,
289  asimdshf,
290  asimdtbl,
291  asisddiff,
292  asisdelem,
293  asisdlse,
294  asisdlsep,
295  asisdlso,
296  asisdlsop,
297  asisdmisc,
298  asisdone,
299  asisdpair,
300  asisdsame,
301  asisdshf,
302  bitfield,
303  branch_imm,
304  branch_reg,
305  compbranch,
306  condbranch,
307  condcmp_imm,
308  condcmp_reg,
309  condsel,
310  cryptoaes,
311  cryptosha2,
312  cryptosha3,
313  dp_1src,
314  dp_2src,
315  dp_3src,
316  exception,
317  extract,
318  float2fix,
319  float2int,
320  floatccmp,
321  floatcmp,
322  floatdp1,
323  floatdp2,
324  floatdp3,
325  floatimm,
326  floatsel,
327  ldst_immpost,
328  ldst_immpre,
329  ldst_imm9,    /* immpost or immpre */
330  ldst_pos,
331  ldst_regoff,
332  ldst_unpriv,
333  ldst_unscaled,
334  ldstexcl,
335  ldstnapair_offs,
336  ldstpair_off,
337  ldstpair_indexed,
338  loadlit,
339  log_imm,
340  log_shift,
341  movewide,
342  pcreladdr,
343  ic_system,
344  testbranch,
345};
346
347/* Opcode enumerators.  */
348
349enum aarch64_op
350{
351  OP_NIL,
352  OP_STRB_POS,
353  OP_LDRB_POS,
354  OP_LDRSB_POS,
355  OP_STRH_POS,
356  OP_LDRH_POS,
357  OP_LDRSH_POS,
358  OP_STR_POS,
359  OP_LDR_POS,
360  OP_STRF_POS,
361  OP_LDRF_POS,
362  OP_LDRSW_POS,
363  OP_PRFM_POS,
364
365  OP_STURB,
366  OP_LDURB,
367  OP_LDURSB,
368  OP_STURH,
369  OP_LDURH,
370  OP_LDURSH,
371  OP_STUR,
372  OP_LDUR,
373  OP_STURV,
374  OP_LDURV,
375  OP_LDURSW,
376  OP_PRFUM,
377
378  OP_LDR_LIT,
379  OP_LDRV_LIT,
380  OP_LDRSW_LIT,
381  OP_PRFM_LIT,
382
383  OP_ADD,
384  OP_B,
385  OP_BL,
386
387  OP_MOVN,
388  OP_MOVZ,
389  OP_MOVK,
390
391  OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
392  OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
393  OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
394
395  OP_MOV_V,             /* MOV alias for moving vector register.  */
396
397  OP_ASR_IMM,
398  OP_LSR_IMM,
399  OP_LSL_IMM,
400
401  OP_BIC,
402
403  OP_UBFX,
404  OP_BFXIL,
405  OP_SBFX,
406  OP_SBFIZ,
407  OP_BFI,
408  OP_UBFIZ,
409  OP_UXTB,
410  OP_UXTH,
411  OP_UXTW,
412
413  OP_CINC,
414  OP_CINV,
415  OP_CNEG,
416  OP_CSET,
417  OP_CSETM,
418
419  OP_FCVT,
420  OP_FCVTN,
421  OP_FCVTN2,
422  OP_FCVTL,
423  OP_FCVTL2,
424  OP_FCVTXN_S,          /* Scalar version.  */
425
426  OP_ROR_IMM,
427
428  OP_SXTL,
429  OP_SXTL2,
430  OP_UXTL,
431  OP_UXTL2,
432
433  OP_TOTAL_NUM,         /* Pseudo.  */
434};
435
436/* Maximum number of operands an instruction can have.  */
437#define AARCH64_MAX_OPND_NUM 6
438/* Maximum number of qualifier sequences an instruction can have.  */
439#define AARCH64_MAX_QLF_SEQ_NUM 10
440/* Operand qualifier typedef; optimized for the size.  */
441typedef unsigned char aarch64_opnd_qualifier_t;
442/* Operand qualifier sequence typedef.  */
443typedef aarch64_opnd_qualifier_t        \
444          aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
445
446/* FIXME: improve the efficiency.  */
447static inline bfd_boolean
448empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
449{
450  int i;
451  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
452    if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
453      return FALSE;
454  return TRUE;
455}
456
457/* This structure holds information for a particular opcode.  */
458
459struct aarch64_opcode
460{
461  /* The name of the mnemonic.  */
462  const char *name;
463
464  /* The opcode itself.  Those bits which will be filled in with
465     operands are zeroes.  */
466  aarch64_insn opcode;
467
468  /* The opcode mask.  This is used by the disassembler.  This is a
469     mask containing ones indicating those bits which must match the
470     opcode field, and zeroes indicating those bits which need not
471     match (and are presumably filled in by operands).  */
472  aarch64_insn mask;
473
474  /* Instruction class.  */
475  enum aarch64_insn_class iclass;
476
477  /* Enumerator identifier.  */
478  enum aarch64_op op;
479
480  /* Which architecture variant provides this instruction.  */
481  const aarch64_feature_set *avariant;
482
483  /* An array of operand codes.  Each code is an index into the
484     operand table.  They appear in the order which the operands must
485     appear in assembly code, and are terminated by a zero.  */
486  enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
487
488  /* A list of operand qualifier code sequence.  Each operand qualifier
489     code qualifies the corresponding operand code.  Each operand
490     qualifier sequence specifies a valid opcode variant and related
491     constraint on operands.  */
492  aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
493
494  /* Flags providing information about this instruction */
495  uint32_t flags;
496};
497
498typedef struct aarch64_opcode aarch64_opcode;
499
500/* Table describing all the AArch64 opcodes.  */
501extern aarch64_opcode aarch64_opcode_table[];
502
503/* Opcode flags.  */
504#define F_ALIAS (1 << 0)
505#define F_HAS_ALIAS (1 << 1)
506/* Disassembly preference priority 1-3 (the larger the higher).  If nothing
507   is specified, it is the priority 0 by default, i.e. the lowest priority.  */
508#define F_P1 (1 << 2)
509#define F_P2 (2 << 2)
510#define F_P3 (3 << 2)
511/* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
512#define F_COND (1 << 4)
513/* Instruction has the field of 'sf'.  */
514#define F_SF (1 << 5)
515/* Instruction has the field of 'size:Q'.  */
516#define F_SIZEQ (1 << 6)
517/* Floating-point instruction has the field of 'type'.  */
518#define F_FPTYPE (1 << 7)
519/* AdvSIMD scalar instruction has the field of 'size'.  */
520#define F_SSIZE (1 << 8)
521/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
522#define F_T (1 << 9)
523/* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
524#define F_GPRSIZE_IN_Q (1 << 10)
525/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
526#define F_LDS_SIZE (1 << 11)
527/* Optional operand; assume maximum of 1 operand can be optional.  */
528#define F_OPD0_OPT (1 << 12)
529#define F_OPD1_OPT (2 << 12)
530#define F_OPD2_OPT (3 << 12)
531#define F_OPD3_OPT (4 << 12)
532#define F_OPD4_OPT (5 << 12)
533/* Default value for the optional operand when omitted from the assembly.  */
534#define F_DEFAULT(X) (((X) & 0x1f) << 15)
535/* Instruction that is an alias of another instruction needs to be
536   encoded/decoded by converting it to/from the real form, followed by
537   the encoding/decoding according to the rules of the real opcode.
538   This compares to the direct coding using the alias's information.
539   N.B. this flag requires F_ALIAS to be used together.  */
540#define F_CONV (1 << 20)
541/* Use together with F_ALIAS to indicate an alias opcode is a programmer
542   friendly pseudo instruction available only in the assembly code (thus will
543   not show up in the disassembly).  */
544#define F_PSEUDO (1 << 21)
545/* Instruction has miscellaneous encoding/decoding rules.  */
546#define F_MISC (1 << 22)
547/* Instruction has the field of 'N'; used in conjunction with F_SF.  */
548#define F_N (1 << 23)
549/* Opcode dependent field.  */
550#define F_OD(X) (((X) & 0x7) << 24)
551/* Next bit is 27.  */
552
553static inline bfd_boolean
554alias_opcode_p (const aarch64_opcode *opcode)
555{
556  return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
557}
558
559static inline bfd_boolean
560opcode_has_alias (const aarch64_opcode *opcode)
561{
562  return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
563}
564
565/* Priority for disassembling preference.  */
566static inline int
567opcode_priority (const aarch64_opcode *opcode)
568{
569  return (opcode->flags >> 2) & 0x3;
570}
571
572static inline bfd_boolean
573pseudo_opcode_p (const aarch64_opcode *opcode)
574{
575  return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
576}
577
578static inline bfd_boolean
579optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
580{
581  return (((opcode->flags >> 12) & 0x7) == idx + 1)
582    ? TRUE : FALSE;
583}
584
585static inline aarch64_insn
586get_optional_operand_default_value (const aarch64_opcode *opcode)
587{
588  return (opcode->flags >> 15) & 0x1f;
589}
590
591static inline unsigned int
592get_opcode_dependent_value (const aarch64_opcode *opcode)
593{
594  return (opcode->flags >> 24) & 0x7;
595}
596
597static inline bfd_boolean
598opcode_has_special_coder (const aarch64_opcode *opcode)
599{
600  return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
601          | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
602    : FALSE;
603}
604
605struct aarch64_name_value_pair
606{
607  const char *  name;
608  aarch64_insn  value;
609};
610
611extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
612extern const struct aarch64_name_value_pair aarch64_sys_regs [];
613extern const struct aarch64_name_value_pair aarch64_pstatefields [];
614extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
615extern const struct aarch64_name_value_pair aarch64_prfops [32];
616
617typedef struct
618{
619  const char *template;
620  uint32_t value;
621  int has_xt;
622} aarch64_sys_ins_reg;
623
624extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
625extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
626extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
627extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
628
629/* Shift/extending operator kinds.
630   N.B. order is important; keep aarch64_operand_modifiers synced.  */
631enum aarch64_modifier_kind
632{
633  AARCH64_MOD_NONE,
634  AARCH64_MOD_MSL,
635  AARCH64_MOD_ROR,
636  AARCH64_MOD_ASR,
637  AARCH64_MOD_LSR,
638  AARCH64_MOD_LSL,
639  AARCH64_MOD_UXTB,
640  AARCH64_MOD_UXTH,
641  AARCH64_MOD_UXTW,
642  AARCH64_MOD_UXTX,
643  AARCH64_MOD_SXTB,
644  AARCH64_MOD_SXTH,
645  AARCH64_MOD_SXTW,
646  AARCH64_MOD_SXTX,
647};
648
649bfd_boolean
650aarch64_extend_operator_p (enum aarch64_modifier_kind);
651
652enum aarch64_modifier_kind
653aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
654/* Condition.  */
655
656typedef struct
657{
658  /* A list of names with the first one as the disassembly preference;
659     terminated by NULL if fewer than 3.  */
660  const char *names[3];
661  aarch64_insn value;
662} aarch64_cond;
663
664extern const aarch64_cond aarch64_conds[16];
665
666const aarch64_cond* get_cond_from_value (aarch64_insn value);
667const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
668
669/* Structure representing an operand.  */
670
671struct aarch64_opnd_info
672{
673  enum aarch64_opnd type;
674  aarch64_opnd_qualifier_t qualifier;
675  int idx;
676
677  union
678    {
679      struct
680        {
681          unsigned regno;
682        } reg;
683      struct
684        {
685          unsigned regno : 5;
686          unsigned index : 4;
687        } reglane;
688      /* e.g. LVn.  */
689      struct
690        {
691          unsigned first_regno : 5;
692          unsigned num_regs : 3;
693          /* 1 if it is a list of reg element.  */
694          unsigned has_index : 1;
695          /* Lane index; valid only when has_index is 1.  */
696          unsigned index : 4;
697        } reglist;
698      /* e.g. immediate or pc relative address offset.  */
699      struct
700        {
701          int64_t value;
702          unsigned is_fp : 1;
703        } imm;
704      /* e.g. address in STR (register offset).  */
705      struct
706        {
707          unsigned base_regno;
708          struct
709            {
710              union
711                {
712                  int imm;
713                  unsigned regno;
714                };
715              unsigned is_reg;
716            } offset;
717          unsigned pcrel : 1;           /* PC-relative.  */
718          unsigned writeback : 1;
719          unsigned preind : 1;          /* Pre-indexed.  */
720          unsigned postind : 1;         /* Post-indexed.  */
721        } addr;
722      const aarch64_cond *cond;
723      /* The encoding of the system register.  */
724      aarch64_insn sysreg;
725      /* The encoding of the PSTATE field.  */
726      aarch64_insn pstatefield;
727      const aarch64_sys_ins_reg *sysins_op;
728      const struct aarch64_name_value_pair *barrier;
729      const struct aarch64_name_value_pair *prfop;
730    };
731
732  /* Operand shifter; in use when the operand is a register offset address,
733     add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
734  struct
735    {
736      enum aarch64_modifier_kind kind;
737      int amount;
738      unsigned operator_present: 1;     /* Only valid during encoding.  */
739      /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
740      unsigned amount_present: 1;
741    } shifter;
742
743  unsigned skip:1;      /* Operand is not completed if there is a fixup needed
744                           to be done on it.  In some (but not all) of these
745                           cases, we need to tell libopcodes to skip the
746                           constraint checking and the encoding for this
747                           operand, so that the libopcodes can pick up the
748                           right opcode before the operand is fixed-up.  This
749                           flag should only be used during the
750                           assembling/encoding.  */
751  unsigned present:1;   /* Whether this operand is present in the assembly
752                           line; not used during the disassembly.  */
753};
754
755typedef struct aarch64_opnd_info aarch64_opnd_info;
756
757/* Structure representing an instruction.
758
759   It is used during both the assembling and disassembling.  The assembler
760   fills an aarch64_inst after a successful parsing and then passes it to the
761   encoding routine to do the encoding.  During the disassembling, the
762   disassembler calls the decoding routine to decode a binary instruction; on a
763   successful return, such a structure will be filled with information of the
764   instruction; then the disassembler uses the information to print out the
765   instruction.  */
766
767struct aarch64_inst
768{
769  /* The value of the binary instruction.  */
770  aarch64_insn value;
771
772  /* Corresponding opcode entry.  */
773  const aarch64_opcode *opcode;
774
775  /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
776  const aarch64_cond *cond;
777
778  /* Operands information.  */
779  aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
780};
781
782typedef struct aarch64_inst aarch64_inst;
783
784/* Diagnosis related declaration and interface.  */
785
786/* Operand error kind enumerators.
787
788   AARCH64_OPDE_RECOVERABLE
789     Less severe error found during the parsing, very possibly because that
790     GAS has picked up a wrong instruction template for the parsing.
791
792   AARCH64_OPDE_SYNTAX_ERROR
793     General syntax error; it can be either a user error, or simply because
794     that GAS is trying a wrong instruction template.
795
796   AARCH64_OPDE_FATAL_SYNTAX_ERROR
797     Definitely a user syntax error.
798
799   AARCH64_OPDE_INVALID_VARIANT
800     No syntax error, but the operands are not a valid combination, e.g.
801     FMOV D0,S0
802
803   AARCH64_OPDE_OUT_OF_RANGE
804     Error about some immediate value out of a valid range.
805
806   AARCH64_OPDE_UNALIGNED
807     Error about some immediate value not properly aligned (i.e. not being a
808     multiple times of a certain value).
809
810   AARCH64_OPDE_REG_LIST
811     Error about the register list operand having unexpected number of
812     registers.
813
814   AARCH64_OPDE_OTHER_ERROR
815     Error of the highest severity and used for any severe issue that does not
816     fall into any of the above categories.
817
818   The enumerators are only interesting to GAS.  They are declared here (in
819   libopcodes) because that some errors are detected (and then notified to GAS)
820   by libopcodes (rather than by GAS solely).
821
822   The first three errors are only deteced by GAS while the
823   AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
824   only libopcodes has the information about the valid variants of each
825   instruction.
826
827   The enumerators have an increasing severity.  This is helpful when there are
828   multiple instruction templates available for a given mnemonic name (e.g.
829   FMOV); this mechanism will help choose the most suitable template from which
830   the generated diagnostics can most closely describe the issues, if any.  */
831
832enum aarch64_operand_error_kind
833{
834  AARCH64_OPDE_NIL,
835  AARCH64_OPDE_RECOVERABLE,
836  AARCH64_OPDE_SYNTAX_ERROR,
837  AARCH64_OPDE_FATAL_SYNTAX_ERROR,
838  AARCH64_OPDE_INVALID_VARIANT,
839  AARCH64_OPDE_OUT_OF_RANGE,
840  AARCH64_OPDE_UNALIGNED,
841  AARCH64_OPDE_REG_LIST,
842  AARCH64_OPDE_OTHER_ERROR
843};
844
845/* N.B. GAS assumes that this structure work well with shallow copy.  */
846struct aarch64_operand_error
847{
848  enum aarch64_operand_error_kind kind;
849  int index;
850  const char *error;
851  int data[3];  /* Some data for extra information.  */
852};
853
854typedef struct aarch64_operand_error aarch64_operand_error;
855
856/* Encoding entrypoint.  */
857
858extern int
859aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
860                       aarch64_insn *, aarch64_opnd_qualifier_t *,
861                       aarch64_operand_error *);
862
863extern const aarch64_opcode *
864aarch64_replace_opcode (struct aarch64_inst *,
865                        const aarch64_opcode *);
866
867/* Given the opcode enumerator OP, return the pointer to the corresponding
868   opcode entry.  */
869
870extern const aarch64_opcode *
871aarch64_get_opcode (enum aarch64_op);
872
873/* Generate the string representation of an operand.  */
874extern void
875aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
876                       const aarch64_opnd_info *, int, int *, bfd_vma *);
877
878/* Miscellaneous interface.  */
879
880extern int
881aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
882
883extern aarch64_opnd_qualifier_t
884aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
885                                const aarch64_opnd_qualifier_t, int);
886
887extern int
888aarch64_num_of_operands (const aarch64_opcode *);
889
890extern int
891aarch64_stack_pointer_p (const aarch64_opnd_info *);
892
893extern
894int aarch64_zero_register_p (const aarch64_opnd_info *);
895
896/* Given an operand qualifier, return the expected data element size
897   of a qualified operand.  */
898extern unsigned char
899aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
900
901extern enum aarch64_operand_class
902aarch64_get_operand_class (enum aarch64_opnd);
903
904extern const char *
905aarch64_get_operand_name (enum aarch64_opnd);
906
907extern const char *
908aarch64_get_operand_desc (enum aarch64_opnd);
909
910#ifdef DEBUG_AARCH64
911extern int debug_dump;
912
913extern void
914aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
915
916#define DEBUG_TRACE(M, ...)                                     \
917  {                                                             \
918    if (debug_dump)                                             \
919      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
920  }
921
922#define DEBUG_TRACE_IF(C, M, ...)                               \
923  {                                                             \
924    if (debug_dump && (C))                                      \
925      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
926  }
927#else  /* !DEBUG_AARCH64 */
928#define DEBUG_TRACE(M, ...) ;
929#define DEBUG_TRACE_IF(C, M, ...) ;
930#endif /* DEBUG_AARCH64 */
931
932#endif /* OPCODE_AARCH64_H */
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