| [444] | 1 | /* ARM assembler/disassembler support. |
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| 2 | Copyright 2004, 2010, 2011 Free Software Foundation, Inc. |
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| 3 | |
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| 4 | This file is part of GDB and GAS. |
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| 5 | |
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| 6 | GDB and GAS are free software; you can redistribute it and/or |
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| 7 | modify it under the terms of the GNU General Public License as |
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| 8 | published by the Free Software Foundation; either version 3, or (at |
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| 9 | your option) any later version. |
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| 10 | |
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| 11 | GDB and GAS are distributed in the hope that it will be useful, but |
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| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | General Public License for more details. |
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| 15 | |
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| 16 | You should have received a copy of the GNU General Public License |
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| 17 | along with GDB or GAS; see the file COPYING3. If not, write to the |
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| 18 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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| 19 | MA 02110-1301, USA. */ |
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| 20 | |
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| 21 | /* The following bitmasks control CPU extensions: */ |
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| 22 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ |
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| 23 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ |
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| 24 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ |
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| 25 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ |
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| 26 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ |
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| 27 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ |
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| 28 | #define ARM_EXT_V4T 0x00000040 /* Thumb. */ |
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| 29 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ |
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| 30 | #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ |
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| 31 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ |
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| 32 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ |
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| 33 | #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ |
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| 34 | #define ARM_EXT_V6 0x00001000 /* ARM V6. */ |
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| 35 | #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ |
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| 36 | /* 0x00004000 Was ARM V6Z. */ |
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| 37 | #define ARM_EXT_V8 0x00004000 /* is now ARMv8. */ |
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| 38 | #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ |
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| 39 | #define ARM_EXT_DIV 0x00010000 /* Integer division. */ |
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| 40 | /* The 'M' in Arm V7M stands for Microcontroller. |
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| 41 | On earlier architecture variants it stands for Multiply. */ |
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| 42 | #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ |
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| 43 | #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ |
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| 44 | #define ARM_EXT_V7 0x00080000 /* Arm V7. */ |
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| 45 | #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ |
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| 46 | #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ |
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| 47 | #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ |
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| 48 | #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ |
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| 49 | #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ |
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| 50 | #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ |
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| 51 | #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), |
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| 52 | not in v7-M. */ |
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| 53 | #define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ |
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| 54 | #define ARM_EXT_SEC 0x10000000 /* Security extensions. */ |
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| 55 | #define ARM_EXT_OS 0x20000000 /* OS Extensions. */ |
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| 56 | #define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM |
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| 57 | state. */ |
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| 58 | #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ |
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| 59 | |
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| 60 | /* Co-processor space extensions. */ |
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| 61 | #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ |
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| 62 | #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ |
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| 63 | #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ |
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| 64 | #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ |
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| 65 | |
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| 66 | #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ |
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| 67 | #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ |
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| 68 | #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ |
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| 69 | #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ |
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| 70 | #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ |
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| 71 | #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ |
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| 72 | #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ |
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| 73 | #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ |
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| 74 | #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ |
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| 75 | #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ |
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| 76 | #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ |
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| 77 | #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ |
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| 78 | #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ |
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| 79 | #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ |
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| 80 | #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ |
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| 81 | #define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ |
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| 82 | #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ |
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| 83 | #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ |
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| 84 | #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ |
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| 85 | |
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| 86 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) |
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| 87 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, |
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| 88 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add |
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| 89 | three more to cover cores prior to ARM6. Finally, there are cores which |
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| 90 | implement further extensions in the co-processor space. */ |
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| 91 | #define ARM_AEXT_V1 ARM_EXT_V1 |
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| 92 | #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) |
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| 93 | #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) |
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| 94 | #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) |
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| 95 | #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) |
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| 96 | #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) |
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| 97 | #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) |
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| 98 | #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) |
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| 99 | #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) |
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| 100 | #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) |
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| 101 | #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) |
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| 102 | #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) |
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| 103 | #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) |
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| 104 | #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) |
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| 105 | #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) |
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| 106 | #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) |
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| 107 | #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) |
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| 108 | #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) |
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| 109 | #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) |
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| 110 | #define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC) |
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| 111 | #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ |
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| 112 | | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ |
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| 113 | | ARM_EXT_V6_DSP ) |
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| 114 | #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) |
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| 115 | #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) |
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| 116 | #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) |
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| 117 | #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) |
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| 118 | #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) |
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| 119 | #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) |
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| 120 | #define ARM_AEXT_NOTM \ |
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| 121 | (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ |
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| 122 | | ARM_EXT_V6_DSP ) |
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| 123 | #define ARM_AEXT_V6M_ONLY \ |
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| 124 | ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) |
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| 125 | #define ARM_AEXT_V6M \ |
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| 126 | ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) |
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| 127 | #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) |
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| 128 | #define ARM_AEXT_V7M \ |
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| 129 | ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ |
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| 130 | & ~(ARM_AEXT_NOTM)) |
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| 131 | #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) |
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| 132 | #define ARM_AEXT_V7EM \ |
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| 133 | (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) |
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| 134 | #define ARM_AEXT_V8A \ |
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| 135 | (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ |
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| 136 | | ARM_EXT_VIRT | ARM_EXT_V8) |
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| 137 | |
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| 138 | /* Processors with specific extensions in the co-processor space. */ |
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| 139 | #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
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| 140 | #define ARM_ARCH_IWMMXT \ |
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| 141 | ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) |
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| 142 | #define ARM_ARCH_IWMMXT2 \ |
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| 143 | ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) |
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| 144 | |
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| 145 | #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) |
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| 146 | #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) |
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| 147 | #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) |
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| 148 | #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) |
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| 149 | #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) |
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| 150 | #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) |
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| 151 | #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
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| 152 | #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
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| 153 | #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
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| 154 | #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) |
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| 155 | #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) |
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| 156 | #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) |
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| 157 | #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ |
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| 158 | | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ |
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| 159 | | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) |
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| 160 | #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) |
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| 161 | |
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| 162 | /* Deprecated. */ |
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| 163 | #define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) |
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| 164 | |
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| 165 | #define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) |
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| 166 | #define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) |
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| 167 | |
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| 168 | #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) |
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| 169 | #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) |
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| 170 | #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) |
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| 171 | #define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) |
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| 172 | #define FPU_ARCH_VFP_V3D16_FP16 \ |
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| 173 | ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) |
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| 174 | #define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) |
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| 175 | #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) |
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| 176 | #define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) |
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| 177 | #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) |
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| 178 | #define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) |
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| 179 | #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ |
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| 180 | ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) |
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| 181 | #define FPU_ARCH_NEON_FP16 \ |
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| 182 | ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) |
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| 183 | #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) |
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| 184 | #define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) |
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| 185 | #define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) |
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| 186 | #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) |
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| 187 | #define FPU_ARCH_NEON_VFP_V4 \ |
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| 188 | ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) |
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| 189 | #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) |
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| 190 | #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
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| 191 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ |
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| 192 | ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
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| 193 | #define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8) |
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| 194 | |
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| 195 | #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) |
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| 196 | |
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| 197 | #define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) |
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| 198 | |
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| 199 | #define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) |
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| 200 | #define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) |
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| 201 | #define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) |
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| 202 | #define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) |
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| 203 | #define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) |
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| 204 | #define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) |
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| 205 | #define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) |
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| 206 | #define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) |
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| 207 | #define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) |
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| 208 | #define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) |
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| 209 | #define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) |
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| 210 | #define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) |
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| 211 | #define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) |
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| 212 | #define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) |
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| 213 | #define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) |
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| 214 | #define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) |
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| 215 | #define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) |
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| 216 | #define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) |
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| 217 | #define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) |
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| 218 | #define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) |
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| 219 | #define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) |
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| 220 | #define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) |
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| 221 | #define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) |
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| 222 | #define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) |
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| 223 | #define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) |
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| 224 | #define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) |
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| 225 | #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) |
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| 226 | #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) |
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| 227 | #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) |
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| 228 | #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) |
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| 229 | #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) |
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| 230 | #define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) |
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| 231 | |
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| 232 | /* Some useful combinations: */ |
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| 233 | #define ARM_ARCH_NONE ARM_FEATURE (0, 0) |
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| 234 | #define FPU_NONE ARM_FEATURE (0, 0) |
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| 235 | #define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ |
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| 236 | #define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) |
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| 237 | #define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) |
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| 238 | /* v7-a+sec. */ |
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| 239 | #define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0) |
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| 240 | /* v7-a+mp+sec. */ |
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| 241 | #define ARM_ARCH_V7A_MP_SEC \ |
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| 242 | ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ |
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| 243 | 0) |
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| 244 | /* v7-a+idiv+mp+sec+virt. */ |
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| 245 | #define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \ |
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| 246 | ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \ |
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| 247 | | ARM_EXT_DIV | ARM_EXT_ADIV \ |
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| 248 | | ARM_EXT_VIRT, 0) |
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| 249 | /* v7-r+idiv. */ |
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| 250 | #define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) |
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| 251 | /* Features that are present in v6M and v6S-M but not other v6 cores. */ |
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| 252 | #define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) |
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| 253 | /* v8-a+fp. */ |
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| 254 | #define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) |
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| 255 | /* v8-a+simd (implies fp). */ |
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| 256 | #define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ |
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| 257 | FPU_ARCH_NEON_VFP_ARMV8) |
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| 258 | /* v8-a+crypto (implies simd+fp). */ |
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| 259 | #define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ |
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| 260 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) |
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| 261 | |
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| 262 | /* There are too many feature bits to fit in a single word, so use a |
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| 263 | structure. For simplicity we put all core features in one word and |
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| 264 | everything else in the other. */ |
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| 265 | typedef struct |
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| 266 | { |
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| 267 | unsigned long core; |
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| 268 | unsigned long coproc; |
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| 269 | } arm_feature_set; |
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| 270 | |
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| 271 | #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ |
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| 272 | (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) |
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| 273 | |
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| 274 | #define ARM_CPU_IS_ANY(CPU) \ |
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| 275 | ((CPU).core == ((arm_feature_set)ARM_ANY).core) |
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| 276 | |
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| 277 | #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
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| 278 | do { \ |
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| 279 | (TARG).core = (F1).core | (F2).core; \ |
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| 280 | (TARG).coproc = (F1).coproc | (F2).coproc; \ |
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| 281 | } while (0) |
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| 282 | |
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| 283 | #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ |
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| 284 | do { \ |
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| 285 | (TARG).core = (F1).core &~ (F2).core; \ |
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| 286 | (TARG).coproc = (F1).coproc &~ (F2).coproc; \ |
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| 287 | } while (0) |
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| 288 | |
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| 289 | #define ARM_FEATURE(core, coproc) {(core), (coproc)} |
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