source: trunk/libs/newlib/src/include/opcode/m68k.h @ 482

Last change on this file since 482 was 444, checked in by satin@…, 6 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc

File size: 14.5 KB
Line 
1/* Opcode table header for m680[01234]0/m6888[12]/m68851.
2   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
3   2003, 2004, 2006, 2010 Free Software Foundation, Inc.
4
5   This file is part of GDB, GAS, and the GNU binutils.
6
7   GDB, GAS, and the GNU binutils are free software; you can redistribute
8   them and/or modify them under the terms of the GNU General Public
9   License as published by the Free Software Foundation; either version 3,
10   or (at your option) any later version.
11
12   GDB, GAS, and the GNU binutils are distributed in the hope that they
13   will be useful, but WITHOUT ANY WARRANTY; without even the implied
14   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
15   the GNU General Public License for more details.
16
17   You should have received a copy of the GNU General Public License
18   along with this file; see the file COPYING3.  If not, write to the Free
19   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20   02110-1301, USA.  */
21
22/* These are used as bit flags for the arch field in the m68k_opcode
23   structure.  */
24#define _m68k_undef  0
25#define m68000   0x001
26#define m68010   0x002
27#define m68020   0x004
28#define m68030   0x008
29#define m68040   0x010
30#define m68060   0x020
31#define m68881   0x040
32#define m68851   0x080
33#define cpu32    0x100          /* e.g., 68332 */
34#define fido_a   0x200
35#define m68k_mask  0x3ff
36
37#define mcfmac   0x400          /* ColdFire MAC. */
38#define mcfemac  0x800          /* ColdFire EMAC. */
39#define cfloat   0x1000         /* ColdFire FPU.  */
40#define mcfhwdiv 0x2000         /* ColdFire hardware divide.  */
41
42#define mcfisa_a 0x4000         /* ColdFire ISA_A.  */
43#define mcfisa_aa 0x8000        /* ColdFire ISA_A+.  */
44#define mcfisa_b 0x10000        /* ColdFire ISA_B.  */
45#define mcfisa_c 0x20000        /* ColdFire ISA_C.  */
46#define mcfusp   0x40000        /* ColdFire USP instructions.  */
47#define mcf_mask 0x7e400
48
49/* Handy aliases.  */
50#define m68040up   (m68040 | m68060)
51#define m68030up   (m68030 | m68040up)
52#define m68020up   (m68020 | m68030up)
53#define m68010up   (m68010 | cpu32 | fido_a | m68020up)
54#define m68000up   (m68000 | m68010up)
55
56#define mfloat  (m68881 | m68040 | m68060)
57#define mmmu    (m68851 | m68030 | m68040 | m68060)
58
59/* The structure used to hold information for an opcode.  */
60
61struct m68k_opcode
62{
63  /* The opcode name.  */
64  const char *name;
65  /* The pseudo-size of the instruction(in bytes).  Used to determine
66     number of bytes necessary to disassemble the instruction.  */
67  unsigned int size;
68  /* The opcode itself.  */
69  unsigned long opcode;
70  /* The mask used by the disassembler.  */
71  unsigned long match;
72  /* The arguments.  */
73  const char *args;
74  /* The architectures which support this opcode.  */
75  unsigned int arch;
76};
77
78/* The structure used to hold information for an opcode alias.  */
79
80struct m68k_opcode_alias
81{
82  /* The alias name.  */
83  const char *alias;
84  /* The instruction for which this is an alias.  */
85  const char *primary;
86};
87
88/* We store four bytes of opcode for all opcodes because that is the
89   most any of them need.  The actual length of an instruction is
90   always at least 2 bytes, and is as much longer as necessary to hold
91   the operands it has.
92
93   The match field is a mask saying which bits must match particular
94   opcode in order for an instruction to be an instance of that
95   opcode.
96
97   The args field is a string containing two characters for each
98   operand of the instruction.  The first specifies the kind of
99   operand; the second, the place it is stored.
100
101   If the first char of args is '.', it indicates that the opcode is
102   two words.  This is only necessary when the match field does not
103   have any bits set in the second opcode word.  Such a '.' is skipped
104   for operand processing.  */
105
106/* Kinds of operands:
107   Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+-
108
109   D  data register only.  Stored as 3 bits.
110   A  address register only.  Stored as 3 bits.
111   a  address register indirect only.  Stored as 3 bits.
112   R  either kind of register.  Stored as 4 bits.
113   r  either kind of register indirect only.  Stored as 4 bits.
114      At the moment, used only for cas2 instruction.
115   F  floating point coprocessor register only.   Stored as 3 bits.
116   O  an offset (or width): immediate data 0-31 or data register.
117      Stored as 6 bits in special format for BF... insns.
118   +  autoincrement only.  Stored as 3 bits (number of the address register).
119   -  autodecrement only.  Stored as 3 bits (number of the address register).
120   Q  quick immediate data.  Stored as 3 bits.
121      This matches an immediate operand only when value is in range 1 .. 8.
122   M  moveq immediate data.  Stored as 8 bits.
123      This matches an immediate operand only when value is in range -128..127
124   T  trap vector immediate data.  Stored as 4 bits.
125
126   k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
127      a three bit register offset, depending on the field type.
128
129   #  immediate data.  Stored in special places (b, w or l)
130      which say how many bits to store.
131   ^  immediate data for floating point instructions.   Special places
132      are offset by 2 bytes from '#'...
133   B  pc-relative address, converted to an offset
134      that is treated as immediate data.
135   d  displacement and register.  Stores the register as 3 bits
136      and stores the displacement in the entire second word.
137
138   C  the CCR.  No need to store it; this is just for filtering validity.
139   S  the SR.  No need to store, just as with CCR.
140   U  the USP.  No need to store, just as with CCR.
141   E  the MAC ACC.  No need to store, just as with CCR.
142   e  the EMAC ACC[0123].
143   G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
144   g  the EMAC ACCEXT{01,23}.
145   H  the MASK.  No need to store, just as with CCR.
146   i  the MAC/EMAC scale factor.
147
148   I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
149      extracted from the 'd' field of word one, which means that an extended
150      coprocessor opcode can be skipped using the 'i' place, if needed.
151
152   s  System Control register for the floating point coprocessor.
153
154   J  Misc register for movec instruction, stored in 'j' format.
155        Possible values:
156        0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
157        0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
158        0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
159        0x003   TC      MMU Translation Control         [60, 40]
160        0x004   ITT0    Instruction Transparent
161                                Translation reg 0       [60, 40]
162        0x005   ITT1    Instruction Transparent
163                                Translation reg 1       [60, 40]
164        0x006   DTT0    Data Transparent
165                                Translation reg 0       [60, 40]
166        0x007   DTT1    Data Transparent
167                                Translation reg 1       [60, 40]
168        0x008   BUSCR   Bus Control Register            [60]
169        0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
170        0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
171        0x802   CAAR    Cache Address Register          [        30, 20]
172        0x803   MSP     Master Stack Pointer            [    40, 30, 20]
173        0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
174        0x805   MMUSR   MMU Status reg                  [    40]
175        0x806   URP     User Root Pointer               [60, 40]
176        0x807   SRP     Supervisor Root Pointer         [60, 40]
177        0x808   PCR     Processor Configuration reg     [60]
178        0xC00   ROMBAR  ROM Base Address Register       [520X]
179        0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
180        0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
181        0xC0F   MBAR0   RAM Base Address Register 0     [520X]
182        0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
183        0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
184
185    L  Register list of the type d0-d7/a0-a7 etc.
186       (New!  Improved!  Can also hold fp0-fp7, as well!)
187       The assembler tries to see if the registers match the insn by
188       looking at where the insn wants them stored.
189
190    l  Register list like L, but with all the bits reversed.
191       Used for going the other way. . .
192
193    c  cache identifier which may be "nc" for no cache, "ic"
194       for instruction cache, "dc" for data cache, or "bc"
195       for both caches.  Used in cinv and cpush.  Always
196       stored in position "d".
197
198    u  Any register, with ``upper'' or ``lower'' specification.  Used
199       in the mac instructions with size word.
200
201 The remainder are all stored as 6 bits using an address mode and a
202 register number; they differ in which addressing modes they match.
203
204   *  all                                       (modes 0-6,7.0-4)
205   ~  alterable memory                          (modes 2-6,7.0,7.1)
206                                                (not 0,1,7.2-4)
207   %  alterable                                 (modes 0-6,7.0,7.1)
208                                                (not 7.2-4)
209   ;  data                                      (modes 0,2-6,7.0-4)
210                                                (not 1)
211   @  data, but not immediate                   (modes 0,2-6,7.0-3)
212                                                (not 1,7.4)
213   !  control                                   (modes 2,5,6,7.0-3)
214                                                (not 0,1,3,4,7.4)
215   &  alterable control                         (modes 2,5,6,7.0,7.1)
216                                                (not 0,1,3,4,7.2-4)
217   $  alterable data                            (modes 0,2-6,7.0,7.1)
218                                                (not 1,7.2-4)
219   ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
220                                                (not 1,3,4,7.2-4)
221   /  control, or data register                 (modes 0,2,5,6,7.0-3)
222                                                (not 1,3,4,7.4)
223   >  *save operands                            (modes 2,4,5,6,7.0,7.1)
224                                                (not 0,1,3,7.2-4)
225   <  *restore operands                         (modes 2,3,5,6,7.0-3)
226                                                (not 0,1,4,7.4)
227
228   coldfire move operands:
229   m                                            (modes 0-4)
230   n                                            (modes 5,7.2)
231   o                                            (modes 6,7.0,7.1,7.3,7.4)
232   p                                            (modes 0-5)
233
234   coldfire bset/bclr/btst/mulsl/mulul operands:
235   q                                            (modes 0,2-5)
236   v                                            (modes 0,2-5,7.0,7.1)
237   b                                            (modes 0,2-5,7.2)
238   w                                            (modes 2-5,7.2)
239   y                                            (modes 2,5)
240   z                                            (modes 2,5,7.2)
241   x  mov3q immediate operand.
242   j  coprocessor ET operand.
243   K  coprocessor command number.
244   4                                            (modes 2,3,4,5)
245  */
246
247/* For the 68851:  */
248/* I didn't use much imagination in choosing the
249   following codes, so many of them aren't very
250   mnemonic. -rab
251
252   0  32 bit pmmu register
253        Possible values:
254        000     TC      Translation Control Register (68030, 68851)
255
256   1  16 bit pmmu register
257        111     AC      Access Control (68851)
258
259   2  8 bit pmmu register
260        100     CAL     Current Access Level (68851)
261        101     VAL     Validate Access Level (68851)
262        110     SCC     Stack Change Control (68851)
263
264   3  68030-only pmmu registers (32 bit)
265        010     TT0     Transparent Translation reg 0
266                        (aka Access Control reg 0 -- AC0 -- on 68ec030)
267        011     TT1     Transparent Translation reg 1
268                        (aka Access Control reg 1 -- AC1 -- on 68ec030)
269
270   W  wide pmmu registers
271        Possible values:
272        001     DRP     Dma Root Pointer (68851)
273        010     SRP     Supervisor Root Pointer (68030, 68851)
274        011     CRP     Cpu Root Pointer (68030, 68851)
275
276   f    function code register (68030, 68851)
277        0       SFC
278        1       DFC
279
280   V    VAL register only (68851)
281
282   X    BADx, BACx (16 bit)
283        100     BAD     Breakpoint Acknowledge Data (68851)
284        101     BAC     Breakpoint Acknowledge Control (68851)
285
286   Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
287   Z    PCSR (68851)
288
289   |    memory          (modes 2-6, 7.*)
290
291   t  address test level (68030 only)
292      Stored as 3 bits, range 0-7.
293      Also used for breakpoint instruction now.
294
295*/
296
297/* Places to put an operand, for non-general operands:
298   Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
299
300   s  source, low bits of first word.
301   d  dest, shifted 9 in first word
302   1  second word, shifted 12
303   2  second word, shifted 6
304   3  second word, shifted 0
305   4  third word, shifted 12
306   5  third word, shifted 6
307   6  third word, shifted 0
308   7  second word, shifted 7
309   8  second word, shifted 10
310   9  second word, shifted 5
311   E  second word, shifted 9
312   D  store in both place 1 and place 3; for divul and divsl.
313   B  first word, low byte, for branch displacements
314   W  second word (entire), for branch displacements
315   L  second and third words (entire), for branch displacements
316      (also overloaded for move16)
317   b  second word, low byte
318   w  second word (entire) [variable word/long branch offset for dbra]
319   W  second word (entire) (must be signed 16 bit value)
320   l  second and third word (entire)
321   g  variable branch offset for bra and similar instructions.
322      The place to store depends on the magnitude of offset.
323   t  store in both place 7 and place 8; for floating point operations
324   c  branch offset for cpBcc operations.
325      The place to store is word two if bit six of word one is zero,
326      and words two and three if bit six of word one is one.
327   i  Increment by two, to skip over coprocessor extended operands.   Only
328      works with the 'I' format.
329   k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
330      Also used for dynamic fmovem instruction.
331   C  floating point coprocessor constant - 7 bits.  Also used for static
332      K-factors...
333   j  Movec register #, stored in 12 low bits of second word.
334   m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
335      and remaining 3 bits of register shifted 9 bits in first word.
336      Indicate upper/lower in 1 bit shifted 7 bits in second word.
337      Use with `R' or `u' format.
338   n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
339      with MSB shifted 6 bits in first word and remaining 3 bits of
340      register shifted 9 bits in first word.  No upper/lower
341      indication is done.)  Use with `R' or `u' format.
342   o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
343      Indicate upper/lower in 1 bit shifted 7 bits in second word.
344      Use with `R' or `u' format.
345   M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
346      upper/lower in 1 bit shifted 6 bits in second word.  Use with
347      `R' or `u' format.
348   N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
349      upper/lower in 1 bit shifted 6 bits in second word.  Use with
350      `R' or `u' format.
351   h  shift indicator (scale factor), 1 bit shifted 10 in second word
352
353 Places to put operand, for general operands:
354   d  destination, shifted 6 bits in first word
355   b  source, at low bit of first word, and immediate uses one byte
356   w  source, at low bit of first word, and immediate uses two bytes
357   l  source, at low bit of first word, and immediate uses four bytes
358   s  source, at low bit of first word.
359      Used sometimes in contexts where immediate is not allowed anyway.
360   f  single precision float, low bit of 1st word, immediate uses 4 bytes
361   F  double precision float, low bit of 1st word, immediate uses 8 bytes
362   x  extended precision float, low bit of 1st word, immediate uses 12 bytes
363   p  packed float, low bit of 1st word, immediate uses 12 bytes
364   G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
365   H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
366   F  EMAC ACCx
367   f  EMAC ACCy
368   I  MAC/EMAC scale factor
369   /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
370   ]  first word, bit 10
371*/
372
373extern const struct m68k_opcode m68k_opcodes[];
374extern const struct m68k_opcode_alias m68k_opcode_aliases[];
375
376extern const int m68k_numopcodes, m68k_numaliases;
377
378/* end of m68k-opcode.h */
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