source: trunk/libs/newlib/src/include/opcode/mips.h @ 666

Last change on this file since 666 was 444, checked in by satin@…, 6 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc

File size: 67.1 KB
Line 
1/* mips.h.  Mips opcode list for GDB, the GNU debugger.
2   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3   2003, 2004, 2005, 2008, 2009, 2010, 2013
4   Free Software Foundation, Inc.
5   Contributed by Ralph Campbell and OSF
6   Commented and modified by Ian Lance Taylor, Cygnus Support
7
8   This file is part of GDB, GAS, and the GNU binutils.
9
10   GDB, GAS, and the GNU binutils are free software; you can redistribute
11   them and/or modify them under the terms of the GNU General Public
12   License as published by the Free Software Foundation; either version 3,
13   or (at your option) any later version.
14
15   GDB, GAS, and the GNU binutils are distributed in the hope that they
16   will be useful, but WITHOUT ANY WARRANTY; without even the implied
17   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
18   the GNU General Public License for more details.
19
20   You should have received a copy of the GNU General Public License
21   along with this file; see the file COPYING3.  If not, write to the Free
22   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23   MA 02110-1301, USA.  */
24
25#ifndef _MIPS_H_
26#define _MIPS_H_
27
28#include "bfd.h"
29
30/* These are bit masks and shift counts to use to access the various
31   fields of an instruction.  To retrieve the X field of an
32   instruction, use the expression
33        (i >> OP_SH_X) & OP_MASK_X
34   To set the same field (to j), use
35        i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
36
37   Make sure you use fields that are appropriate for the instruction,
38   of course.
39
40   The 'i' format uses OP, RS, RT and IMMEDIATE.
41
42   The 'j' format uses OP and TARGET.
43
44   The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
45
46   The 'b' format uses OP, RS, RT and DELTA.
47
48   The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
49
50   The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
51
52   A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
53   breakpoint instruction are not defined; Kane says the breakpoint
54   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
55   only use ten bits).  An optional two-operand form of break/sdbbp
56   allows the lower ten bits to be set too, and MIPS32 and later
57   architectures allow 20 bits to be set with a signal operand
58   (using CODE20).
59
60   The syscall instruction uses CODE20.
61
62   The general coprocessor instructions use COPZ.  */
63
64#define OP_MASK_OP              0x3f
65#define OP_SH_OP                26
66#define OP_MASK_RS              0x1f
67#define OP_SH_RS                21
68#define OP_MASK_FR              0x1f
69#define OP_SH_FR                21
70#define OP_MASK_FMT             0x1f
71#define OP_SH_FMT               21
72#define OP_MASK_BCC             0x7
73#define OP_SH_BCC               18
74#define OP_MASK_CODE            0x3ff
75#define OP_SH_CODE              16
76#define OP_MASK_CODE2           0x3ff
77#define OP_SH_CODE2             6
78#define OP_MASK_RT              0x1f
79#define OP_SH_RT                16
80#define OP_MASK_FT              0x1f
81#define OP_SH_FT                16
82#define OP_MASK_CACHE           0x1f
83#define OP_SH_CACHE             16
84#define OP_MASK_RD              0x1f
85#define OP_SH_RD                11
86#define OP_MASK_FS              0x1f
87#define OP_SH_FS                11
88#define OP_MASK_PREFX           0x1f
89#define OP_SH_PREFX             11
90#define OP_MASK_CCC             0x7
91#define OP_SH_CCC               8
92#define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
93#define OP_SH_CODE20            6
94#define OP_MASK_SHAMT           0x1f
95#define OP_SH_SHAMT             6
96#define OP_MASK_EXTLSB          OP_MASK_SHAMT
97#define OP_SH_EXTLSB            OP_SH_SHAMT
98#define OP_MASK_STYPE           OP_MASK_SHAMT
99#define OP_SH_STYPE             OP_SH_SHAMT
100#define OP_MASK_FD              0x1f
101#define OP_SH_FD                6
102#define OP_MASK_TARGET          0x3ffffff
103#define OP_SH_TARGET            0
104#define OP_MASK_COPZ            0x1ffffff
105#define OP_SH_COPZ              0
106#define OP_MASK_IMMEDIATE       0xffff
107#define OP_SH_IMMEDIATE         0
108#define OP_MASK_DELTA           0xffff
109#define OP_SH_DELTA             0
110#define OP_MASK_FUNCT           0x3f
111#define OP_SH_FUNCT             0
112#define OP_MASK_SPEC            0x3f
113#define OP_SH_SPEC              0
114#define OP_SH_LOCC              8       /* FP condition code.  */
115#define OP_SH_HICC              18      /* FP condition code.  */
116#define OP_MASK_CC              0x7
117#define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
118#define OP_MASK_COP1NORM        0x1     /* a single bit.  */
119#define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
120#define OP_MASK_COP1SPEC        0xf
121#define OP_MASK_COP1SCLR        0x4
122#define OP_MASK_COP1CMP         0x3
123#define OP_SH_COP1CMP           4
124#define OP_SH_FORMAT            21      /* FP short format field.  */
125#define OP_MASK_FORMAT          0x7
126#define OP_SH_TRUE              16
127#define OP_MASK_TRUE            0x1
128#define OP_SH_GE                17
129#define OP_MASK_GE              0x01
130#define OP_SH_UNSIGNED          16
131#define OP_MASK_UNSIGNED        0x1
132#define OP_SH_HINT              16
133#define OP_MASK_HINT            0x1f
134#define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
135#define OP_MASK_MMI             0x3f
136#define OP_SH_MMISUB            6
137#define OP_MASK_MMISUB          0x1f
138#define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
139#define OP_SH_PERFREG           1
140#define OP_SH_SEL               0       /* Coprocessor select field.  */
141#define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
142#define OP_SH_CODE19            6       /* 19 bit wait code.  */
143#define OP_MASK_CODE19          0x7ffff
144#define OP_SH_ALN               21
145#define OP_MASK_ALN             0x7
146#define OP_SH_VSEL              21
147#define OP_MASK_VSEL            0x1f
148#define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
149                                           but 0x8-0xf don't select bytes.  */
150#define OP_SH_VECBYTE           22
151#define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
152#define OP_SH_VECALIGN          21
153#define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
154#define OP_SH_INSMSB            11
155#define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
156#define OP_SH_EXTMSBD           11
157
158/* MIPS DSP ASE */
159#define OP_SH_DSPACC            11
160#define OP_MASK_DSPACC          0x3
161#define OP_SH_DSPACC_S          21
162#define OP_MASK_DSPACC_S        0x3
163#define OP_SH_DSPSFT            20
164#define OP_MASK_DSPSFT          0x3f
165#define OP_SH_DSPSFT_7          19
166#define OP_MASK_DSPSFT_7        0x7f
167#define OP_SH_SA3               21
168#define OP_MASK_SA3             0x7
169#define OP_SH_SA4               21
170#define OP_MASK_SA4             0xf
171#define OP_SH_IMM8              16
172#define OP_MASK_IMM8            0xff
173#define OP_SH_IMM10             16
174#define OP_MASK_IMM10           0x3ff
175#define OP_SH_WRDSP             11
176#define OP_MASK_WRDSP           0x3f
177#define OP_SH_RDDSP             16
178#define OP_MASK_RDDSP           0x3f
179#define OP_SH_BP                11
180#define OP_MASK_BP              0x3
181
182/* MIPS MT ASE */
183#define OP_SH_MT_U              5
184#define OP_MASK_MT_U            0x1
185#define OP_SH_MT_H              4
186#define OP_MASK_MT_H            0x1
187#define OP_SH_MTACC_T           18
188#define OP_MASK_MTACC_T         0x3
189#define OP_SH_MTACC_D           13
190#define OP_MASK_MTACC_D         0x3
191
192/* MIPS MCU ASE */
193#define OP_MASK_3BITPOS         0x7
194#define OP_SH_3BITPOS           12
195#define OP_MASK_OFFSET12        0xfff
196#define OP_SH_OFFSET12          0
197
198#define OP_OP_COP0              0x10
199#define OP_OP_COP1              0x11
200#define OP_OP_COP2              0x12
201#define OP_OP_COP3              0x13
202#define OP_OP_LWC1              0x31
203#define OP_OP_LWC2              0x32
204#define OP_OP_LWC3              0x33    /* a.k.a. pref */
205#define OP_OP_LDC1              0x35
206#define OP_OP_LDC2              0x36
207#define OP_OP_LDC3              0x37    /* a.k.a. ld */
208#define OP_OP_SWC1              0x39
209#define OP_OP_SWC2              0x3a
210#define OP_OP_SWC3              0x3b
211#define OP_OP_SDC1              0x3d
212#define OP_OP_SDC2              0x3e
213#define OP_OP_SDC3              0x3f    /* a.k.a. sd */
214
215/* MIPS VIRT ASE */
216#define OP_MASK_CODE10          0x3ff
217#define OP_SH_CODE10            11
218
219/* Values in the 'VSEL' field.  */
220#define MDMX_FMTSEL_IMM_QH      0x1d
221#define MDMX_FMTSEL_IMM_OB      0x1e
222#define MDMX_FMTSEL_VEC_QH      0x15
223#define MDMX_FMTSEL_VEC_OB      0x16
224
225/* UDI */
226#define OP_SH_UDI1              6
227#define OP_MASK_UDI1            0x1f
228#define OP_SH_UDI2              6
229#define OP_MASK_UDI2            0x3ff
230#define OP_SH_UDI3              6
231#define OP_MASK_UDI3            0x7fff
232#define OP_SH_UDI4              6
233#define OP_MASK_UDI4            0xfffff
234
235/* Octeon */
236#define OP_SH_BBITIND           16
237#define OP_MASK_BBITIND         0x1f
238#define OP_SH_CINSPOS           6
239#define OP_MASK_CINSPOS         0x1f
240#define OP_SH_CINSLM1           11
241#define OP_MASK_CINSLM1         0x1f
242#define OP_SH_SEQI              6
243#define OP_MASK_SEQI            0x3ff
244
245/* Loongson */
246#define OP_SH_OFFSET_A          6
247#define OP_MASK_OFFSET_A        0xff
248#define OP_SH_OFFSET_B          3
249#define OP_MASK_OFFSET_B        0xff
250#define OP_SH_OFFSET_C          6
251#define OP_MASK_OFFSET_C        0x1ff
252#define OP_SH_RZ                0
253#define OP_MASK_RZ              0x1f
254#define OP_SH_FZ                0
255#define OP_MASK_FZ              0x1f
256
257/* Every MICROMIPSOP_X definition requires a corresponding OP_X
258   definition, and vice versa.  This simplifies various parts
259   of the operand handling in GAS.  The fields below only exist
260   in the microMIPS encoding, so define each one to have an empty
261   range.  */
262#define OP_MASK_TRAP            0
263#define OP_SH_TRAP              0
264#define OP_MASK_OFFSET10        0
265#define OP_SH_OFFSET10          0
266#define OP_MASK_RS3             0
267#define OP_SH_RS3               0
268#define OP_MASK_MB              0
269#define OP_SH_MB                0
270#define OP_MASK_MC              0
271#define OP_SH_MC                0
272#define OP_MASK_MD              0
273#define OP_SH_MD                0
274#define OP_MASK_ME              0
275#define OP_SH_ME                0
276#define OP_MASK_MF              0
277#define OP_SH_MF                0
278#define OP_MASK_MG              0
279#define OP_SH_MG                0
280#define OP_MASK_MH              0
281#define OP_SH_MH                0
282#define OP_MASK_MJ              0
283#define OP_SH_MJ                0
284#define OP_MASK_ML              0
285#define OP_SH_ML                0
286#define OP_MASK_MM              0
287#define OP_SH_MM                0
288#define OP_MASK_MN              0
289#define OP_SH_MN                0
290#define OP_MASK_MP              0
291#define OP_SH_MP                0
292#define OP_MASK_MQ              0
293#define OP_SH_MQ                0
294#define OP_MASK_IMMA            0
295#define OP_SH_IMMA              0
296#define OP_MASK_IMMB            0
297#define OP_SH_IMMB              0
298#define OP_MASK_IMMC            0
299#define OP_SH_IMMC              0
300#define OP_MASK_IMMF            0
301#define OP_SH_IMMF              0
302#define OP_MASK_IMMG            0
303#define OP_SH_IMMG              0
304#define OP_MASK_IMMH            0
305#define OP_SH_IMMH              0
306#define OP_MASK_IMMI            0
307#define OP_SH_IMMI              0
308#define OP_MASK_IMMJ            0
309#define OP_SH_IMMJ              0
310#define OP_MASK_IMML            0
311#define OP_SH_IMML              0
312#define OP_MASK_IMMM            0
313#define OP_SH_IMMM              0
314#define OP_MASK_IMMN            0
315#define OP_SH_IMMN              0
316#define OP_MASK_IMMO            0
317#define OP_SH_IMMO              0
318#define OP_MASK_IMMP            0
319#define OP_SH_IMMP              0
320#define OP_MASK_IMMQ            0
321#define OP_SH_IMMQ              0
322#define OP_MASK_IMMU            0
323#define OP_SH_IMMU              0
324#define OP_MASK_IMMW            0
325#define OP_SH_IMMW              0
326#define OP_MASK_IMMX            0
327#define OP_SH_IMMX              0
328#define OP_MASK_IMMY            0
329#define OP_SH_IMMY              0
330
331/* Enhanced VA Scheme */
332#define OP_SH_EVAOFFSET         7
333#define OP_MASK_EVAOFFSET       0x1ff
334
335/* Enumerates the various types of MIPS operand.  */
336enum mips_operand_type {
337  /* Described by mips_int_operand.  */
338  OP_INT,
339
340  /* Described by mips_mapped_int_operand.  */
341  OP_MAPPED_INT,
342
343  /* Described by mips_msb_operand.  */
344  OP_MSB,
345
346  /* Described by mips_reg_operand.  */
347  OP_REG,
348
349  /* Like OP_REG, but can be omitted if the register is the same as the
350     previous operand.  */
351  OP_OPTIONAL_REG,
352
353  /* Described by mips_reg_pair_operand.  */
354  OP_REG_PAIR,
355
356  /* Described by mips_pcrel_operand.  */
357  OP_PCREL,
358
359  /* A performance register.  The field is 5 bits in size, but the supported
360     values are much more restricted.  */
361  OP_PERF_REG,
362
363  /* The final operand in a microMIPS ADDIUSP instruction.  It mostly acts
364     as a normal 9-bit signed offset that is multiplied by four, but there
365     are four special cases:
366
367     -2 * 4 => -258 * 4
368     -1 * 4 => -257 * 4
369      0 * 4 =>  256 * 4
370      1 * 4 =>  257 * 4.  */
371  OP_ADDIUSP_INT,
372
373  /* The target of a (D)CLO or (D)CLZ instruction.  The operand spans two
374     5-bit register fields, both of which must be set to the destination
375     register.  */
376  OP_CLO_CLZ_DEST,
377
378  /* A register list for a microMIPS LWM or SWM instruction.  The operand
379     size determines whether the 16-bit or 32-bit encoding is required.  */
380  OP_LWM_SWM_LIST,
381
382  /* The register list for an emulated MIPS16 ENTRY or EXIT instruction.  */
383  OP_ENTRY_EXIT_LIST,
384
385  /* The register list and frame size for a MIPS16 SAVE or RESTORE
386     instruction.  */
387  OP_SAVE_RESTORE_LIST,
388
389  /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
390
391     V      Meaning
392     -----  -------
393     0EEE0  8 copies of $vN[E], OB format
394     0EE01  4 copies of $vN[E], QH format
395     10110  all 8 elements of $vN, OB format
396     10101  all 4 elements of $vN, QH format
397     11110  8 copies of immediate N, OB format
398     11101  4 copies of immediate N, QH format.  */
399  OP_MDMX_IMM_REG,
400
401  /* A register operand that must match the destination register.  */
402  OP_REPEAT_DEST_REG,
403
404  /* A register operand that must match the previous register.  */
405  OP_REPEAT_PREV_REG,
406
407  /* $pc, which has no encoding in the architectural instruction.  */
408  OP_PC,
409
410  /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
411     which.  */
412  OP_VU0_SUFFIX,
413
414  /* Like OP_VU0_SUFFIX, but used when the operand's value has already
415     been set.  Any suffix used here must match the previous value.  */
416  OP_VU0_MATCH_SUFFIX,
417
418  /* An index selected by an integer, e.g. [1].  */
419  OP_IMM_INDEX,
420
421  /* An index selected by a register, e.g. [$2].  */
422  OP_REG_INDEX
423};
424
425/* Enumerates the types of MIPS register.  */
426enum mips_reg_operand_type {
427  /* General registers $0-$31.  Software names like $at can also be used.  */
428  OP_REG_GP,
429
430  /* Floating-point registers $f0-$f31.  */
431  OP_REG_FP,
432
433  /* Coprocessor condition code registers $cc0-$cc7.  FPU condition codes
434     can also be written $fcc0-$fcc7.  */
435  OP_REG_CCC,
436
437  /* FPRs used in a vector capacity.  They can be written $f0-$f31
438     or $v0-$v31, although the latter form is not used for the VR5400
439     vector instructions.  */
440  OP_REG_VEC,
441
442  /* DSP accumulator registers $ac0-$ac3.  */
443  OP_REG_ACC,
444
445  /* Coprocessor registers $0-$31.  Mnemonic names like c0_cause can
446     also be used in some contexts.  */
447  OP_REG_COPRO,
448
449  /* Hardware registers $0-$31.  Mnemonic names like hwr_cpunum can
450     also be used in some contexts.  */
451  OP_REG_HW,
452
453  /* Floating-point registers $vf0-$vf31.  */
454  OP_REG_VF,
455
456  /* Integer registers $vi0-$vi31.  */
457  OP_REG_VI,
458
459  /* R5900 VU0 registers $I, $Q, $R and $ACC.  */
460  OP_REG_R5900_I,
461  OP_REG_R5900_Q,
462  OP_REG_R5900_R,
463  OP_REG_R5900_ACC,
464
465  /* MSA registers $w0-$w31.  */
466  OP_REG_MSA,
467
468  /* MSA control registers $0-$31.  */
469  OP_REG_MSA_CTRL
470};
471
472/* Base class for all operands.  */
473struct mips_operand
474{
475  /* The type of the operand.  */
476  enum mips_operand_type type;
477
478  /* The operand occupies SIZE bits of the instruction, starting at LSB.  */
479  unsigned short size;
480  unsigned short lsb;
481};
482
483/* Describes an integer operand with a regular encoding pattern.  */
484struct mips_int_operand
485{
486  struct mips_operand root;
487
488  /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
489     The cyclically previous field value encodes 1 << SHIFT less than that,
490     and so on.  E.g.
491
492     - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
493       but 15 encodes -1.
494
495     - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
496       shifted left two places.
497
498     - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
499       that 0 encodes 8.
500
501     - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3.  */
502  unsigned int max_val;
503  int bias;
504  unsigned int shift;
505
506  /* True if the operand should be printed as hex rather than decimal.  */
507  bfd_boolean print_hex;
508};
509
510/* Uses a lookup table to describe a small integer operand.  */
511struct mips_mapped_int_operand
512{
513  struct mips_operand root;
514
515  /* Maps each encoding value to the integer that it represents.  */
516  const int *int_map;
517
518  /* True if the operand should be printed as hex rather than decimal.  */
519  bfd_boolean print_hex;
520};
521
522/* An operand that encodes the most significant bit position of a bitfield.
523   Given a bitfield that spans bits [MSB, LSB], some operands of this type
524   encode MSB directly while others encode MSB - LSB.  Each operand of this
525   type is preceded by an integer operand that specifies LSB.
526
527   The assembly form varies between instructions.  For some instructions,
528   such as EXT, the operand is written as the bitfield size.  For others,
529   such as EXTS, it is written in raw MSB - LSB form.  */
530struct mips_msb_operand
531{
532  struct mips_operand root;
533
534  /* The assembly-level operand encoded by a field value of 0.  */
535  int bias;
536
537  /* True if the operand encodes MSB directly, false if it encodes
538     MSB - LSB.  */
539  bfd_boolean add_lsb;
540
541  /* The maximum value of MSB + 1.  */
542  unsigned int opsize;
543};
544
545/* Describes a single register operand.  */
546struct mips_reg_operand
547{
548  struct mips_operand root;
549
550  /* The type of register.  */
551  enum mips_reg_operand_type reg_type;
552
553  /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
554     otherwise the encoding is the same as the register number.  */
555  const unsigned char *reg_map;
556};
557
558/* Describes an operand that encodes a pair of registers.  */
559struct mips_reg_pair_operand
560{
561  struct mips_operand root;
562
563  /* The type of register.  */
564  enum mips_reg_operand_type reg_type;
565
566  /* Encoding N represents REG1_MAP[N], REG2_MAP[N].  */
567  unsigned char *reg1_map;
568  unsigned char *reg2_map;
569};
570
571/* Describes an operand that is calculated relative to a base PC.
572   The base PC is usually the address of the following instruction,
573   but the rules for MIPS16 instructions like ADDIUPC are more complicated.  */
574struct mips_pcrel_operand
575{
576  /* Encodes the offset.  */
577  struct mips_int_operand root;
578
579  /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
580     which is then added to the offset encoded by ROOT.  */
581  unsigned int align_log2 : 8;
582
583  /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
584     reinstated.  This is true for jumps and branches and false for
585     PC-relative data instructions.  */
586  unsigned int include_isa_bit : 1;
587
588  /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
589     This is true for JALX and false otherwise.  */
590  unsigned int flip_isa_bit : 1;
591};
592
593/* Return true if the assembly syntax allows OPERAND to be omitted.  */
594
595static inline bfd_boolean
596mips_optional_operand_p (const struct mips_operand *operand)
597{
598  return (operand->type == OP_OPTIONAL_REG
599          || operand->type == OP_REPEAT_PREV_REG);
600}
601
602/* Return a version of INSN in which the field specified by OPERAND
603   has value UVAL.  */
604
605static inline unsigned int
606mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
607                     unsigned int uval)
608{
609  unsigned int mask;
610
611  mask = (1 << operand->size) - 1;
612  insn &= ~(mask << operand->lsb);
613  insn |= (uval & mask) << operand->lsb;
614  return insn;
615}
616
617/* Extract OPERAND from instruction INSN.  */
618
619static inline unsigned int
620mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
621{
622  return (insn >> operand->lsb) & ((1 << operand->size) - 1);
623}
624
625/* UVAL is the value encoded by OPERAND.  Return it in signed form.  */
626
627static inline int
628mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
629{
630  unsigned int sign_bit, mask;
631
632  mask = (1 << operand->size) - 1;
633  sign_bit = 1 << (operand->size - 1);
634  return ((uval + sign_bit) & mask) - sign_bit;
635}
636
637/* Return the integer that OPERAND encodes as UVAL.  */
638
639static inline int
640mips_decode_int_operand (const struct mips_int_operand *operand,
641                         unsigned int uval)
642{
643  uval |= (operand->max_val - uval) & -(1 << operand->root.size);
644  uval += operand->bias;
645  uval <<= operand->shift;
646  return uval;
647}
648
649/* Return the maximum value that can be encoded by OPERAND.  */
650
651static inline int
652mips_int_operand_max (const struct mips_int_operand *operand)
653{
654  return (operand->max_val + operand->bias) << operand->shift;
655}
656
657/* Return the minimum value that can be encoded by OPERAND.  */
658
659static inline int
660mips_int_operand_min (const struct mips_int_operand *operand)
661{
662  unsigned int mask;
663
664  mask = (1 << operand->root.size) - 1;
665  return mips_int_operand_max (operand) - (mask << operand->shift);
666}
667
668/* Return the register that OPERAND encodes as UVAL.  */
669
670static inline int
671mips_decode_reg_operand (const struct mips_reg_operand *operand,
672                         unsigned int uval)
673{
674  if (operand->reg_map)
675    uval = operand->reg_map[uval];
676  return uval;
677}
678
679/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
680   Return the address that it encodes.  */
681
682static inline bfd_vma
683mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
684                           bfd_vma base_pc, unsigned int uval)
685{
686  bfd_vma addr;
687
688  addr = base_pc & -(1 << operand->align_log2);
689  addr += mips_decode_int_operand (&operand->root, uval);
690  if (operand->include_isa_bit)
691    addr |= base_pc & 1;
692  if (operand->flip_isa_bit)
693    addr ^= 1;
694  return addr;
695}
696
697/* This structure holds information for a particular instruction.  */
698
699struct mips_opcode
700{
701  /* The name of the instruction.  */
702  const char *name;
703  /* A string describing the arguments for this instruction.  */
704  const char *args;
705  /* The basic opcode for the instruction.  When assembling, this
706     opcode is modified by the arguments to produce the actual opcode
707     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
708  unsigned long match;
709  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
710     relevant portions of the opcode when disassembling.  If the
711     actual opcode anded with the match field equals the opcode field,
712     then we have found the correct instruction.  If pinfo is
713     INSN_MACRO, then this field is the macro identifier.  */
714  unsigned long mask;
715  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
716     of bits describing the instruction, notably any relevant hazard
717     information.  */
718  unsigned long pinfo;
719  /* A collection of additional bits describing the instruction. */
720  unsigned long pinfo2;
721  /* A collection of bits describing the instruction sets of which this
722     instruction or macro is a member. */
723  unsigned long membership;
724  /* A collection of bits describing the ASE of which this instruction
725     or macro is a member.  */
726  unsigned long ase;
727  /* A collection of bits describing the instruction sets of which this
728     instruction or macro is not a member.  */
729  unsigned long exclusions;
730};
731
732/* These are the characters which may appear in the args field of an
733   instruction.  They appear in the order in which the fields appear
734   when the instruction is used.  Commas and parentheses in the args
735   string are ignored when assembling, and written into the output
736   when disassembling.
737
738   Each of these characters corresponds to a mask field defined above.
739
740   "1" 5 bit sync type (OP_*_STYPE)
741   "<" 5 bit shift amount (OP_*_SHAMT)
742   ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
743   "a" 26 bit target address (OP_*_TARGET)
744   "+i" likewise, but flips bit 0
745   "b" 5 bit base register (OP_*_RS)
746   "c" 10 bit breakpoint code (OP_*_CODE)
747   "d" 5 bit destination register specifier (OP_*_RD)
748   "h" 5 bit prefx hint (OP_*_PREFX)
749   "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
750   "j" 16 bit signed immediate (OP_*_DELTA)
751   "k" 5 bit cache opcode in target register position (OP_*_CACHE)
752   "o" 16 bit signed offset (OP_*_DELTA)
753   "p" 16 bit PC relative branch target address (OP_*_DELTA)
754   "q" 10 bit extra breakpoint code (OP_*_CODE2)
755   "r" 5 bit same register used as both source and target (OP_*_RS)
756   "s" 5 bit source register specifier (OP_*_RS)
757   "t" 5 bit target register (OP_*_RT)
758   "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
759   "v" 5 bit same register used as both source and destination (OP_*_RS)
760   "w" 5 bit same register used as both target and destination (OP_*_RT)
761   "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
762       (used by clo and clz)
763   "C" 25 bit coprocessor function code (OP_*_COPZ)
764   "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
765   "J" 19 bit wait function code (OP_*_CODE19)
766   "x" accept and ignore register name
767   "z" must be zero register
768   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
769   "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
770        LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
771        microMIPS compatibility).
772        Enforces: 0 <= pos < 32.
773   "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
774        Requires that "+A" or "+E" occur first to set position.
775        Enforces: 0 < (pos+size) <= 32.
776   "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
777        Requires that "+A" or "+E" occur first to set position.
778        Enforces: 0 < (pos+size) <= 32.
779        (Also used by "dext" w/ different limits, but limits for
780        that are checked by the M_DEXT macro.)
781   "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
782        Enforces: 32 <= pos < 64.
783   "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
784        Requires that "+A" or "+E" occur first to set position.
785        Enforces: 32 < (pos+size) <= 64.
786   "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
787        Requires that "+A" or "+E" occur first to set position.
788        Enforces: 32 < (pos+size) <= 64.
789   "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
790        Requires that "+A" or "+E" occur first to set position.
791        Enforces: 32 < (pos+size) <= 64.
792
793   Floating point instructions:
794   "D" 5 bit destination register (OP_*_FD)
795   "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
796   "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
797   "S" 5 bit fs source 1 register (OP_*_FS)
798   "T" 5 bit ft source 2 register (OP_*_FT)
799   "R" 5 bit fr source 3 register (OP_*_FR)
800   "V" 5 bit same register used as floating source and destination (OP_*_FS)
801   "W" 5 bit same register used as floating target and destination (OP_*_FT)
802
803   Coprocessor instructions:
804   "E" 5 bit target register (OP_*_RT)
805   "G" 5 bit destination register (OP_*_RD)
806   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
807   "P" 5 bit performance-monitor register (OP_*_PERFREG)
808   "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
809   "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
810
811   Macro instructions:
812   "A" General 32 bit expression
813   "I" 32 bit immediate (value placed in imm_expr).
814   "F" 64 bit floating point constant in .rdata
815   "L" 64 bit floating point constant in .lit8
816   "f" 32 bit floating point constant
817   "l" 32 bit floating point constant in .lit4
818
819   MDMX and VR5400 instruction operands (note that while these use the
820   FP register fields, the MDMX instructions accept both $fN and $vN names
821   for the registers):
822   "O"  alignment offset (OP_*_ALN)
823   "Q"  vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
824   "X"  destination register (OP_*_FD)
825   "Y"  source register (OP_*_FS)
826   "Z"  source register (OP_*_FT)
827
828   R5900 VU0 Macromode instructions:
829   "+5" 5 bit floating point register (FD)
830   "+6" 5 bit floating point register (FS)
831   "+7" 5 bit floating point register (FT)
832   "+8" 5 bit integer register (FD)
833   "+9" 5 bit integer register (FS)
834   "+0" 5 bit integer register (FT)
835   "+K" match an existing 4-bit channel mask starting at bit 21
836   "+L" 2-bit channel index starting at bit 21
837   "+M" 2-bit channel index starting at bit 23
838   "+N" match an existing 2-bit channel index starting at bit 0
839   "+f" 15 bit immediate for VCALLMS
840   "+g" 5 bit signed immediate for VIADDI
841   "+m" $ACC register (syntax only)
842   "+q" $Q register (syntax only)
843   "+r" $R register (syntax only)
844   "+y" $I register (syntax only)
845   "#+" "++" decorator in ($reg++) sequence
846   "#-" "--" decorator in (--$reg) sequence
847
848   DSP ASE usage:
849   "2" 2 bit unsigned immediate for byte align (OP_*_BP)
850   "3" 3 bit unsigned immediate (OP_*_SA3)
851   "4" 4 bit unsigned immediate (OP_*_SA4)
852   "5" 8 bit unsigned immediate (OP_*_IMM8)
853   "6" 5 bit unsigned immediate (OP_*_RS)
854   "7" 2 bit dsp accumulator register (OP_*_DSPACC)
855   "8" 6 bit unsigned immediate (OP_*_WRDSP)
856   "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
857   "0" 6 bit signed immediate (OP_*_DSPSFT)
858   ":" 7 bit signed immediate (OP_*_DSPSFT_7)
859   "'" 6 bit unsigned immediate (OP_*_RDDSP)
860   "@" 10 bit signed immediate (OP_*_IMM10)
861
862   MT ASE usage:
863   "!" 1 bit usermode flag (OP_*_MT_U)
864   "$" 1 bit load high flag (OP_*_MT_H)
865   "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
866   "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
867   "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
868   "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
869
870   MCU ASE usage:
871   "~" 12 bit offset (OP_*_OFFSET12)
872   "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
873
874   VIRT ASE usage:
875   "+J" 10-bit hypcall code (OP_*CODE10)
876
877   UDI immediates:
878   "+1" UDI immediate bits 6-10
879   "+2" UDI immediate bits 6-15
880   "+3" UDI immediate bits 6-20
881   "+4" UDI immediate bits 6-25
882
883   Octeon:
884   "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
885   "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
886        otherwise skips to next candidate.
887   "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
888   "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
889        32 <= pos < 64, otherwise skips to next candidate.
890   "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
891   "+s" Length-minus-one field of cins32/exts32.  Requires msb position
892        of the field to be <= 31.
893   "+S" Length-minus-one field of cins/exts.  Requires msb position
894        of the field to be <= 63.
895
896   Loongson-3A:
897   "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
898   "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
899   "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
900   "+z" 5-bit rz register (OP_*_RZ)
901   "+Z" 5-bit fz register (OP_*_FZ)
902
903   Enhanced VA Scheme:
904   "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
905
906   MSA Extension:
907   "+d" 5-bit MSA register (FD)
908   "+e" 5-bit MSA register (FS)
909   "+h" 5-bit MSA register (FT)
910   "+k" 5-bit GPR at bit 6
911   "+l" 5-bit MSA control register at bit 6
912   "+n" 5-bit MSA control register at bit 11
913   "+o" 5-bit vector element index at bit 16
914   "+u" 4-bit vector element index at bit 16
915   "+v" 3-bit vector element index at bit 16
916   "+w" 2-bit vector element index at bit 16
917   "+T" (-512 .. 511) << 0 at bit 16
918   "+U" (-512 .. 511) << 1 at bit 16
919   "+V" (-512 .. 511) << 2 at bit 16
920   "+W" (-512 .. 511) << 3 at bit 16
921   "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
922   "+!" 3 bit unsigned bit position at bit 16
923   "+@" 4 bit unsigned bit position at bit 16
924   "+#" 6 bit unsigned bit position at bit 16
925   "+$" 5 bit unsigned immediate at bit 16
926   "+%" 5 bit signed immediate at bit 16
927   "+^" 10 bit signed immediate at bit 11
928   "+&" 0 vector element index
929   "+*" 5-bit register vector element index at bit 16
930   "+|" 8-bit mask at bit 16
931
932   Other:
933   "()" parens surrounding optional value
934   ","  separates operands
935   "+"  Start of extension sequence.
936
937   Characters used so far, for quick reference when adding more:
938   "1234567890"
939   "%[]<>(),+:'@!#$*&\~"
940   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
941   "abcdefghijklopqrstuvwxz"
942
943   Extension character sequences used so far ("+" followed by the
944   following), for quick reference when adding more:
945   "1234567890"
946   "~!@#$%^&*|"
947   "ABCEFGHJKLMNPQSTUVWXZ"
948   "abcdefghijklmnopqrstuvwxyz"
949*/
950
951/* These are the bits which may be set in the pinfo field of an
952   instructions, if it is not equal to INSN_MACRO.  */
953
954/* Writes to operand number N.  */
955#define INSN_WRITE_SHIFT            0
956#define INSN_WRITE_1                0x00000001
957#define INSN_WRITE_2                0x00000002
958#define INSN_WRITE_ALL              0x00000003
959/* Reads from operand number N.  */
960#define INSN_READ_SHIFT             2
961#define INSN_READ_1                 0x00000004
962#define INSN_READ_2                 0x00000008
963#define INSN_READ_3                 0x00000010
964#define INSN_READ_4                 0x00000020
965#define INSN_READ_ALL               0x0000003c
966/* Modifies general purpose register 31.  */
967#define INSN_WRITE_GPR_31           0x00000040
968/* Modifies coprocessor condition code.  */
969#define INSN_WRITE_COND_CODE        0x00000080
970/* Reads coprocessor condition code.  */
971#define INSN_READ_COND_CODE         0x00000100
972/* TLB operation.  */
973#define INSN_TLB                    0x00000200
974/* Reads coprocessor register other than floating point register.  */
975#define INSN_COP                    0x00000400
976/* Instruction loads value from memory, requiring delay.  */
977#define INSN_LOAD_MEMORY_DELAY      0x00000800
978/* Instruction loads value from coprocessor, requiring delay.  */
979#define INSN_LOAD_COPROC_DELAY      0x00001000
980/* Instruction has unconditional branch delay slot.  */
981#define INSN_UNCOND_BRANCH_DELAY    0x00002000
982/* Instruction has conditional branch delay slot.  */
983#define INSN_COND_BRANCH_DELAY      0x00004000
984/* Conditional branch likely: if branch not taken, insn nullified.  */
985#define INSN_COND_BRANCH_LIKELY     0x00008000
986/* Moves to coprocessor register, requiring delay.  */
987#define INSN_COPROC_MOVE_DELAY      0x00010000
988/* Loads coprocessor register from memory, requiring delay.  */
989#define INSN_COPROC_MEMORY_DELAY    0x00020000
990/* Reads the HI register.  */
991#define INSN_READ_HI                0x00040000
992/* Reads the LO register.  */
993#define INSN_READ_LO                0x00080000
994/* Modifies the HI register.  */
995#define INSN_WRITE_HI               0x00100000
996/* Modifies the LO register.  */
997#define INSN_WRITE_LO               0x00200000
998/* Not to be placed in a branch delay slot, either architecturally
999   or for ease of handling (such as with instructions that take a trap).  */
1000#define INSN_NO_DELAY_SLOT          0x00400000
1001/* Instruction stores value into memory.  */
1002#define INSN_STORE_MEMORY           0x00800000
1003/* Instruction uses single precision floating point.  */
1004#define FP_S                        0x01000000
1005/* Instruction uses double precision floating point.  */
1006#define FP_D                        0x02000000
1007/* Instruction is part of the tx39's integer multiply family.    */
1008#define INSN_MULT                   0x04000000
1009/* Reads general purpose register 24.  */
1010#define INSN_READ_GPR_24            0x08000000
1011/* Writes to general purpose register 24.  */
1012#define INSN_WRITE_GPR_24           0x10000000
1013/* A user-defined instruction.  */
1014#define INSN_UDI                    0x20000000
1015/* Instruction is actually a macro.  It should be ignored by the
1016   disassembler, and requires special treatment by the assembler.  */
1017#define INSN_MACRO                  0xffffffff
1018
1019/* These are the bits which may be set in the pinfo2 field of an
1020   instruction. */
1021
1022/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
1023#define INSN2_ALIAS                 0x00000001
1024/* Instruction reads MDMX accumulator. */
1025#define INSN2_READ_MDMX_ACC         0x00000002
1026/* Instruction writes MDMX accumulator. */
1027#define INSN2_WRITE_MDMX_ACC        0x00000004
1028/* Macro uses single-precision floating-point instructions.  This should
1029   only be set for macros.  For instructions, FP_S in pinfo carries the
1030   same information.  */
1031#define INSN2_M_FP_S                0x00000008
1032/* Macro uses double-precision floating-point instructions.  This should
1033   only be set for macros.  For instructions, FP_D in pinfo carries the
1034   same information.  */
1035#define INSN2_M_FP_D                0x00000010
1036/* Instruction has a branch delay slot that requires a 16-bit instruction.  */
1037#define INSN2_BRANCH_DELAY_16BIT    0x00000020
1038/* Instruction has a branch delay slot that requires a 32-bit instruction.  */
1039#define INSN2_BRANCH_DELAY_32BIT    0x00000040
1040/* Writes to the stack pointer ($29).  */
1041#define INSN2_WRITE_SP              0x00000080
1042/* Reads from the stack pointer ($29).  */
1043#define INSN2_READ_SP               0x00000100
1044/* Reads the RA ($31) register.  */
1045#define INSN2_READ_GPR_31           0x00000200
1046/* Reads the program counter ($pc).  */
1047#define INSN2_READ_PC               0x00000400
1048/* Is an unconditional branch insn. */
1049#define INSN2_UNCOND_BRANCH         0x00000800
1050/* Is a conditional branch insn. */
1051#define INSN2_COND_BRANCH           0x00001000
1052/* Reads from $16.  This is true of the MIPS16 0x6500 nop.  */
1053#define INSN2_READ_GPR_16           0x00002000
1054/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask.  */
1055#define INSN2_VU0_CHANNEL_SUFFIX    0x00004000
1056
1057/* Masks used to mark instructions to indicate which MIPS ISA level
1058   they were introduced in.  INSN_ISA_MASK masks an enumeration that
1059   specifies the base ISA level(s).  The remainder of a 32-bit
1060   word constructed using these macros is a bitmask of the remaining
1061   INSN_* values below.  */
1062
1063#define INSN_ISA_MASK             0x0000000ful
1064
1065/* We cannot start at zero due to ISA_UNKNOWN below.  */
1066#define INSN_ISA1                 1
1067#define INSN_ISA2                 2
1068#define INSN_ISA3                 3
1069#define INSN_ISA4                 4
1070#define INSN_ISA5                 5
1071#define INSN_ISA32                6
1072#define INSN_ISA32R2              7
1073#define INSN_ISA64                8
1074#define INSN_ISA64R2              9
1075/* Below this point the INSN_* values correspond to combinations of ISAs.
1076   They are only for use in the opcodes table to indicate membership of
1077   a combination of ISAs that cannot be expressed using the usual inclusion
1078   ordering on the above INSN_* values.  */
1079#define INSN_ISA3_32              10
1080#define INSN_ISA3_32R2            11
1081#define INSN_ISA4_32              12
1082#define INSN_ISA4_32R2            13
1083#define INSN_ISA5_32R2            14
1084
1085/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
1086   INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
1087   this table describes whether at least one of the ISAs described by X
1088   is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
1089   a particular core and X as the ISA level(s) at which a certain instruction
1090   is defined.)  The ISA(s) described by X is/are implemented by Y iff
1091   (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
1092   is non-zero.  */
1093static const unsigned int mips_isa_table[] =
1094  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
1095
1096/* Masks used for Chip specific instructions.  */
1097#define INSN_CHIP_MASK            0xc3ff0f20
1098
1099/* Cavium Networks Octeon instructions.  */
1100#define INSN_OCTEON               0x00000800
1101#define INSN_OCTEONP              0x00000200
1102#define INSN_OCTEON2              0x00000100
1103
1104/* MIPS R5900 instruction */
1105#define INSN_5900                 0x00004000
1106
1107/* MIPS R4650 instruction.  */
1108#define INSN_4650                 0x00010000
1109/* LSI R4010 instruction.  */
1110#define INSN_4010                 0x00020000
1111/* NEC VR4100 instruction.  */
1112#define INSN_4100                 0x00040000
1113/* Toshiba R3900 instruction.  */
1114#define INSN_3900                 0x00080000
1115/* MIPS R10000 instruction.  */
1116#define INSN_10000                0x00100000
1117/* Broadcom SB-1 instruction.  */
1118#define INSN_SB1                  0x00200000
1119/* NEC VR4111/VR4181 instruction.  */
1120#define INSN_4111                 0x00400000
1121/* NEC VR4120 instruction.  */
1122#define INSN_4120                 0x00800000
1123/* NEC VR5400 instruction.  */
1124#define INSN_5400                 0x01000000
1125/* NEC VR5500 instruction.  */
1126#define INSN_5500                 0x02000000
1127
1128/* ST Microelectronics Loongson 2E.  */
1129#define INSN_LOONGSON_2E          0x40000000
1130/* ST Microelectronics Loongson 2F.  */
1131#define INSN_LOONGSON_2F          0x80000000
1132/* Loongson 3A.  */
1133#define INSN_LOONGSON_3A          0x00000400
1134/* RMI Xlr instruction */
1135#define INSN_XLR                 0x00000020
1136
1137/* DSP ASE */
1138#define ASE_DSP                 0x00000001
1139#define ASE_DSP64               0x00000002
1140/* DSP R2 ASE  */
1141#define ASE_DSPR2               0x00000004
1142/* Enhanced VA Scheme */
1143#define ASE_EVA                 0x00000008
1144/* MCU (MicroController) ASE */
1145#define ASE_MCU                 0x00000010
1146/* MDMX ASE */
1147#define ASE_MDMX                0x00000020
1148/* MIPS-3D ASE */
1149#define ASE_MIPS3D              0x00000040
1150/* MT ASE */
1151#define ASE_MT                  0x00000080
1152/* SmartMIPS ASE  */
1153#define ASE_SMARTMIPS           0x00000100
1154/* Virtualization ASE */
1155#define ASE_VIRT                0x00000200
1156#define ASE_VIRT64              0x00000400
1157/* MSA Extension  */
1158#define ASE_MSA                 0x00000800
1159#define ASE_MSA64               0x00001000
1160
1161/* MIPS ISA defines, use instead of hardcoding ISA level.  */
1162
1163#define       ISA_UNKNOWN     0               /* Gas internal use.  */
1164#define       ISA_MIPS1       INSN_ISA1
1165#define       ISA_MIPS2       INSN_ISA2
1166#define       ISA_MIPS3       INSN_ISA3
1167#define       ISA_MIPS4       INSN_ISA4
1168#define       ISA_MIPS5       INSN_ISA5
1169
1170#define       ISA_MIPS32      INSN_ISA32
1171#define       ISA_MIPS64      INSN_ISA64
1172
1173#define       ISA_MIPS32R2    INSN_ISA32R2
1174#define       ISA_MIPS64R2    INSN_ISA64R2
1175
1176
1177/* CPU defines, use instead of hardcoding processor number. Keep this
1178   in sync with bfd/archures.c in order for machine selection to work.  */
1179#define CPU_UNKNOWN     0               /* Gas internal use.  */
1180#define CPU_R3000       3000
1181#define CPU_R3900       3900
1182#define CPU_R4000       4000
1183#define CPU_R4010       4010
1184#define CPU_VR4100      4100
1185#define CPU_R4111       4111
1186#define CPU_VR4120      4120
1187#define CPU_R4300       4300
1188#define CPU_R4400       4400
1189#define CPU_R4600       4600
1190#define CPU_R4650       4650
1191#define CPU_R5000       5000
1192#define CPU_VR5400      5400
1193#define CPU_VR5500      5500
1194#define CPU_R5900       5900
1195#define CPU_R6000       6000
1196#define CPU_RM7000      7000
1197#define CPU_R8000       8000
1198#define CPU_RM9000      9000
1199#define CPU_R10000      10000
1200#define CPU_R12000      12000
1201#define CPU_R14000      14000
1202#define CPU_R16000      16000
1203#define CPU_MIPS16      16
1204#define CPU_MIPS32      32
1205#define CPU_MIPS32R2    33
1206#define CPU_MIPS5       5
1207#define CPU_MIPS64      64
1208#define CPU_MIPS64R2    65
1209#define CPU_SB1         12310201        /* octal 'SB', 01.  */
1210#define CPU_LOONGSON_2E 3001
1211#define CPU_LOONGSON_2F 3002
1212#define CPU_LOONGSON_3A 3003
1213#define CPU_OCTEON      6501
1214#define CPU_OCTEONP     6601
1215#define CPU_OCTEON2     6502
1216#define CPU_XLR         887682          /* decimal 'XLR'   */
1217
1218/* Return true if the given CPU is included in INSN_* mask MASK.  */
1219
1220static inline bfd_boolean
1221cpu_is_member (int cpu, unsigned int mask)
1222{
1223  switch (cpu)
1224    {
1225    case CPU_R4650:
1226    case CPU_RM7000:
1227    case CPU_RM9000:
1228      return (mask & INSN_4650) != 0;
1229
1230    case CPU_R4010:
1231      return (mask & INSN_4010) != 0;
1232
1233    case CPU_VR4100:
1234      return (mask & INSN_4100) != 0;
1235
1236    case CPU_R3900:
1237      return (mask & INSN_3900) != 0;
1238
1239    case CPU_R10000:
1240    case CPU_R12000:
1241    case CPU_R14000:
1242    case CPU_R16000:
1243      return (mask & INSN_10000) != 0;
1244
1245    case CPU_SB1:
1246      return (mask & INSN_SB1) != 0;
1247
1248    case CPU_R4111:
1249      return (mask & INSN_4111) != 0;
1250
1251    case CPU_VR4120:
1252      return (mask & INSN_4120) != 0;
1253
1254    case CPU_VR5400:
1255      return (mask & INSN_5400) != 0;
1256
1257    case CPU_VR5500:
1258      return (mask & INSN_5500) != 0;
1259
1260    case CPU_R5900:
1261      return (mask & INSN_5900) != 0;
1262
1263    case CPU_LOONGSON_2E:
1264      return (mask & INSN_LOONGSON_2E) != 0;
1265
1266    case CPU_LOONGSON_2F:
1267      return (mask & INSN_LOONGSON_2F) != 0;
1268
1269    case CPU_LOONGSON_3A:
1270      return (mask & INSN_LOONGSON_3A) != 0;
1271
1272    case CPU_OCTEON:
1273      return (mask & INSN_OCTEON) != 0;
1274
1275    case CPU_OCTEONP:
1276      return (mask & INSN_OCTEONP) != 0;
1277
1278    case CPU_OCTEON2:
1279      return (mask & INSN_OCTEON2) != 0;
1280
1281    case CPU_XLR:
1282      return (mask & INSN_XLR) != 0;
1283
1284    default:
1285      return FALSE;
1286    }
1287}
1288
1289/* Test for membership in an ISA including chip specific ISAs.  INSN
1290   is pointer to an element of the opcode table; ISA is the specified
1291   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
1292   test, or zero if no CPU specific ISA test is desired.  Return true
1293   if instruction INSN is available to the given ISA and CPU. */
1294
1295static inline bfd_boolean
1296opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
1297{
1298  if (!cpu_is_member (cpu, insn->exclusions))
1299    {
1300      /* Test for ISA level compatibility.  */
1301      if ((isa & INSN_ISA_MASK) != 0
1302          && (insn->membership & INSN_ISA_MASK) != 0
1303          && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
1304               >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
1305        return TRUE;
1306
1307      /* Test for ASE compatibility.  */
1308      if ((ase & insn->ase) != 0)
1309        return TRUE;
1310
1311      /* Test for processor-specific extensions.  */
1312      if (cpu_is_member (cpu, insn->membership))
1313        return TRUE;
1314    }
1315  return FALSE;
1316}
1317
1318/* This is a list of macro expanded instructions.
1319
1320   _I appended means immediate
1321   _A appended means target address of a jump
1322   _AB appended means address with (possibly zero) base register
1323   _D appended means 64 bit floating point constant
1324   _S appended means 32 bit floating point constant.  */
1325
1326enum
1327{
1328  M_ABS,
1329  M_ACLR_AB,
1330  M_ADD_I,
1331  M_ADDU_I,
1332  M_AND_I,
1333  M_ASET_AB,
1334  M_BALIGN,
1335  M_BC1FL,
1336  M_BC1TL,
1337  M_BC2FL,
1338  M_BC2TL,
1339  M_BEQ,
1340  M_BEQ_I,
1341  M_BEQL,
1342  M_BEQL_I,
1343  M_BGE,
1344  M_BGEL,
1345  M_BGE_I,
1346  M_BGEL_I,
1347  M_BGEU,
1348  M_BGEUL,
1349  M_BGEU_I,
1350  M_BGEUL_I,
1351  M_BGEZ,
1352  M_BGEZL,
1353  M_BGEZALL,
1354  M_BGT,
1355  M_BGTL,
1356  M_BGT_I,
1357  M_BGTL_I,
1358  M_BGTU,
1359  M_BGTUL,
1360  M_BGTU_I,
1361  M_BGTUL_I,
1362  M_BGTZ,
1363  M_BGTZL,
1364  M_BLE,
1365  M_BLEL,
1366  M_BLE_I,
1367  M_BLEL_I,
1368  M_BLEU,
1369  M_BLEUL,
1370  M_BLEU_I,
1371  M_BLEUL_I,
1372  M_BLEZ,
1373  M_BLEZL,
1374  M_BLT,
1375  M_BLTL,
1376  M_BLT_I,
1377  M_BLTL_I,
1378  M_BLTU,
1379  M_BLTUL,
1380  M_BLTU_I,
1381  M_BLTUL_I,
1382  M_BLTZ,
1383  M_BLTZL,
1384  M_BLTZALL,
1385  M_BNE,
1386  M_BNEL,
1387  M_BNE_I,
1388  M_BNEL_I,
1389  M_CACHE_AB,
1390  M_CACHEE_AB,
1391  M_DABS,
1392  M_DADD_I,
1393  M_DADDU_I,
1394  M_DDIV_3,
1395  M_DDIV_3I,
1396  M_DDIVU_3,
1397  M_DDIVU_3I,
1398  M_DIV_3,
1399  M_DIV_3I,
1400  M_DIVU_3,
1401  M_DIVU_3I,
1402  M_DLA_AB,
1403  M_DLCA_AB,
1404  M_DLI,
1405  M_DMUL,
1406  M_DMUL_I,
1407  M_DMULO,
1408  M_DMULO_I,
1409  M_DMULOU,
1410  M_DMULOU_I,
1411  M_DREM_3,
1412  M_DREM_3I,
1413  M_DREMU_3,
1414  M_DREMU_3I,
1415  M_DSUB_I,
1416  M_DSUBU_I,
1417  M_DSUBU_I_2,
1418  M_J_A,
1419  M_JAL_1,
1420  M_JAL_2,
1421  M_JAL_A,
1422  M_JALS_1,
1423  M_JALS_2,
1424  M_JALS_A,
1425  M_JRADDIUSP,
1426  M_JRC,
1427  M_L_DAB,
1428  M_LA_AB,
1429  M_LB_AB,
1430  M_LBE_AB,
1431  M_LBU_AB,
1432  M_LBUE_AB,
1433  M_LCA_AB,
1434  M_LD_AB,
1435  M_LDC1_AB,
1436  M_LDC2_AB,
1437  M_LQC2_AB,
1438  M_LDC3_AB,
1439  M_LDL_AB,
1440  M_LDM_AB,
1441  M_LDP_AB,
1442  M_LDR_AB,
1443  M_LH_AB,
1444  M_LHE_AB,
1445  M_LHU_AB,
1446  M_LHUE_AB,
1447  M_LI,
1448  M_LI_D,
1449  M_LI_DD,
1450  M_LI_S,
1451  M_LI_SS,
1452  M_LL_AB,
1453  M_LLD_AB,
1454  M_LLE_AB,
1455  M_LQ_AB,
1456  M_LW_AB,
1457  M_LWE_AB,
1458  M_LWC0_AB,
1459  M_LWC1_AB,
1460  M_LWC2_AB,
1461  M_LWC3_AB,
1462  M_LWL_AB,
1463  M_LWLE_AB,
1464  M_LWM_AB,
1465  M_LWP_AB,
1466  M_LWR_AB,
1467  M_LWRE_AB,
1468  M_LWU_AB,
1469  M_MSGSND,
1470  M_MSGLD,
1471  M_MSGLD_T,
1472  M_MSGWAIT,
1473  M_MSGWAIT_T,
1474  M_MOVE,
1475  M_MOVEP,
1476  M_MUL,
1477  M_MUL_I,
1478  M_MULO,
1479  M_MULO_I,
1480  M_MULOU,
1481  M_MULOU_I,
1482  M_NOR_I,
1483  M_OR_I,
1484  M_PREF_AB,
1485  M_PREFE_AB,
1486  M_REM_3,
1487  M_REM_3I,
1488  M_REMU_3,
1489  M_REMU_3I,
1490  M_DROL,
1491  M_ROL,
1492  M_DROL_I,
1493  M_ROL_I,
1494  M_DROR,
1495  M_ROR,
1496  M_DROR_I,
1497  M_ROR_I,
1498  M_S_DA,
1499  M_S_DAB,
1500  M_S_S,
1501  M_SAA_AB,
1502  M_SAAD_AB,
1503  M_SC_AB,
1504  M_SCD_AB,
1505  M_SCE_AB,
1506  M_SD_AB,
1507  M_SDC1_AB,
1508  M_SDC2_AB,
1509  M_SQC2_AB,
1510  M_SDC3_AB,
1511  M_SDL_AB,
1512  M_SDM_AB,
1513  M_SDP_AB,
1514  M_SDR_AB,
1515  M_SEQ,
1516  M_SEQ_I,
1517  M_SGE,
1518  M_SGE_I,
1519  M_SGEU,
1520  M_SGEU_I,
1521  M_SGT,
1522  M_SGT_I,
1523  M_SGTU,
1524  M_SGTU_I,
1525  M_SLE,
1526  M_SLE_I,
1527  M_SLEU,
1528  M_SLEU_I,
1529  M_SLT_I,
1530  M_SLTU_I,
1531  M_SNE,
1532  M_SNE_I,
1533  M_SB_AB,
1534  M_SBE_AB,
1535  M_SH_AB,
1536  M_SHE_AB,
1537  M_SQ_AB,
1538  M_SW_AB,
1539  M_SWE_AB,
1540  M_SWC0_AB,
1541  M_SWC1_AB,
1542  M_SWC2_AB,
1543  M_SWC3_AB,
1544  M_SWL_AB,
1545  M_SWLE_AB,
1546  M_SWM_AB,
1547  M_SWP_AB,
1548  M_SWR_AB,
1549  M_SWRE_AB,
1550  M_SUB_I,
1551  M_SUBU_I,
1552  M_SUBU_I_2,
1553  M_TEQ_I,
1554  M_TGE_I,
1555  M_TGEU_I,
1556  M_TLT_I,
1557  M_TLTU_I,
1558  M_TNE_I,
1559  M_TRUNCWD,
1560  M_TRUNCWS,
1561  M_ULD_AB,
1562  M_ULH_AB,
1563  M_ULHU_AB,
1564  M_ULW_AB,
1565  M_USH_AB,
1566  M_USW_AB,
1567  M_USD_AB,
1568  M_XOR_I,
1569  M_COP0,
1570  M_COP1,
1571  M_COP2,
1572  M_COP3,
1573  M_NUM_MACROS
1574};
1575
1576
1577/* The order of overloaded instructions matters.  Label arguments and
1578   register arguments look the same. Instructions that can have either
1579   for arguments must apear in the correct order in this table for the
1580   assembler to pick the right one. In other words, entries with
1581   immediate operands must apear after the same instruction with
1582   registers.
1583
1584   Many instructions are short hand for other instructions (i.e., The
1585   jal <register> instruction is short for jalr <register>).  */
1586
1587extern const struct mips_operand mips_vu0_channel_mask;
1588extern const struct mips_operand *decode_mips_operand (const char *);
1589extern const struct mips_opcode mips_builtin_opcodes[];
1590extern const int bfd_mips_num_builtin_opcodes;
1591extern struct mips_opcode *mips_opcodes;
1592extern int bfd_mips_num_opcodes;
1593#define NUMOPCODES bfd_mips_num_opcodes
1594
1595
1596/* The rest of this file adds definitions for the mips16 TinyRISC
1597   processor.  */
1598
1599/* These are the bitmasks and shift counts used for the different
1600   fields in the instruction formats.  Other than OP, no masks are
1601   provided for the fixed portions of an instruction, since they are
1602   not needed.
1603
1604   The I format uses IMM11.
1605
1606   The RI format uses RX and IMM8.
1607
1608   The RR format uses RX, and RY.
1609
1610   The RRI format uses RX, RY, and IMM5.
1611
1612   The RRR format uses RX, RY, and RZ.
1613
1614   The RRI_A format uses RX, RY, and IMM4.
1615
1616   The SHIFT format uses RX, RY, and SHAMT.
1617
1618   The I8 format uses IMM8.
1619
1620   The I8_MOVR32 format uses RY and REGR32.
1621
1622   The IR_MOV32R format uses REG32R and MOV32Z.
1623
1624   The I64 format uses IMM8.
1625
1626   The RI64 format uses RY and IMM5.
1627   */
1628
1629#define MIPS16OP_MASK_OP        0x1f
1630#define MIPS16OP_SH_OP          11
1631#define MIPS16OP_MASK_IMM11     0x7ff
1632#define MIPS16OP_SH_IMM11       0
1633#define MIPS16OP_MASK_RX        0x7
1634#define MIPS16OP_SH_RX          8
1635#define MIPS16OP_MASK_IMM8      0xff
1636#define MIPS16OP_SH_IMM8        0
1637#define MIPS16OP_MASK_RY        0x7
1638#define MIPS16OP_SH_RY          5
1639#define MIPS16OP_MASK_IMM5      0x1f
1640#define MIPS16OP_SH_IMM5        0
1641#define MIPS16OP_MASK_RZ        0x7
1642#define MIPS16OP_SH_RZ          2
1643#define MIPS16OP_MASK_IMM4      0xf
1644#define MIPS16OP_SH_IMM4        0
1645#define MIPS16OP_MASK_REGR32    0x1f
1646#define MIPS16OP_SH_REGR32      0
1647#define MIPS16OP_MASK_REG32R    0x1f
1648#define MIPS16OP_SH_REG32R      3
1649#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1650#define MIPS16OP_MASK_MOVE32Z   0x7
1651#define MIPS16OP_SH_MOVE32Z     0
1652#define MIPS16OP_MASK_IMM6      0x3f
1653#define MIPS16OP_SH_IMM6        5
1654
1655/* These are the characters which may appears in the args field of a MIPS16
1656   instruction.  They appear in the order in which the fields appear when the
1657   instruction is used.  Commas and parentheses in the args string are ignored
1658   when assembling, and written into the output when disassembling.
1659
1660   "y" 3 bit register (MIPS16OP_*_RY)
1661   "x" 3 bit register (MIPS16OP_*_RX)
1662   "z" 3 bit register (MIPS16OP_*_RZ)
1663   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1664   "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1665   "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1666   "0" zero register ($0)
1667   "S" stack pointer ($sp or $29)
1668   "P" program counter
1669   "R" return address register ($ra or $31)
1670   "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1671   "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1672   "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1673   "a" 26 bit jump address
1674   "i" likewise, but flips bit 0
1675   "e" 11 bit extension value
1676   "l" register list for entry instruction
1677   "L" register list for exit instruction
1678
1679   "I" an immediate value used for macros
1680
1681   The remaining codes may be extended.  Except as otherwise noted,
1682   the full extended operand is a 16 bit signed value.
1683   "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1684   ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1685   "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1686   "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1687   "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1688   "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1689   "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1690   "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1691   "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1692   "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1693   "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1694   "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1695   "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1696   "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1697   "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1698   "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1699   "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1700   "q" 11 bit branch address (MIPS16OP_*_IMM11)
1701   "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1702   "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1703   "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1704   "m" 7 bit register list for save instruction (18 bit extended)
1705   "M" 7 bit register list for restore instruction (18 bit extended)
1706  */
1707
1708/* Save/restore encoding for the args field when all 4 registers are
1709   either saved as arguments or saved/restored as statics.  */
1710#define MIPS16_ALL_ARGS    0xe
1711#define MIPS16_ALL_STATICS 0xb
1712
1713/* The following flags have the same value for the mips16 opcode
1714   table:
1715
1716   INSN_ISA3
1717
1718   INSN_UNCOND_BRANCH_DELAY
1719   INSN_COND_BRANCH_DELAY
1720   INSN_COND_BRANCH_LIKELY (never used)
1721   INSN_READ_HI
1722   INSN_READ_LO
1723   INSN_WRITE_HI
1724   INSN_WRITE_LO
1725   INSN_TRAP
1726   FP_D (never used)
1727   */
1728
1729extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
1730extern const struct mips_opcode mips16_opcodes[];
1731extern const int bfd_mips16_num_opcodes;
1732
1733/* These are the bit masks and shift counts used for the different fields
1734   in the microMIPS instruction formats.  No masks are provided for the
1735   fixed portions of an instruction, since they are not needed.  */
1736
1737#define MICROMIPSOP_MASK_IMMEDIATE      0xffff
1738#define MICROMIPSOP_SH_IMMEDIATE        0
1739#define MICROMIPSOP_MASK_DELTA          0xffff
1740#define MICROMIPSOP_SH_DELTA            0
1741#define MICROMIPSOP_MASK_CODE10         0x3ff
1742#define MICROMIPSOP_SH_CODE10           16      /* 10-bit wait code.  */
1743#define MICROMIPSOP_MASK_TRAP           0xf
1744#define MICROMIPSOP_SH_TRAP             12      /* 4-bit trap code.  */
1745#define MICROMIPSOP_MASK_SHAMT          0x1f
1746#define MICROMIPSOP_SH_SHAMT            11
1747#define MICROMIPSOP_MASK_TARGET         0x3ffffff
1748#define MICROMIPSOP_SH_TARGET           0
1749#define MICROMIPSOP_MASK_EXTLSB         0x1f    /* "ext" LSB.  */
1750#define MICROMIPSOP_SH_EXTLSB           6
1751#define MICROMIPSOP_MASK_EXTMSBD        0x1f    /* "ext" MSBD.  */
1752#define MICROMIPSOP_SH_EXTMSBD          11
1753#define MICROMIPSOP_MASK_INSMSB         0x1f    /* "ins" MSB.  */
1754#define MICROMIPSOP_SH_INSMSB           11
1755#define MICROMIPSOP_MASK_CODE           0x3ff
1756#define MICROMIPSOP_SH_CODE             16      /* 10-bit higher break code. */
1757#define MICROMIPSOP_MASK_CODE2          0x3ff
1758#define MICROMIPSOP_SH_CODE2            6       /* 10-bit lower break code.  */
1759#define MICROMIPSOP_MASK_CACHE          0x1f
1760#define MICROMIPSOP_SH_CACHE            21      /* 5-bit cache op.  */
1761#define MICROMIPSOP_MASK_SEL            0x7
1762#define MICROMIPSOP_SH_SEL              11
1763#define MICROMIPSOP_MASK_OFFSET12       0xfff
1764#define MICROMIPSOP_SH_OFFSET12         0
1765#define MICROMIPSOP_MASK_3BITPOS        0x7
1766#define MICROMIPSOP_SH_3BITPOS          21
1767#define MICROMIPSOP_MASK_STYPE          0x1f
1768#define MICROMIPSOP_SH_STYPE            16
1769#define MICROMIPSOP_MASK_OFFSET10       0x3ff
1770#define MICROMIPSOP_SH_OFFSET10         6
1771#define MICROMIPSOP_MASK_RS             0x1f
1772#define MICROMIPSOP_SH_RS               16
1773#define MICROMIPSOP_MASK_RT             0x1f
1774#define MICROMIPSOP_SH_RT               21
1775#define MICROMIPSOP_MASK_RD             0x1f
1776#define MICROMIPSOP_SH_RD               11
1777#define MICROMIPSOP_MASK_FS             0x1f
1778#define MICROMIPSOP_SH_FS               16
1779#define MICROMIPSOP_MASK_FT             0x1f
1780#define MICROMIPSOP_SH_FT               21
1781#define MICROMIPSOP_MASK_FD             0x1f
1782#define MICROMIPSOP_SH_FD               11
1783#define MICROMIPSOP_MASK_FR             0x1f
1784#define MICROMIPSOP_SH_FR               6
1785#define MICROMIPSOP_MASK_RS3            0x1f
1786#define MICROMIPSOP_SH_RS3              6
1787#define MICROMIPSOP_MASK_PREFX          0x1f
1788#define MICROMIPSOP_SH_PREFX            11
1789#define MICROMIPSOP_MASK_BCC            0x7
1790#define MICROMIPSOP_SH_BCC              18
1791#define MICROMIPSOP_MASK_CCC            0x7
1792#define MICROMIPSOP_SH_CCC              13
1793#define MICROMIPSOP_MASK_COPZ           0x7fffff
1794#define MICROMIPSOP_SH_COPZ             3
1795
1796#define MICROMIPSOP_MASK_MB             0x7
1797#define MICROMIPSOP_SH_MB               23
1798#define MICROMIPSOP_MASK_MC             0x7
1799#define MICROMIPSOP_SH_MC               4
1800#define MICROMIPSOP_MASK_MD             0x7
1801#define MICROMIPSOP_SH_MD               7
1802#define MICROMIPSOP_MASK_ME             0x7
1803#define MICROMIPSOP_SH_ME               1
1804#define MICROMIPSOP_MASK_MF             0x7
1805#define MICROMIPSOP_SH_MF               3
1806#define MICROMIPSOP_MASK_MG             0x7
1807#define MICROMIPSOP_SH_MG               0
1808#define MICROMIPSOP_MASK_MH             0x7
1809#define MICROMIPSOP_SH_MH               7
1810#define MICROMIPSOP_MASK_MJ             0x1f
1811#define MICROMIPSOP_SH_MJ               0
1812#define MICROMIPSOP_MASK_ML             0x7
1813#define MICROMIPSOP_SH_ML               4
1814#define MICROMIPSOP_MASK_MM             0x7
1815#define MICROMIPSOP_SH_MM               1
1816#define MICROMIPSOP_MASK_MN             0x7
1817#define MICROMIPSOP_SH_MN               4
1818#define MICROMIPSOP_MASK_MP             0x1f
1819#define MICROMIPSOP_SH_MP               5
1820#define MICROMIPSOP_MASK_MQ             0x7
1821#define MICROMIPSOP_SH_MQ               7
1822
1823#define MICROMIPSOP_MASK_IMMA           0x7f
1824#define MICROMIPSOP_SH_IMMA             0
1825#define MICROMIPSOP_MASK_IMMB           0x7
1826#define MICROMIPSOP_SH_IMMB             1
1827#define MICROMIPSOP_MASK_IMMC           0xf
1828#define MICROMIPSOP_SH_IMMC             0
1829#define MICROMIPSOP_MASK_IMMD           0x3ff
1830#define MICROMIPSOP_SH_IMMD             0
1831#define MICROMIPSOP_MASK_IMME           0x7f
1832#define MICROMIPSOP_SH_IMME             0
1833#define MICROMIPSOP_MASK_IMMF           0xf
1834#define MICROMIPSOP_SH_IMMF             0
1835#define MICROMIPSOP_MASK_IMMG           0xf
1836#define MICROMIPSOP_SH_IMMG             0
1837#define MICROMIPSOP_MASK_IMMH           0xf
1838#define MICROMIPSOP_SH_IMMH             0
1839#define MICROMIPSOP_MASK_IMMI           0x7f
1840#define MICROMIPSOP_SH_IMMI             0
1841#define MICROMIPSOP_MASK_IMMJ           0xf
1842#define MICROMIPSOP_SH_IMMJ             0
1843#define MICROMIPSOP_MASK_IMML           0xf
1844#define MICROMIPSOP_SH_IMML             0
1845#define MICROMIPSOP_MASK_IMMM           0x7
1846#define MICROMIPSOP_SH_IMMM             1
1847#define MICROMIPSOP_MASK_IMMN           0x3
1848#define MICROMIPSOP_SH_IMMN             4
1849#define MICROMIPSOP_MASK_IMMO           0xf
1850#define MICROMIPSOP_SH_IMMO             0
1851#define MICROMIPSOP_MASK_IMMP           0x1f
1852#define MICROMIPSOP_SH_IMMP             0
1853#define MICROMIPSOP_MASK_IMMQ           0x7fffff
1854#define MICROMIPSOP_SH_IMMQ             0
1855#define MICROMIPSOP_MASK_IMMU           0x1f
1856#define MICROMIPSOP_SH_IMMU             0
1857#define MICROMIPSOP_MASK_IMMW           0x3f
1858#define MICROMIPSOP_SH_IMMW             1
1859#define MICROMIPSOP_MASK_IMMX           0xf
1860#define MICROMIPSOP_SH_IMMX             1
1861#define MICROMIPSOP_MASK_IMMY           0x1ff
1862#define MICROMIPSOP_SH_IMMY             1
1863
1864/* MIPS DSP ASE */
1865#define MICROMIPSOP_MASK_DSPACC         0x3
1866#define MICROMIPSOP_SH_DSPACC           14
1867#define MICROMIPSOP_MASK_DSPSFT         0x3f
1868#define MICROMIPSOP_SH_DSPSFT           16
1869#define MICROMIPSOP_MASK_SA3            0x7
1870#define MICROMIPSOP_SH_SA3              13
1871#define MICROMIPSOP_MASK_SA4            0xf
1872#define MICROMIPSOP_SH_SA4              12
1873#define MICROMIPSOP_MASK_IMM8           0xff
1874#define MICROMIPSOP_SH_IMM8             13
1875#define MICROMIPSOP_MASK_IMM10          0x3ff
1876#define MICROMIPSOP_SH_IMM10            16
1877#define MICROMIPSOP_MASK_WRDSP          0x3f
1878#define MICROMIPSOP_SH_WRDSP            14
1879#define MICROMIPSOP_MASK_BP             0x3
1880#define MICROMIPSOP_SH_BP               14
1881
1882/* Placeholders for fields that only exist in the traditional 32-bit
1883   instruction encoding; see the comment above for details.  */
1884#define MICROMIPSOP_MASK_CODE20         0
1885#define MICROMIPSOP_SH_CODE20           0
1886#define MICROMIPSOP_MASK_PERFREG        0
1887#define MICROMIPSOP_SH_PERFREG          0
1888#define MICROMIPSOP_MASK_CODE19         0
1889#define MICROMIPSOP_SH_CODE19           0
1890#define MICROMIPSOP_MASK_ALN            0
1891#define MICROMIPSOP_SH_ALN              0
1892#define MICROMIPSOP_MASK_VECBYTE        0
1893#define MICROMIPSOP_SH_VECBYTE          0
1894#define MICROMIPSOP_MASK_VECALIGN       0
1895#define MICROMIPSOP_SH_VECALIGN         0
1896#define MICROMIPSOP_MASK_DSPACC_S       0
1897#define MICROMIPSOP_SH_DSPACC_S         0
1898#define MICROMIPSOP_MASK_DSPSFT_7       0
1899#define MICROMIPSOP_SH_DSPSFT_7         0
1900#define MICROMIPSOP_MASK_RDDSP          0
1901#define MICROMIPSOP_SH_RDDSP            0
1902#define MICROMIPSOP_MASK_MT_U           0
1903#define MICROMIPSOP_SH_MT_U             0
1904#define MICROMIPSOP_MASK_MT_H           0
1905#define MICROMIPSOP_SH_MT_H             0
1906#define MICROMIPSOP_MASK_MTACC_T        0
1907#define MICROMIPSOP_SH_MTACC_T          0
1908#define MICROMIPSOP_MASK_MTACC_D        0
1909#define MICROMIPSOP_SH_MTACC_D          0
1910#define MICROMIPSOP_MASK_BBITIND        0
1911#define MICROMIPSOP_SH_BBITIND          0
1912#define MICROMIPSOP_MASK_CINSPOS        0
1913#define MICROMIPSOP_SH_CINSPOS          0
1914#define MICROMIPSOP_MASK_CINSLM1        0
1915#define MICROMIPSOP_SH_CINSLM1          0
1916#define MICROMIPSOP_MASK_SEQI           0
1917#define MICROMIPSOP_SH_SEQI             0
1918#define MICROMIPSOP_SH_OFFSET_A         0
1919#define MICROMIPSOP_MASK_OFFSET_A       0
1920#define MICROMIPSOP_SH_OFFSET_B         0
1921#define MICROMIPSOP_MASK_OFFSET_B       0
1922#define MICROMIPSOP_SH_OFFSET_C         0
1923#define MICROMIPSOP_MASK_OFFSET_C       0
1924#define MICROMIPSOP_SH_RZ               0
1925#define MICROMIPSOP_MASK_RZ             0
1926#define MICROMIPSOP_SH_FZ               0
1927#define MICROMIPSOP_MASK_FZ             0
1928
1929/* microMIPS Enhanced VA Scheme */
1930#define MICROMIPSOP_SH_EVAOFFSET        0
1931#define MICROMIPSOP_MASK_EVAOFFSET      0x1ff
1932
1933/* These are the characters which may appears in the args field of a microMIPS
1934   instruction.  They appear in the order in which the fields appear
1935   when the instruction is used.  Commas and parentheses in the args
1936   string are ignored when assembling, and written into the output
1937   when disassembling.
1938
1939   The followings are for 16-bit microMIPS instructions.
1940
1941   "ma" must be $28
1942   "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1943        The same register used as both source and target.
1944   "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1945   "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1946        The same register used as both source and target.
1947   "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1948   "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1949   "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1950   "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1951   "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1952   "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1953   "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1954   "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1955   "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1956   "mr" must be program counter
1957   "ms" must be $29
1958   "mt" must be the same as the previous register
1959   "mx" must be the same as the destination register
1960   "my" must be $31
1961   "mz" must be $0
1962
1963   "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1964   "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1965   "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1966        32768, 65535) (MICROMIPSOP_*_IMMC)
1967   "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1968   "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1969   "mF" 4-bit immediate (0 .. 15)  (MICROMIPSOP_*_IMMF)
1970   "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1971   "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1972   "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1973   "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1974   "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1975   "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1976   "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1977   "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1978   "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1979   "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1980   "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1981   "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1982   "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1983   "mZ" must be zero
1984
1985   In most cases 32-bit microMIPS instructions use the same characters
1986   as MIPS (with ADDIUPC being a notable exception, but there are some
1987   others too).
1988
1989   "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1990   "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
1991   "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1992   ">" shift amount between 32 and 63, stored after subtracting 32
1993       (MICROMIPSOP_*_SHAMT)
1994   "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1995   "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1996   "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1997   "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1998   "+i" likewise, but flips bit 0
1999   "b" 5-bit base register (MICROMIPSOP_*_RS)
2000   "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
2001   "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
2002   "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
2003   "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
2004   "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
2005   "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
2006   "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
2007   "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
2008   "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
2009   "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
2010   "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
2011   "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
2012   "t" 5-bit target register (MICROMIPSOP_*_RT)
2013   "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
2014   "v" 5-bit same register used as both source and destination
2015       (MICROMIPSOP_*_RS)
2016   "w" 5-bit same register used as both target and destination
2017       (MICROMIPSOP_*_RT)
2018   "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
2019   "z" must be zero register
2020   "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
2021   "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
2022   "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
2023
2024   "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
2025        LSB (MICROMIPSOP_*_EXTLSB).
2026        Enforces: 0 <= pos < 32.
2027   "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
2028        Requires that "+A" or "+E" occur first to set position.
2029        Enforces: 0 < (pos+size) <= 32.
2030   "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
2031        Requires that "+A" or "+E" occur first to set position.
2032        Enforces: 0 < (pos+size) <= 32.
2033        (Also used by DEXT w/ different limits, but limits for
2034        that are checked by the M_DEXT macro.)
2035   "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
2036        Enforces: 32 <= pos < 64.
2037   "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
2038        Requires that "+A" or "+E" occur first to set position.
2039        Enforces: 32 < (pos+size) <= 64.
2040   "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
2041        Requires that "+A" or "+E" occur first to set position.
2042        Enforces: 32 < (pos+size) <= 64.
2043   "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
2044        Requires that "+A" or "+E" occur first to set position.
2045        Enforces: 32 < (pos+size) <= 64.
2046
2047   PC-relative addition (ADDIUPC) instruction:
2048   "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
2049   "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
2050
2051   Floating point instructions:
2052   "D" 5-bit destination register (MICROMIPSOP_*_FD)
2053   "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
2054   "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
2055   "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
2056   "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
2057   "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
2058   "V" 5-bit same register used as floating source and destination or target
2059       (MICROMIPSOP_*_FS)
2060
2061   Coprocessor instructions:
2062   "E" 5-bit target register (MICROMIPSOP_*_RT)
2063   "G" 5-bit source register (MICROMIPSOP_*_RS)
2064   "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
2065
2066   Macro instructions:
2067   "A" general 32 bit expression
2068   "I" 32-bit immediate (value placed in imm_expr).
2069   "F" 64-bit floating point constant in .rdata
2070   "L" 64-bit floating point constant in .lit8
2071   "f" 32-bit floating point constant
2072   "l" 32-bit floating point constant in .lit4
2073
2074   DSP ASE usage:
2075   "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
2076   "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
2077   "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
2078   "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
2079   "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
2080   "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
2081   "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
2082   "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
2083   "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
2084   "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
2085
2086   microMIPS Enhanced VA Scheme:
2087   "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
2088
2089   MSA Extension:
2090   "+d" 5-bit MSA register (FD)
2091   "+e" 5-bit MSA register (FS)
2092   "+h" 5-bit MSA register (FT)
2093   "+k" 5-bit GPR at bit 6
2094   "+l" 5-bit MSA control register at bit 6
2095   "+n" 5-bit MSA control register at bit 11
2096   "+o" 5-bit vector element index at bit 16
2097   "+u" 4-bit vector element index at bit 16
2098   "+v" 3-bit vector element index at bit 16
2099   "+w" 2-bit vector element index at bit 16
2100   "+x" 5-bit shift amount at bit 16
2101   "+T" (-512 .. 511) << 0 at bit 16
2102   "+U" (-512 .. 511) << 1 at bit 16
2103   "+V" (-512 .. 511) << 2 at bit 16
2104   "+W" (-512 .. 511) << 3 at bit 16
2105   "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
2106   "+!" 3 bit unsigned bit position at bit 16
2107   "+@" 4 bit unsigned bit position at bit 16
2108   "+#" 6 bit unsigned bit position at bit 16
2109   "+$" 5 bit unsigned immediate at bit 16
2110   "+%" 5 bit signed immediate at bit 16
2111   "+^" 10 bit signed immediate at bit 11
2112   "+&" 0 vector element index
2113   "+*" 5-bit register vector element index at bit 16
2114   "+|" 8-bit mask at bit 16
2115
2116   Other:
2117   "()" parens surrounding optional value
2118   ","  separates operands
2119   "+"  start of extension sequence
2120   "m"  start of microMIPS extension sequence
2121
2122   Characters used so far, for quick reference when adding more:
2123   "12345678 0"
2124   "<>(),+.@\^|~"
2125   "ABCDEFGHI KLMN   RST V    "
2126   "abcd f hijklmnopqrstuvw yz"
2127
2128   Extension character sequences used so far ("+" followed by the
2129   following), for quick reference when adding more:
2130   ""
2131   "~!@#$%^&*|"
2132   "ABCEFGHTUVW"
2133   "dehijklnouvwx"
2134
2135   Extension character sequences used so far ("m" followed by the
2136   following), for quick reference when adding more:
2137   ""
2138   ""
2139   " BCDEFGHIJ LMNOPQ   U WXYZ"
2140   " bcdefghij lmn pq st   xyz"
2141*/
2142
2143extern const struct mips_operand *decode_micromips_operand (const char *);
2144extern const struct mips_opcode micromips_opcodes[];
2145extern const int bfd_micromips_num_opcodes;
2146
2147/* A NOP insn impemented as "or at,at,zero".
2148   Used to implement -mfix-loongson2f.  */
2149#define LOONGSON2F_NOP_INSN     0x00200825
2150
2151#endif /* _MIPS_H_ */
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