| 1 | /* Nios II opcode list for GAS, the GNU assembler. |
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| 2 | Copyright (C) 2012, 2013 Free Software Foundation, Inc. |
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| 3 | Contributed by Nigel Gray (ngray@altera.com). |
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| 4 | Contributed by Mentor Graphics, Inc. |
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| 5 | |
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| 6 | This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
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| 7 | |
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| 8 | GAS/GDB is free software; you can redistribute it and/or modify |
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| 9 | it under the terms of the GNU General Public License as published by |
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| 10 | the Free Software Foundation; either version 3, or (at your option) |
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| 11 | any later version. |
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| 12 | |
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| 13 | GAS/GDB is distributed in the hope that it will be useful, |
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| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 16 | GNU General Public License for more details. |
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| 17 | |
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| 18 | You should have received a copy of the GNU General Public License |
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| 19 | along with GAS or GDB; see the file COPYING3. If not, write to |
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| 20 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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| 21 | Boston, MA 02110-1301, USA. */ |
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| 22 | |
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| 23 | #ifndef _NIOS2_H_ |
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| 24 | #define _NIOS2_H_ |
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| 25 | |
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| 26 | #include "bfd.h" |
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| 27 | |
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| 28 | /**************************************************************************** |
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| 29 | * This file contains structures, bit masks and shift counts used |
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| 30 | * by the GNU toolchain to define the Nios II instruction set and |
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| 31 | * access various opcode fields. |
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| 32 | ****************************************************************************/ |
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| 33 | |
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| 34 | /* Identify different overflow situations for error messages. */ |
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| 35 | enum overflow_type |
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| 36 | { |
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| 37 | call_target_overflow = 0, |
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| 38 | branch_target_overflow, |
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| 39 | address_offset_overflow, |
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| 40 | signed_immed16_overflow, |
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| 41 | unsigned_immed16_overflow, |
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| 42 | unsigned_immed5_overflow, |
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| 43 | custom_opcode_overflow, |
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| 44 | no_overflow |
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| 45 | }; |
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| 46 | |
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| 47 | /* This structure holds information for a particular instruction. |
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| 48 | |
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| 49 | The args field is a string describing the operands. The following |
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| 50 | letters can appear in the args: |
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| 51 | c - a 5-bit control register index |
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| 52 | d - a 5-bit destination register index |
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| 53 | s - a 5-bit left source register index |
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| 54 | t - a 5-bit right source register index |
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| 55 | i - a 16-bit signed immediate |
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| 56 | u - a 16-bit unsigned immediate |
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| 57 | o - a 16-bit signed program counter relative offset |
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| 58 | j - a 5-bit unsigned immediate |
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| 59 | b - a 5-bit break instruction constant |
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| 60 | l - a 8-bit custom instruction constant |
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| 61 | m - a 26-bit unsigned immediate |
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| 62 | Literal ',', '(', and ')' characters may also appear in the args as |
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| 63 | delimiters. |
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| 64 | |
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| 65 | The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection |
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| 66 | of bits describing the instruction, notably any relevant hazard |
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| 67 | information. |
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| 68 | |
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| 69 | When assembling, the match field contains the opcode template, which |
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| 70 | is modified by the arguments to produce the actual opcode |
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| 71 | that is emitted. If pinfo is INSN_MACRO, then this is 0. |
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| 72 | |
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| 73 | If pinfo is INSN_MACRO, the mask field stores the macro identifier. |
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| 74 | Otherwise this is a bit mask for the relevant portions of the opcode |
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| 75 | when disassembling. If the actual opcode anded with the match field |
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| 76 | equals the opcode field, then we have found the correct instruction. */ |
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| 77 | |
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| 78 | struct nios2_opcode |
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| 79 | { |
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| 80 | const char *name; /* The name of the instruction. */ |
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| 81 | const char *args; /* A string describing the arguments for this |
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| 82 | instruction. */ |
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| 83 | const char *args_test; /* Like args, but with an extra argument for |
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| 84 | the expected opcode. */ |
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| 85 | unsigned long num_args; /* The number of arguments the instruction |
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| 86 | takes. */ |
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| 87 | unsigned long match; /* The basic opcode for the instruction. */ |
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| 88 | unsigned long mask; /* Mask for the opcode field of the |
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| 89 | instruction. */ |
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| 90 | unsigned long pinfo; /* Is this a real instruction or instruction |
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| 91 | macro? */ |
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| 92 | enum overflow_type overflow_msg; /* Used to generate informative |
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| 93 | message when fixup overflows. */ |
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| 94 | }; |
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| 95 | |
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| 96 | /* This value is used in the nios2_opcode.pinfo field to indicate that the |
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| 97 | instruction is a macro or pseudo-op. This requires special treatment by |
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| 98 | the assembler, and is used by the disassembler to determine whether to |
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| 99 | check for a nop. */ |
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| 100 | #define NIOS2_INSN_MACRO 0x80000000 |
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| 101 | #define NIOS2_INSN_MACRO_MOV 0x80000001 |
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| 102 | #define NIOS2_INSN_MACRO_MOVI 0x80000002 |
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| 103 | #define NIOS2_INSN_MACRO_MOVIA 0x80000004 |
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| 104 | |
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| 105 | #define NIOS2_INSN_RELAXABLE 0x40000000 |
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| 106 | #define NIOS2_INSN_UBRANCH 0x00000010 |
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| 107 | #define NIOS2_INSN_CBRANCH 0x00000020 |
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| 108 | #define NIOS2_INSN_CALL 0x00000040 |
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| 109 | |
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| 110 | #define NIOS2_INSN_ADDI 0x00000080 |
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| 111 | #define NIOS2_INSN_ANDI 0x00000100 |
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| 112 | #define NIOS2_INSN_ORI 0x00000200 |
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| 113 | #define NIOS2_INSN_XORI 0x00000400 |
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| 114 | |
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| 115 | |
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| 116 | /* Associates a register name ($6) with a 5-bit index (eg 6). */ |
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| 117 | struct nios2_reg |
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| 118 | { |
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| 119 | const char *name; |
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| 120 | const int index; |
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| 121 | }; |
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| 122 | |
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| 123 | |
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| 124 | /* These are bit masks and shift counts for accessing the various |
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| 125 | fields of a Nios II instruction. */ |
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| 126 | |
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| 127 | /* Macros for getting and setting an instruction field. */ |
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| 128 | #define GET_INSN_FIELD(X, i) \ |
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| 129 | (((i) & OP_MASK_##X) >> OP_SH_##X) |
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| 130 | #define SET_INSN_FIELD(X, i, j) \ |
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| 131 | ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X))) |
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| 132 | |
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| 133 | /* Instruction field definitions. */ |
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| 134 | #define IW_A_LSB 27 |
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| 135 | #define IW_A_MSB 31 |
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| 136 | #define IW_A_SZ 5 |
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| 137 | #define IW_A_MASK 0x1f |
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| 138 | |
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| 139 | #define IW_B_LSB 22 |
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| 140 | #define IW_B_MSB 26 |
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| 141 | #define IW_B_SZ 5 |
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| 142 | #define IW_B_MASK 0x1f |
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| 143 | |
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| 144 | #define IW_C_LSB 17 |
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| 145 | #define IW_C_MSB 21 |
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| 146 | #define IW_C_SZ 5 |
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| 147 | #define IW_C_MASK 0x1f |
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| 148 | |
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| 149 | #define IW_IMM16_LSB 6 |
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| 150 | #define IW_IMM16_MSB 21 |
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| 151 | #define IW_IMM16_SZ 16 |
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| 152 | #define IW_IMM16_MASK 0xffff |
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| 153 | |
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| 154 | #define IW_IMM26_LSB 6 |
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| 155 | #define IW_IMM26_MSB 31 |
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| 156 | #define IW_IMM26_SZ 26 |
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| 157 | #define IW_IMM26_MASK 0x3ffffff |
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| 158 | |
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| 159 | #define IW_OP_LSB 0 |
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| 160 | #define IW_OP_MSB 5 |
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| 161 | #define IW_OP_SZ 6 |
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| 162 | #define IW_OP_MASK 0x3f |
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| 163 | |
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| 164 | #define IW_OPX_LSB 11 |
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| 165 | #define IW_OPX_MSB 16 |
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| 166 | #define IW_OPX_SZ 6 |
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| 167 | #define IW_OPX_MASK 0x3f |
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| 168 | |
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| 169 | #define IW_SHIFT_IMM5_LSB 6 |
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| 170 | #define IW_SHIFT_IMM5_MSB 10 |
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| 171 | #define IW_SHIFT_IMM5_SZ 5 |
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| 172 | #define IW_SHIFT_IMM5_MASK 0x1f |
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| 173 | |
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| 174 | #define IW_CONTROL_REGNUM_LSB 6 |
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| 175 | #define IW_CONTROL_REGNUM_MSB 9 |
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| 176 | #define IW_CONTROL_REGNUM_SZ 4 |
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| 177 | #define IW_CONTROL_REGNUM_MASK 0xf |
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| 178 | |
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| 179 | /* Operator mask and shift. */ |
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| 180 | #define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB) |
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| 181 | #define OP_SH_OP IW_OP_LSB |
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| 182 | |
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| 183 | /* Masks and shifts for I-type instructions. */ |
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| 184 | #define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB) |
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| 185 | #define OP_SH_IOP IW_OP_LSB |
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| 186 | |
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| 187 | #define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB) |
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| 188 | #define OP_SH_IMM16 IW_IMM16_LSB |
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| 189 | |
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| 190 | #define OP_MASK_IRD (IW_B_MASK << IW_B_LSB) |
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| 191 | #define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */ |
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| 192 | |
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| 193 | #define OP_MASK_IRT (IW_B_MASK << IW_B_LSB) |
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| 194 | #define OP_SH_IRT IW_B_LSB |
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| 195 | |
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| 196 | #define OP_MASK_IRS (IW_A_MASK << IW_A_LSB) |
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| 197 | #define OP_SH_IRS IW_A_LSB |
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| 198 | |
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| 199 | /* Masks and shifts for R-type instructions. */ |
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| 200 | #define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB) |
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| 201 | #define OP_SH_ROP IW_OP_LSB |
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| 202 | |
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| 203 | #define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB) |
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| 204 | #define OP_SH_ROPX IW_OPX_LSB |
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| 205 | |
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| 206 | #define OP_MASK_RRD (IW_C_MASK << IW_C_LSB) |
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| 207 | #define OP_SH_RRD IW_C_LSB |
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| 208 | |
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| 209 | #define OP_MASK_RRT (IW_B_MASK << IW_B_LSB) |
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| 210 | #define OP_SH_RRT IW_B_LSB |
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| 211 | |
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| 212 | #define OP_MASK_RRS (IW_A_MASK << IW_A_LSB) |
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| 213 | #define OP_SH_RRS IW_A_LSB |
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| 214 | |
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| 215 | /* Masks and shifts for J-type instructions. */ |
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| 216 | #define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB) |
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| 217 | #define OP_SH_JOP IW_OP_LSB |
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| 218 | |
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| 219 | #define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB) |
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| 220 | #define OP_SH_IMM26 IW_IMM26_LSB |
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| 221 | |
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| 222 | /* Masks and shifts for CTL instructions. */ |
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| 223 | #define OP_MASK_RCTL 0x000007c0 |
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| 224 | #define OP_SH_RCTL 6 |
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| 225 | |
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| 226 | /* Break instruction imm5 field. */ |
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| 227 | #define OP_MASK_TRAP_IMM5 0x000007c0 |
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| 228 | #define OP_SH_TRAP_IMM5 6 |
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| 229 | |
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| 230 | /* Instruction imm5 field. */ |
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| 231 | #define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB) |
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| 232 | #define OP_SH_IMM5 IW_SHIFT_IMM5_LSB |
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| 233 | |
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| 234 | /* Cache operation fields (type j,i(s)). */ |
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| 235 | #define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB) |
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| 236 | #define OP_SH_CACHE_OPX IW_B_LSB |
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| 237 | #define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB) |
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| 238 | #define OP_SH_CACHE_RRS IW_A_LSB |
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| 239 | |
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| 240 | /* Custom instruction masks. */ |
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| 241 | #define OP_MASK_CUSTOM_A 0x00010000 |
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| 242 | #define OP_SH_CUSTOM_A 16 |
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| 243 | |
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| 244 | #define OP_MASK_CUSTOM_B 0x00008000 |
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| 245 | #define OP_SH_CUSTOM_B 15 |
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| 246 | |
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| 247 | #define OP_MASK_CUSTOM_C 0x00004000 |
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| 248 | #define OP_SH_CUSTOM_C 14 |
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| 249 | |
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| 250 | #define OP_MASK_CUSTOM_N 0x00003fc0 |
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| 251 | #define OP_SH_CUSTOM_N 6 |
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| 252 | #define OP_MAX_CUSTOM_N 255 |
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| 253 | |
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| 254 | /* OP instruction values. */ |
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| 255 | #define OP_ADDI 4 |
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| 256 | #define OP_ANDHI 44 |
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| 257 | #define OP_ANDI 12 |
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| 258 | #define OP_BEQ 38 |
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| 259 | #define OP_BGE 14 |
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| 260 | #define OP_BGEU 46 |
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| 261 | #define OP_BLT 22 |
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| 262 | #define OP_BLTU 54 |
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| 263 | #define OP_BNE 30 |
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| 264 | #define OP_BR 6 |
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| 265 | #define OP_CALL 0 |
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| 266 | #define OP_CMPEQI 32 |
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| 267 | #define OP_CMPGEI 8 |
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| 268 | #define OP_CMPGEUI 40 |
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| 269 | #define OP_CMPLTI 16 |
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| 270 | #define OP_CMPLTUI 48 |
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| 271 | #define OP_CMPNEI 24 |
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| 272 | #define OP_CUSTOM 50 |
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| 273 | #define OP_FLUSHD 59 |
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| 274 | #define OP_FLUSHDA 27 |
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| 275 | #define OP_INITD 51 |
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| 276 | #define OP_INITDA 19 |
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| 277 | #define OP_JMPI 1 |
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| 278 | #define OP_LDB 7 |
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| 279 | #define OP_LDBIO 39 |
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| 280 | #define OP_LDBU 3 |
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| 281 | #define OP_LDBUIO 35 |
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| 282 | #define OP_LDH 15 |
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| 283 | #define OP_LDHIO 47 |
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| 284 | #define OP_LDHU 11 |
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| 285 | #define OP_LDHUIO 43 |
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| 286 | #define OP_LDL 31 |
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| 287 | #define OP_LDW 23 |
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| 288 | #define OP_LDWIO 55 |
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| 289 | #define OP_MULI 36 |
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| 290 | #define OP_OPX 58 |
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| 291 | #define OP_ORHI 52 |
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| 292 | #define OP_ORI 20 |
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| 293 | #define OP_RDPRS 56 |
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| 294 | #define OP_STB 5 |
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| 295 | #define OP_STBIO 37 |
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| 296 | #define OP_STC 29 |
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| 297 | #define OP_STH 13 |
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| 298 | #define OP_STHIO 45 |
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| 299 | #define OP_STW 21 |
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| 300 | #define OP_STWIO 53 |
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| 301 | #define OP_XORHI 60 |
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| 302 | #define OP_XORI 28 |
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| 303 | |
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| 304 | /* OPX instruction values. */ |
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| 305 | #define OPX_ADD 49 |
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| 306 | #define OPX_AND 14 |
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| 307 | #define OPX_BREAK 52 |
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| 308 | #define OPX_BRET 9 |
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| 309 | #define OPX_CALLR 29 |
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| 310 | #define OPX_CMPEQ 32 |
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| 311 | #define OPX_CMPGE 8 |
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| 312 | #define OPX_CMPGEU 40 |
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| 313 | #define OPX_CMPLT 16 |
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| 314 | #define OPX_CMPLTU 48 |
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| 315 | #define OPX_CMPNE 24 |
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| 316 | #define OPX_CRST 62 |
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| 317 | #define OPX_DIV 37 |
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| 318 | #define OPX_DIVU 36 |
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| 319 | #define OPX_ERET 1 |
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| 320 | #define OPX_FLUSHI 12 |
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| 321 | #define OPX_FLUSHP 4 |
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| 322 | #define OPX_HBREAK 53 |
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| 323 | #define OPX_INITI 41 |
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| 324 | #define OPX_INTR 61 |
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| 325 | #define OPX_JMP 13 |
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| 326 | #define OPX_MUL 39 |
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| 327 | #define OPX_MULXSS 31 |
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| 328 | #define OPX_MULXSU 23 |
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| 329 | #define OPX_MULXUU 7 |
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| 330 | #define OPX_NEXTPC 28 |
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| 331 | #define OPX_NOR 6 |
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| 332 | #define OPX_OR 22 |
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| 333 | #define OPX_RDCTL 38 |
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| 334 | #define OPX_RET 5 |
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| 335 | #define OPX_ROL 3 |
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| 336 | #define OPX_ROLI 2 |
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| 337 | #define OPX_ROR 11 |
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| 338 | #define OPX_SLL 19 |
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| 339 | #define OPX_SLLI 18 |
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| 340 | #define OPX_SRA 59 |
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| 341 | #define OPX_SRAI 58 |
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| 342 | #define OPX_SRL 27 |
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| 343 | #define OPX_SRLI 26 |
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| 344 | #define OPX_SUB 57 |
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| 345 | #define OPX_SYNC 54 |
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| 346 | #define OPX_TRAP 45 |
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| 347 | #define OPX_WRCTL 46 |
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| 348 | #define OPX_WRPRS 20 |
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| 349 | #define OPX_XOR 30 |
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| 350 | |
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| 351 | /* The following macros define the opcode matches for each |
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| 352 | instruction code & OP_MASK_INST == OP_MATCH_INST. */ |
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| 353 | |
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| 354 | /* OP instruction matches. */ |
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| 355 | #define OP_MATCH_ADDI OP_ADDI |
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| 356 | #define OP_MATCH_ANDHI OP_ANDHI |
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| 357 | #define OP_MATCH_ANDI OP_ANDI |
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| 358 | #define OP_MATCH_BEQ OP_BEQ |
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| 359 | #define OP_MATCH_BGE OP_BGE |
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| 360 | #define OP_MATCH_BGEU OP_BGEU |
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| 361 | #define OP_MATCH_BLT OP_BLT |
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| 362 | #define OP_MATCH_BLTU OP_BLTU |
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| 363 | #define OP_MATCH_BNE OP_BNE |
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| 364 | #define OP_MATCH_BR OP_BR |
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| 365 | #define OP_MATCH_FLUSHD OP_FLUSHD |
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| 366 | #define OP_MATCH_FLUSHDA OP_FLUSHDA |
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| 367 | #define OP_MATCH_INITD OP_INITD |
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| 368 | #define OP_MATCH_INITDA OP_INITDA |
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| 369 | #define OP_MATCH_CALL OP_CALL |
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| 370 | #define OP_MATCH_CMPEQI OP_CMPEQI |
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| 371 | #define OP_MATCH_CMPGEI OP_CMPGEI |
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| 372 | #define OP_MATCH_CMPGEUI OP_CMPGEUI |
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| 373 | #define OP_MATCH_CMPLTI OP_CMPLTI |
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| 374 | #define OP_MATCH_CMPLTUI OP_CMPLTUI |
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| 375 | #define OP_MATCH_CMPNEI OP_CMPNEI |
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| 376 | #define OP_MATCH_JMPI OP_JMPI |
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| 377 | #define OP_MATCH_LDB OP_LDB |
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| 378 | #define OP_MATCH_LDBIO OP_LDBIO |
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| 379 | #define OP_MATCH_LDBU OP_LDBU |
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| 380 | #define OP_MATCH_LDBUIO OP_LDBUIO |
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| 381 | #define OP_MATCH_LDH OP_LDH |
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| 382 | #define OP_MATCH_LDHIO OP_LDHIO |
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| 383 | #define OP_MATCH_LDHU OP_LDHU |
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| 384 | #define OP_MATCH_LDHUIO OP_LDHUIO |
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| 385 | #define OP_MATCH_LDL OP_LDL |
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| 386 | #define OP_MATCH_LDW OP_LDW |
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| 387 | #define OP_MATCH_LDWIO OP_LDWIO |
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| 388 | #define OP_MATCH_MULI OP_MULI |
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| 389 | #define OP_MATCH_OPX OP_OPX |
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| 390 | #define OP_MATCH_ORHI OP_ORHI |
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| 391 | #define OP_MATCH_ORI OP_ORI |
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| 392 | #define OP_MATCH_RDPRS OP_RDPRS |
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| 393 | #define OP_MATCH_STB OP_STB |
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| 394 | #define OP_MATCH_STBIO OP_STBIO |
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| 395 | #define OP_MATCH_STC OP_STC |
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| 396 | #define OP_MATCH_STH OP_STH |
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| 397 | #define OP_MATCH_STHIO OP_STHIO |
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| 398 | #define OP_MATCH_STW OP_STW |
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| 399 | #define OP_MATCH_STWIO OP_STWIO |
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| 400 | #define OP_MATCH_CUSTOM OP_CUSTOM |
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| 401 | #define OP_MATCH_XORHI OP_XORHI |
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| 402 | #define OP_MATCH_XORI OP_XORI |
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| 403 | #define OP_MATCH_OPX OP_OPX |
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| 404 | |
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| 405 | /* OPX instruction values. */ |
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| 406 | #define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX) |
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| 407 | |
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| 408 | #define OP_MATCH_ADD OPX_MATCH (OPX_ADD) |
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| 409 | #define OP_MATCH_AND OPX_MATCH (OPX_AND) |
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| 410 | #define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK)) |
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| 411 | #define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET)) |
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| 412 | #define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR)) |
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| 413 | #define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ) |
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| 414 | #define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE) |
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| 415 | #define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU) |
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| 416 | #define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT) |
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| 417 | #define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU) |
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| 418 | #define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE) |
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| 419 | #define OP_MATCH_DIV OPX_MATCH (OPX_DIV) |
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| 420 | #define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU) |
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| 421 | #define OP_MATCH_JMP OPX_MATCH (OPX_JMP) |
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| 422 | #define OP_MATCH_MUL OPX_MATCH (OPX_MUL) |
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| 423 | #define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS) |
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| 424 | #define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU) |
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| 425 | #define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU) |
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| 426 | #define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC) |
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| 427 | #define OP_MATCH_NOR OPX_MATCH (OPX_NOR) |
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| 428 | #define OP_MATCH_OR OPX_MATCH (OPX_OR) |
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| 429 | #define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL) |
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| 430 | #define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET)) |
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| 431 | #define OP_MATCH_ROL OPX_MATCH (OPX_ROL) |
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| 432 | #define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI) |
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| 433 | #define OP_MATCH_ROR OPX_MATCH (OPX_ROR) |
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| 434 | #define OP_MATCH_SLL OPX_MATCH (OPX_SLL) |
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| 435 | #define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI) |
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| 436 | #define OP_MATCH_SRA OPX_MATCH (OPX_SRA) |
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| 437 | #define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI) |
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| 438 | #define OP_MATCH_SRL OPX_MATCH (OPX_SRL) |
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| 439 | #define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI) |
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| 440 | #define OP_MATCH_SUB OPX_MATCH (OPX_SUB) |
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| 441 | #define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC) |
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| 442 | #define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP)) |
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| 443 | #define OP_MATCH_ERET (0xef800000 | OPX_MATCH (OPX_ERET)) |
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| 444 | #define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL) |
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| 445 | #define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS) |
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| 446 | #define OP_MATCH_XOR OPX_MATCH (OPX_XOR) |
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| 447 | #define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI) |
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| 448 | #define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP) |
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| 449 | #define OP_MATCH_INITI OPX_MATCH (OPX_INITI) |
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| 450 | |
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| 451 | /* Some unusual op masks. */ |
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| 452 | #define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ |
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| 453 | | OP_MASK_ROPX | OP_MASK_OP) \ |
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| 454 | & 0xfffff03f) |
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| 455 | #define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
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| 456 | | OP_MASK_OP)) |
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| 457 | #define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
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| 458 | | OP_MASK_OP)) |
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| 459 | #define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
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| 460 | | OP_MASK_OP)) |
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| 461 | #define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ |
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| 462 | | OP_MASK_ROPX | OP_MASK_OP) \ |
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| 463 | & 0xfffff83f) |
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| 464 | #define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
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| 465 | | OP_MASK_OP)) /*& 0xfffff83f */ |
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| 466 | #define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ |
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| 467 | | OP_MASK_OP)) |
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| 468 | #define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
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| 469 | | OP_MASK_OP)) |
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| 470 | #define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
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| 471 | | OP_MASK_OP)) |
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| 472 | |
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| 473 | #define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
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| 474 | #define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
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| 475 | #define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
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| 476 | #define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
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| 477 | #define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ |
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| 478 | | OP_MASK_OP)) /*& 0xfffff83f */ |
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| 479 | |
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| 480 | #ifndef OP_MASK |
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| 481 | #define OP_MASK 0xffffffff |
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| 482 | #endif |
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| 483 | |
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| 484 | /* These convenience macros to extract instruction fields are used by GDB. */ |
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| 485 | #define GET_IW_A(Iw) \ |
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| 486 | (((Iw) >> IW_A_LSB) & IW_A_MASK) |
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| 487 | #define GET_IW_B(Iw) \ |
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| 488 | (((Iw) >> IW_B_LSB) & IW_B_MASK) |
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| 489 | #define GET_IW_C(Iw) \ |
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| 490 | (((Iw) >> IW_C_LSB) & IW_C_MASK) |
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| 491 | #define GET_IW_CONTROL_REGNUM(Iw) \ |
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| 492 | (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK) |
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| 493 | #define GET_IW_IMM16(Iw) \ |
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| 494 | (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK) |
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| 495 | #define GET_IW_IMM26(Iw) \ |
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| 496 | (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK) |
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| 497 | #define GET_IW_OP(Iw) \ |
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| 498 | (((Iw) >> IW_OP_LSB) & IW_OP_MASK) |
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| 499 | #define GET_IW_OPX(Iw) \ |
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| 500 | (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK) |
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| 501 | |
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| 502 | /* These are the data structures we use to hold the instruction information. */ |
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| 503 | extern const struct nios2_opcode nios2_builtin_opcodes[]; |
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| 504 | extern const int bfd_nios2_num_builtin_opcodes; |
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| 505 | extern struct nios2_opcode *nios2_opcodes; |
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| 506 | extern int bfd_nios2_num_opcodes; |
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| 507 | |
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| 508 | /* These are the data structures used to hold the register information. */ |
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| 509 | extern const struct nios2_reg nios2_builtin_regs[]; |
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| 510 | extern struct nios2_reg *nios2_regs; |
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| 511 | extern const int nios2_num_builtin_regs; |
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| 512 | extern int nios2_num_regs; |
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| 513 | |
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| 514 | /* Machine-independent macro for number of opcodes. */ |
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| 515 | #define NUMOPCODES bfd_nios2_num_opcodes |
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| 516 | #define NUMREGISTERS nios2_num_regs; |
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| 517 | |
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| 518 | /* This is made extern so that the assembler can use it to find out |
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| 519 | what instruction caused an error. */ |
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| 520 | extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long); |
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| 521 | |
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| 522 | #endif /* _NIOS2_H */ |
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