1 | /* Print GOULD NPL instructions for GDB, the GNU debugger. |
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2 | Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. |
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3 | |
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4 | This file is part of GDB. |
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5 | |
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6 | GDB is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 3, or (at your option) |
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9 | any later version. |
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10 | |
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11 | GDB is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |
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16 | You should have received a copy of the GNU General Public License |
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17 | along with GDB; see the file COPYING3. If not, write to |
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18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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19 | Boston, MA 02110-1301, USA. */ |
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20 | |
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21 | struct gld_opcode |
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22 | { |
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23 | char *name; |
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24 | unsigned long opcode; |
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25 | unsigned long mask; |
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26 | char *args; |
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27 | int length; |
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28 | }; |
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29 | |
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30 | /* We store four bytes of opcode for all opcodes because that |
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31 | is the most any of them need. The actual length of an instruction |
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32 | is always at least 2 bytes, and at most four. The length of the |
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33 | instruction is based on the opcode. |
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34 | |
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35 | The mask component is a mask saying which bits must match |
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36 | particular opcode in order for an instruction to be an instance |
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37 | of that opcode. |
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38 | |
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39 | The args component is a string containing characters |
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40 | that are used to format the arguments to the instruction. */ |
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41 | |
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42 | /* Kinds of operands: |
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43 | r Register in first field |
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44 | R Register in second field |
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45 | b Base register in first field |
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46 | B Base register in second field |
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47 | v Vector register in first field |
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48 | V Vector register in first field |
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49 | A Optional address register (base register) |
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50 | X Optional index register |
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51 | I Immediate data (16bits signed) |
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52 | O Offset field (16bits signed) |
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53 | h Offset field (15bits signed) |
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54 | d Offset field (14bits signed) |
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55 | S Shift count field |
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56 | |
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57 | any other characters are printed as is... */ |
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58 | |
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59 | /* The assembler requires that this array be sorted as follows: |
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60 | all instances of the same mnemonic must be consecutive. |
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61 | All instances of the same mnemonic with the same number of operands |
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62 | must be consecutive. */ |
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63 | struct gld_opcode gld_opcodes[] = |
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64 | { |
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65 | { "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, |
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66 | { "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, |
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67 | { "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, |
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68 | { "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, |
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69 | { "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, |
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70 | { "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, |
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71 | { "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, |
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72 | { "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, |
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73 | { "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, |
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74 | { "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, |
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75 | { "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, |
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76 | { "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, |
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77 | { "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, |
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78 | { "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, |
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79 | { "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, |
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80 | { "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, |
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81 | { "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, |
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82 | { "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, |
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83 | { "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, |
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84 | { "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, |
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85 | { "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, |
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86 | { "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, |
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87 | { "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, |
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88 | { "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, |
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89 | { "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, |
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90 | { "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, |
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91 | { "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, |
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92 | { "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, |
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93 | { "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, |
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94 | { "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, |
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95 | { "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, |
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96 | { "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, |
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97 | { "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, |
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98 | { "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, |
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99 | { "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, |
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100 | { "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, |
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101 | { "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, |
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102 | { "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, |
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103 | { "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, |
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104 | { "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, |
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105 | |
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106 | { "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, |
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107 | { "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, |
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108 | { "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, |
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109 | { "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, |
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110 | { "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, |
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111 | { "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, |
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112 | { "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, |
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113 | { "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, |
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114 | { "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, |
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115 | { "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, |
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116 | |
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117 | { "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, |
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118 | { "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, |
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119 | { "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, |
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120 | { "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, |
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121 | { "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, |
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122 | { "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, |
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123 | { "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, |
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124 | { "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, |
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125 | { "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, |
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126 | { "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, |
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127 | { "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, |
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128 | { "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, |
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129 | { "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, |
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130 | |
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131 | { "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, |
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132 | { "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, |
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133 | { "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, |
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134 | { "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, |
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135 | { "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, |
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136 | { "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, |
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137 | { "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, |
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138 | { "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, |
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139 | { "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, |
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140 | { "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, |
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141 | { "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, |
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142 | { "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, |
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143 | { "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, |
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144 | { "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, |
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145 | { "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, |
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146 | { "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, |
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147 | { "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, |
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148 | { "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, |
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149 | { "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, |
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150 | { "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, |
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151 | { "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, |
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152 | |
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153 | { "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, |
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154 | { "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, |
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155 | { "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, |
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156 | { "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, |
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157 | { "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, |
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158 | { "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, |
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159 | { "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, |
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160 | { "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, |
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161 | { "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, |
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162 | { "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, |
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163 | { "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, |
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164 | { "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, |
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165 | { "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, |
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166 | { "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, |
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167 | { "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, |
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168 | { "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, |
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169 | { "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, |
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170 | { "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, |
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171 | { "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, |
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172 | { "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, |
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173 | { "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, |
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174 | { "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, |
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175 | { "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, |
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176 | { "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, |
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177 | { "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, |
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178 | { "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, |
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179 | { "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, |
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180 | { "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, |
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181 | { "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, |
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182 | { "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, |
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183 | |
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184 | { "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, |
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185 | { "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, |
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186 | { "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, |
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187 | { "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, |
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188 | { "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, |
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189 | { "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, |
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190 | { "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, |
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191 | { "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, |
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192 | |
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193 | { "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, |
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194 | { "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, |
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195 | { "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, |
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196 | { "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, |
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197 | |
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198 | { "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, |
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199 | { "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, |
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200 | { "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, |
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201 | { "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, |
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202 | { "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, |
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203 | { "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, |
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204 | { "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, |
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205 | { "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, |
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206 | { "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, |
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207 | { "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, |
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208 | { "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, |
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209 | { "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, |
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210 | { "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, |
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211 | { "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, |
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212 | { "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, |
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213 | { "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, |
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214 | { "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, |
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215 | { "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, |
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216 | |
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217 | { "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, |
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218 | { "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, |
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219 | { "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, |
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220 | { "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, |
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221 | { "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, |
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222 | { "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, |
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223 | |
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224 | { "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, |
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225 | { "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, |
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226 | { "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, |
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227 | { "slc", 0x24400000, 0xfc600000, "r,S", 2 }, |
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228 | { "slad", 0x20400000, 0xfc600000, "r,S", 2 }, |
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229 | { "slld", 0x20600000, 0xfc600000, "r,S", 2 }, |
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230 | { "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, |
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231 | { "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, |
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232 | { "src", 0x24000000, 0xfc600000, "r,S", 2 }, |
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233 | { "srad", 0x20000000, 0xfc600000, "r,S", 2 }, |
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234 | { "srld", 0x20200000, 0xfc600000, "r,S", 2 }, |
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235 | { "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, |
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236 | { "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, |
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237 | { "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, |
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238 | { "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, |
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239 | { "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, |
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240 | |
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241 | { "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, |
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242 | { "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, |
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243 | { "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, |
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244 | { "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, |
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245 | { "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, |
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246 | |
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247 | { "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, |
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248 | { "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, |
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249 | { "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, |
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250 | { "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, |
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251 | { "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, |
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252 | { "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, |
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253 | { "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, |
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254 | { "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, |
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255 | { "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, |
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256 | { "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, |
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257 | |
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258 | { "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, |
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259 | { "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, |
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260 | { "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, |
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261 | |
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262 | { "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, |
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263 | { "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, |
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264 | { "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, |
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265 | { "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, |
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266 | { "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, |
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267 | { "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, |
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268 | { "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, |
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269 | { "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, |
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270 | { "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, |
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271 | { "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, |
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272 | { "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, |
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273 | { "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, |
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274 | { "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, |
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275 | { "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, |
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276 | { "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, |
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277 | { "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, |
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278 | { "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, |
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279 | { "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, |
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280 | { "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, |
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281 | { "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, |
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282 | { "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, |
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283 | { "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, |
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284 | { "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, |
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285 | { "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, |
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286 | { "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, |
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287 | { "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, |
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288 | { "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, |
---|
289 | { "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, |
---|
290 | |
---|
291 | { "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, |
---|
292 | { "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, |
---|
293 | { "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, |
---|
294 | { "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, |
---|
295 | { "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, |
---|
296 | { "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, |
---|
297 | { "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, |
---|
298 | { "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, |
---|
299 | { "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, |
---|
300 | { "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, |
---|
301 | |
---|
302 | { "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, |
---|
303 | { "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, |
---|
304 | { "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, |
---|
305 | { "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, |
---|
306 | { "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, |
---|
307 | { "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, |
---|
308 | { "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, |
---|
309 | { "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, |
---|
310 | { "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, |
---|
311 | { "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, |
---|
312 | { "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, |
---|
313 | { "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, |
---|
314 | { "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, |
---|
315 | { "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, |
---|
316 | { "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, |
---|
317 | { "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, |
---|
318 | |
---|
319 | { "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, |
---|
320 | { "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, |
---|
321 | { "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, |
---|
322 | { "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, |
---|
323 | { "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, |
---|
324 | { "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, |
---|
325 | { "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, |
---|
326 | { "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, |
---|
327 | { "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, |
---|
328 | { "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, |
---|
329 | { "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, |
---|
330 | { "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, |
---|
331 | { "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, |
---|
332 | { "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, |
---|
333 | |
---|
334 | { "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, |
---|
335 | { "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, |
---|
336 | { "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, |
---|
337 | { "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, |
---|
338 | { "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, |
---|
339 | |
---|
340 | { "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, |
---|
341 | { "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, |
---|
342 | { "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, |
---|
343 | { "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, |
---|
344 | { "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, |
---|
345 | |
---|
346 | { "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, |
---|
347 | { "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, |
---|
348 | { "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, |
---|
349 | { "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, |
---|
350 | { "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, |
---|
351 | { "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, |
---|
352 | { "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, |
---|
353 | { "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, |
---|
354 | { "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, |
---|
355 | { "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, |
---|
356 | { "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, |
---|
357 | { "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, |
---|
358 | { "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, |
---|
359 | |
---|
360 | { "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, |
---|
361 | { "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, |
---|
362 | { "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, |
---|
363 | { "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, |
---|
364 | { "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, |
---|
365 | { "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, |
---|
366 | { "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, |
---|
367 | { "exr", 0xf8070000, 0xfc0f0000, "", 4 }, |
---|
368 | { "halt", 0x00000000, 0xfc0f0000, "", 2 }, |
---|
369 | { "wait", 0x00010000, 0xfc0f0000, "", 2 }, |
---|
370 | { "nop", 0x00020000, 0xfc0f0000, "", 2 }, |
---|
371 | { "eiae", 0x00030000, 0xfc0f0000, "", 2 }, |
---|
372 | { "efae", 0x000d0000, 0xfc0f0000, "", 2 }, |
---|
373 | { "diae", 0x000e0000, 0xfc0f0000, "", 2 }, |
---|
374 | { "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, |
---|
375 | { "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, |
---|
376 | { "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, |
---|
377 | { "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, |
---|
378 | { "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, |
---|
379 | { "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, |
---|
380 | { "attnio", 0x00050000, 0xfc0f0000, "", 2 }, |
---|
381 | { "fudit", 0x28080000, 0xfc0f0000, "", 2 }, |
---|
382 | { "break", 0x28090000, 0xfc0f0000, "", 2 }, |
---|
383 | { "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, |
---|
384 | { "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, |
---|
385 | { "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, |
---|
386 | { "block", 0x04060000, 0xfc0f0000, "", 2 }, |
---|
387 | { "unblock", 0x04070000, 0xfc0f0000, "", 2 }, |
---|
388 | { "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, |
---|
389 | { "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, |
---|
390 | { "fq", 0x04080000, 0xfc0f0000, "r", 2 }, |
---|
391 | { "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, |
---|
392 | { "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, |
---|
393 | { "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, |
---|
394 | { "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, |
---|
395 | { "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, |
---|
396 | { "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, |
---|
397 | { "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, |
---|
398 | { "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, |
---|
399 | { "grun", 0x0c040000, 0xfc0f0000, "", 2 }, |
---|
400 | { "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, |
---|
401 | { "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, |
---|
402 | |
---|
403 | { "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, |
---|
404 | { "trver", 0x28070000, 0xfc0f0000, "r", 2 }, |
---|
405 | { "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, |
---|
406 | |
---|
407 | { "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, |
---|
408 | { "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, |
---|
409 | { "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, |
---|
410 | { "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, |
---|
411 | { "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, |
---|
412 | { "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, |
---|
413 | { "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, |
---|
414 | { "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, |
---|
415 | { "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, |
---|
416 | }; |
---|
417 | |
---|
418 | int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); |
---|
419 | |
---|
420 | struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / |
---|
421 | sizeof(gld_opcodes[0]); |
---|