[444] | 1 | /* score-inst.h -- Score Instructions Table |
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| 2 | Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
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| 3 | Contributed by: |
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| 4 | Brain.lin (brain.lin@sunplusct.com) |
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| 5 | Mei Ligang (ligang@sunnorth.com.cn) |
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| 6 | Pei-Lin Tsai (pltsai@sunplus.com) |
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| 7 | |
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| 8 | This file is part of GAS, the GNU Assembler. |
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| 9 | |
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| 10 | GAS is free software; you can redistribute it and/or modify |
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| 11 | it under the terms of the GNU General Public License as published by |
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| 12 | the Free Software Foundation; either version 3, or (at your option) |
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| 13 | any later version. |
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| 14 | |
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| 15 | GAS is distributed in the hope that it will be useful, |
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| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 18 | GNU General Public License for more details. |
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| 19 | |
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| 20 | You should have received a copy of the GNU General Public License |
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| 21 | along with GAS; see the file COPYING3. If not, write to the Free |
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| 22 | Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
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| 23 | 02110-1301, USA. */ |
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| 24 | |
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| 25 | #ifndef SCORE_INST_H |
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| 26 | #define SCORE_INST_H |
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| 27 | |
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| 28 | #define LDST_UNALIGN_MASK 0x0000007f |
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| 29 | #define UA_LCB 0x00000060 |
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| 30 | #define UA_LCW 0x00000062 |
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| 31 | #define UA_LCE 0x00000066 |
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| 32 | #define UA_SCB 0x00000068 |
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| 33 | #define UA_SCW 0x0000006a |
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| 34 | #define UA_SCE 0x0000006e |
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| 35 | #define UA_LL 0x0000000c |
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| 36 | #define UA_SC 0x0000000e |
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| 37 | #define LDST16_RR_MASK 0x0000000f |
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| 38 | #define N16_LW 8 |
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| 39 | #define N16_LH 9 |
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| 40 | #define N16_POP 10 |
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| 41 | #define N16_LBU 11 |
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| 42 | #define N16_SW 12 |
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| 43 | #define N16_SH 13 |
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| 44 | #define N16_PUSH 14 |
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| 45 | #define N16_SB 15 |
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| 46 | #define LDST16_RI_MASK 0x7007 |
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| 47 | #define N16_LWP 0x7000 |
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| 48 | #define N16_LHP 0x7001 |
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| 49 | #define N16_LBUP 0x7003 |
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| 50 | #define N16_SWP 0x7004 |
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| 51 | #define N16_SHP 0x7005 |
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| 52 | #define N16_SBP 0x7007 |
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| 53 | #define N16_LIU 0x5000 |
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| 54 | |
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| 55 | #define OPC_PSEUDOLDST_MASK 0x00000007 |
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| 56 | |
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| 57 | enum |
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| 58 | { |
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| 59 | INSN_LW = 0, |
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| 60 | INSN_LH = 1, |
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| 61 | INSN_LHU = 2, |
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| 62 | INSN_LB = 3, |
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| 63 | INSN_SW = 4, |
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| 64 | INSN_SH = 5, |
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| 65 | INSN_LBU = 6, |
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| 66 | INSN_SB = 7, |
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| 67 | }; |
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| 68 | |
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| 69 | /* Sub opcdoe opcode. */ |
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| 70 | enum |
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| 71 | { |
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| 72 | INSN16_LBU = 11, |
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| 73 | INSN16_LH = 9, |
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| 74 | INSN16_LW = 8, |
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| 75 | INSN16_SB = 15, |
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| 76 | INSN16_SH = 13, |
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| 77 | INSN16_SW = 12, |
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| 78 | }; |
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| 79 | |
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| 80 | enum |
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| 81 | { |
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| 82 | LDST_NOUPDATE = 0, |
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| 83 | LDST_PRE = 1, |
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| 84 | LDST_POST = 2, |
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| 85 | }; |
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| 86 | |
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| 87 | enum score_insn_type |
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| 88 | { |
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| 89 | Rd_I4, |
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| 90 | Rd_I5, |
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| 91 | Rd_rvalueBP_I5, |
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| 92 | Rd_lvalueBP_I5, |
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| 93 | Rd_Rs_I5, |
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| 94 | x_Rs_I5, |
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| 95 | x_I5_x, |
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| 96 | Rd_I8, |
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| 97 | Rd_Rs_I14, |
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| 98 | I15, |
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| 99 | Rd_I16, |
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| 100 | Rd_I30, |
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| 101 | Rd_I32, |
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| 102 | Rd_rvalueRs_SI10, |
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| 103 | Rd_lvalueRs_SI10, |
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| 104 | Rd_rvalueRs_preSI12, |
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| 105 | Rd_rvalueRs_postSI12, |
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| 106 | Rd_lvalueRs_preSI12, |
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| 107 | Rd_lvalueRs_postSI12, |
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| 108 | Rd_Rs_SI14, |
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| 109 | Rd_rvalueRs_SI15, |
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| 110 | Rd_lvalueRs_SI15, |
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| 111 | Rd_SI5, |
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| 112 | Rd_SI6, |
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| 113 | Rd_SI16, |
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| 114 | PC_DISP8div2, |
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| 115 | PC_DISP11div2, |
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| 116 | PC_DISP19div2, |
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| 117 | PC_DISP24div2, |
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| 118 | Rd_Rs_Rs, |
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| 119 | x_Rs_x, |
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| 120 | x_Rs_Rs, |
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| 121 | Rd_Rs_x, |
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| 122 | Rd_x_Rs, |
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| 123 | Rd_x_x, |
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| 124 | Rd_Rs, |
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| 125 | Rd_HighRs, |
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| 126 | Rd_lvalueRs, |
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| 127 | Rd_rvalueRs, |
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| 128 | Rd_lvalue32Rs, |
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| 129 | Rd_rvalue32Rs, |
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| 130 | x_Rs, |
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| 131 | NO_OPD, |
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| 132 | NO16_OPD, |
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| 133 | OP5_rvalueRs_SI15, |
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| 134 | I5_Rs_Rs_I5_OP5, |
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| 135 | x_rvalueRs_post4, |
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| 136 | Rd_rvalueRs_post4, |
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| 137 | Rd_x_I5, |
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| 138 | Rd_lvalueRs_post4, |
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| 139 | x_lvalueRs_post4, |
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| 140 | Rd_LowRs, |
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| 141 | Rd_Rs_Rs_imm, |
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| 142 | Insn_Type_PCE, |
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| 143 | Insn_Type_SYN, |
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| 144 | Insn_GP, |
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| 145 | Insn_PIC, |
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| 146 | Insn_internal, |
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| 147 | Insn_BCMP, |
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| 148 | Ra_I9_I5, |
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| 149 | }; |
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| 150 | |
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| 151 | enum score_data_type |
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| 152 | { |
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| 153 | _IMM4 = 0, |
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| 154 | _IMM5, |
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| 155 | _IMM8, |
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| 156 | _IMM14, |
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| 157 | _IMM15, |
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| 158 | _IMM16, |
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| 159 | _SIMM10 = 6, |
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| 160 | _SIMM12, |
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| 161 | _SIMM14, |
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| 162 | _SIMM15, |
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| 163 | _SIMM16, |
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| 164 | _SIMM14_NEG = 11, |
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| 165 | _IMM16_NEG, |
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| 166 | _SIMM16_NEG, |
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| 167 | _IMM20, |
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| 168 | _IMM25, |
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| 169 | _DISP8div2 = 16, |
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| 170 | _DISP11div2, |
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| 171 | _DISP19div2, |
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| 172 | _DISP24div2, |
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| 173 | _VALUE, |
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| 174 | _VALUE_HI16, |
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| 175 | _VALUE_LO16, |
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| 176 | _VALUE_LDST_LO16 = 23, |
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| 177 | _SIMM16_LA, |
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| 178 | _IMM5_RSHIFT_1, |
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| 179 | _IMM5_RSHIFT_2, |
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| 180 | _SIMM16_LA_POS, |
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| 181 | _IMM5_RANGE_8_31, |
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| 182 | _IMM10_RSHIFT_2, |
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| 183 | _GP_IMM15 = 30, |
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| 184 | _GP_IMM14 = 31, |
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| 185 | _SIMM16_pic = 42, /* Index in score_df_range. */ |
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| 186 | _IMM16_LO16_pic = 43, |
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| 187 | _IMM16_pic = 44, |
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| 188 | |
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| 189 | _SIMM5 = 45, |
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| 190 | _SIMM6 = 46, |
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| 191 | _IMM32 = 47, |
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| 192 | _SIMM32 = 48, |
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| 193 | _IMM11 = 49, |
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| 194 | _IMM5_MULTI_LOAD = 50, |
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| 195 | }; |
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| 196 | |
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| 197 | #define REG_TMP 1 |
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| 198 | |
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| 199 | #define OP_REG_TYPE (1 << 6) |
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| 200 | #define OP_IMM_TYPE (1 << 7) |
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| 201 | #define OP_SH_REGD (OP_REG_TYPE |20) |
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| 202 | #define OP_SH_REGS1 (OP_REG_TYPE |15) |
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| 203 | #define OP_SH_REGS2 (OP_REG_TYPE |10) |
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| 204 | #define OP_SH_I (OP_IMM_TYPE | 1) |
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| 205 | #define OP_SH_RI15 (OP_IMM_TYPE | 0) |
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| 206 | #define OP_SH_I12 (OP_IMM_TYPE | 3) |
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| 207 | #define OP_SH_DISP24 (OP_IMM_TYPE | 1) |
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| 208 | #define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) |
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| 209 | #define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) |
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| 210 | #define OP_SH_I5 (OP_IMM_TYPE |10) |
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| 211 | #define OP_SH_I10 (OP_IMM_TYPE | 5) |
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| 212 | #define OP_SH_COPID (OP_IMM_TYPE | 5) |
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| 213 | #define OP_SH_TRAPI5 (OP_IMM_TYPE |15) |
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| 214 | #define OP_SH_I15 (OP_IMM_TYPE |10) |
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| 215 | |
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| 216 | #define OP16_SH_REGD (OP_REG_TYPE | 8) |
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| 217 | #define OP16_SH_REGS1 (OP_REG_TYPE | 4) |
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| 218 | #define OP16_SH_I45 (OP_IMM_TYPE | 3) |
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| 219 | #define OP16_SH_I8 (OP_IMM_TYPE | 0) |
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| 220 | #define OP16_SH_DISP8 (OP_IMM_TYPE | 0) |
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| 221 | #define OP16_SH_DISP11 (OP_IMM_TYPE | 1) |
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| 222 | |
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| 223 | enum insn_class |
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| 224 | { |
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| 225 | INSN_CLASS_16, |
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| 226 | INSN_CLASS_32, |
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| 227 | INSN_CLASS_48, |
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| 228 | INSN_CLASS_PCE, |
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| 229 | INSN_CLASS_SYN |
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| 230 | }; |
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| 231 | |
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| 232 | /* s3_s7: Globals for both tc-score.c and elf32-score.c. */ |
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| 233 | extern int score3; |
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| 234 | extern int score7; |
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| 235 | |
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| 236 | #endif |
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