source: trunk/libs/newlib/src/include/opcode/v850.h @ 466

Last change on this file since 466 was 444, checked in by satin@…, 6 years ago

add newlib,libalmos-mkh, restructure shared_syscalls.h and mini-libc

File size: 8.8 KB
RevLine 
[444]1/* v850.h -- Header file for NEC V850 opcode table
2   Copyright 1996-2013 Free Software Foundation, Inc.
3   Written by J.T. Conklin, Cygnus Support
4
5   This file is part of GDB, GAS, and the GNU binutils.
6
7   GDB, GAS, and the GNU binutils are free software; you can redistribute
8   them and/or modify them under the terms of the GNU General Public
9   License as published by the Free Software Foundation; either version 3,
10   or (at your option) any later version.
11
12   GDB, GAS, and the GNU binutils are distributed in the hope that they
13   will be useful, but WITHOUT ANY WARRANTY; without even the implied
14   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
15   the GNU General Public License for more details.
16
17   You should have received a copy of the GNU General Public License
18   along with this file; see the file COPYING3.  If not, write to the Free
19   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20   MA 02110-1301, USA.  */
21
22#ifndef V850_H
23#define V850_H
24
25/* The opcode table is an array of struct v850_opcode.  */
26
27struct v850_opcode
28{
29  /* The opcode name.  */
30  const char *name;
31
32  /* The opcode itself.  Those bits which will be filled in with
33     operands are zeroes.  */
34  unsigned long opcode;
35
36  /* The opcode mask.  This is used by the disassembler.  This is a
37     mask containing ones indicating those bits which must match the
38     opcode field, and zeroes indicating those bits which need not
39     match (and are presumably filled in by operands).  */
40  unsigned long mask;
41
42  /* An array of operand codes.  Each code is an index into the
43     operand table.  They appear in the order which the operands must
44     appear in assembly code, and are terminated by a zero.  */
45  unsigned char operands[8];
46
47  /* Which (if any) operand is a memory operand.  */
48  unsigned int memop;
49
50  /* Target processor(s).  A bit field of processors which support
51     this instruction.  Note a bit field is used as some instructions
52     are available on multiple, different processor types, whereas
53     other instructions are only available on one specific type.  */
54  unsigned int processors;
55};
56
57/* Values for architecture number.  */
58#define arch_V850      0
59#define arch_V850E     (arch_V850 + 1)
60#define arch_V850E1    (arch_V850E + 1)
61#define arch_V850E2    (arch_V850E1 + 1)
62#define arch_V850E2V3  (arch_V850E2 + 1)
63#define arch_V850E3V5  (arch_V850E2V3 + 1)
64#define arch_separator (arch_V850E3V5 + 1)
65
66#define opt_EXTENSION  (arch_separator)
67#define opt_ALIAS      (opt_EXTENSION + 1)
68
69/* Values for the processors field in the v850_opcode structure.  */
70#define PROCESSOR_V850       (1 << (arch_V850))     /* Just the V850.  */
71#define PROCESSOR_V850E      (1 << (arch_V850E))    /* Just the V850E.  */
72#define PROCESSOR_V850E1     (1 << (arch_V850E1))   /* Just the V850E1.  */
73#define PROCESSOR_V850E2     (1 << (arch_V850E2))   /* Just the V850E2.  */
74#define PROCESSOR_V850E2V3   (1 << (arch_V850E2V3)) /* Just the V850E2V3.  */
75#define PROCESSOR_V850E3V5   (1 << (arch_V850E3V5)) /* Just the V850E3V5.  */
76
77/* UPPERS */
78#define PROCESSOR_V850E3V5_UP (PROCESSOR_V850E3V5)
79#define PROCESSOR_V850E2V3_UP (PROCESSOR_V850E2V3 | PROCESSOR_V850E3V5_UP)
80#define PROCESSOR_V850E2_UP   (PROCESSOR_V850E2   | PROCESSOR_V850E2V3_UP)
81#define PROCESSOR_V850E_UP    (PROCESSOR_V850E    | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
82#define PROCESSOR_ALL         (PROCESSOR_V850     | PROCESSOR_V850E_UP)
83
84#define PROCESSOR_MASK        (PROCESSOR_ALL)
85#define PROCESSOR_NOT_V850    (PROCESSOR_ALL & (~ PROCESSOR_V850))         /* Any processor except the V850.  */
86
87#define PROCESSOR_UNKNOWN    ~(PROCESSOR_MASK)
88
89/* OPTIONS */
90#define PROCESSOR_OPTION_EXTENSION (1 << (opt_EXTENSION))                  /* Enable extension opcodes.  */
91#define PROCESSOR_OPTION_ALIAS     (1 << (opt_ALIAS))                      /* Enable alias opcodes.  */
92
93#define SET_PROCESSOR_MASK(mask,set)    ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
94
95/* The table itself is sorted by major opcode number, and is otherwise
96   in the order in which the disassembler should consider
97   instructions.  */
98extern const struct v850_opcode v850_opcodes[];
99extern const int v850_num_opcodes;
100
101
102/* The operands table is an array of struct v850_operand.  */
103
104struct v850_operand
105{
106  /* The number of bits in the operand.  */
107  /* If this value is -1 then the operand's bits are in a discontinous
108     distribution in the instruction. */
109  int bits;
110
111  /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
112  /* (bits == -1): Bit mask of the bits in the operand.  */
113  int shift;
114
115  /* Insertion function.  This is used by the assembler.  To insert an
116     operand value into an instruction, check this field.
117
118     If it is NULL, execute
119         i |= (op & ((1 << o->bits) - 1)) << o->shift;
120     (i is the instruction which we are filling in, o is a pointer to
121     this structure, and op is the opcode value; this assumes twos
122     complement arithmetic).
123
124     If this field is not NULL, then simply call it with the
125     instruction and the operand value.  It will return the new value
126     of the instruction.  If the ERRMSG argument is not NULL, then if
127     the operand value is illegal, *ERRMSG will be set to a warning
128     string (the operand will be inserted in any case).  If the
129     operand value is legal, *ERRMSG will be unchanged (most operands
130     can accept any value).  */
131  unsigned long (* insert)
132    (unsigned long instruction, long op, const char ** errmsg);
133
134  /* Extraction function.  This is used by the disassembler.  To
135     extract this operand type from an instruction, check this field.
136
137     If it is NULL, compute
138         op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
139         if (o->flags & V850_OPERAND_SIGNED)
140             op = (op << (32 - o->bits)) >> (32 - o->bits);
141     (i is the instruction, o is a pointer to this structure, and op
142     is the result; this assumes twos complement arithmetic).
143
144     If this field is not NULL, then simply call it with the
145     instruction value.  It will return the value of the operand.  If
146     the INVALID argument is not NULL, *INVALID will be set to
147     non-zero if this operand type can not actually be extracted from
148     this operand (i.e., the instruction does not match).  If the
149     operand is valid, *INVALID will not be changed.  */
150  unsigned long (* extract) (unsigned long instruction, int * invalid);
151
152  /* One bit syntax flags.  */
153  int flags;
154
155  int default_reloc;
156};
157
158/* Elements in the table are retrieved by indexing with values from
159   the operands field of the v850_opcodes table.  */
160
161extern const struct v850_operand v850_operands[];
162
163/* Values defined for the flags field of a struct v850_operand.  */
164
165/* This operand names a general purpose register.  */
166#define V850_OPERAND_REG        0x01
167
168/* This operand is the ep register.  */
169#define V850_OPERAND_EP         0x02
170
171/* This operand names a system register.  */
172#define V850_OPERAND_SRG        0x04
173
174/* Prologue eilogue type instruction, V850E specific.  */
175#define V850E_OPERAND_REG_LIST  0x08
176
177/* This operand names a condition code used in the setf instruction.  */
178#define V850_OPERAND_CC         0x10
179
180#define V850_OPERAND_FLOAT_CC   0x20
181
182/* This operand names a vector purpose register.  */
183#define V850_OPERAND_VREG       0x40
184
185/* 16 bit immediate follows instruction, V850E specific.  */
186#define V850E_IMMEDIATE16       0x80
187
188/* hi16 bit immediate follows instruction, V850E specific.  */
189#define V850E_IMMEDIATE16HI     0x100
190
191/* 23 bit immediate follows instruction, V850E specific.  */
192#define V850E_IMMEDIATE23       0x200
193
194/* 32 bit immediate follows instruction, V850E specific.  */
195#define V850E_IMMEDIATE32       0x400
196
197/* This is a relaxable operand.   Only used for D9->D22 branch relaxing
198   right now.  We may need others in the future (or maybe handle them like
199   promoted operands on the mn10300?).  */
200#define V850_OPERAND_RELAX      0x800
201
202/* This operand takes signed values.  */
203#define V850_OPERAND_SIGNED     0x1000
204
205/* This operand is a displacement.  */
206#define V850_OPERAND_DISP       0x2000
207
208/* This operand is a PC displacement.  */
209#define V850_PCREL              0x4000
210
211/* The register specified must be even number.  */
212#define V850_REG_EVEN           0x8000
213
214/* The register specified must not be r0.  */
215#define V850_NOT_R0             0x20000
216
217/* The register specified must not be 0.  */
218#define V850_NOT_IMM0           0x40000
219
220/* The condition code must not be SA CONDITION.  */
221#define V850_NOT_SA             0x80000
222
223/* The operand has '!' prefix.  */
224#define V850_OPERAND_BANG       0x100000
225
226/* The operand has '%' prefix.  */
227#define V850_OPERAND_PERCENT    0x200000
228
229/* This operand is a cache oparation.  */
230#define V850_OPERAND_CACHEOP    0x400000
231
232/* This operand is a prefetch oparation.  */
233#define V850_OPERAND_PREFOP     0x800000
234
235/* A PC-relative displacement where a positive value indicates a backwards displacement.  */
236#define V850_INVERSE_PCREL      0x1000000
237
238extern int v850_msg_is_out_of_range (const char *);
239
240#endif /* V850_H */
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