[444] | 1 | /* Copyright (c) 2009, 2010, 2011, 2012 ARM Ltd. All rights reserved. |
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| 2 | |
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| 3 | Redistribution and use in source and binary forms, with or without |
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| 4 | modification, are permitted provided that the following conditions |
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| 5 | are met: |
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| 6 | 1. Redistributions of source code must retain the above copyright |
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| 7 | notice, this list of conditions and the following disclaimer. |
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| 8 | 2. Redistributions in binary form must reproduce the above copyright |
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| 9 | notice, this list of conditions and the following disclaimer in the |
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| 10 | documentation and/or other materials provided with the distribution. |
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| 11 | 3. The name of the company may not be used to endorse or promote |
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| 12 | products derived from this software without specific prior written |
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| 13 | permission. |
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| 14 | |
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| 15 | THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 16 | WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 17 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 18 | IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 19 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 20 | TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 21 | PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 22 | LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 23 | NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 24 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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| 25 | |
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| 26 | #include "newlib.h" |
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| 27 | #include "svc.h" |
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| 28 | |
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| 29 | /* ANSI concatenation macros. */ |
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| 30 | #define CONCAT(a, b) CONCAT2(a, b) |
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| 31 | #define CONCAT2(a, b) a ## b |
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| 32 | |
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| 33 | #ifdef __USER_LABEL_PREFIX__ |
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| 34 | #define FUNCTION( name ) CONCAT (__USER_LABEL_PREFIX__, name) |
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| 35 | #else |
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| 36 | #error __USER_LABEL_PREFIX is not defined |
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| 37 | #endif |
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| 38 | |
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| 39 | |
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| 40 | .text |
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| 41 | .align 2 |
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| 42 | _init_vectors: |
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| 43 | /* Installs a table of exception vectors to catch and handle all |
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| 44 | exceptions by terminating the process with a diagnostic. */ |
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| 45 | adr x0, vectors |
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| 46 | msr vbar_el3, x0 |
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| 47 | msr vbar_el2, x0 |
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| 48 | msr vbar_el1, x0 |
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| 49 | ret |
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| 50 | |
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| 51 | curr_sp0_sync: |
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| 52 | curr_sp0_irq: |
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| 53 | curr_sp0_fiq: |
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| 54 | curr_sp0_serror: |
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| 55 | curr_spx_sync: |
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| 56 | curr_spx_irq: |
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| 57 | curr_spx_fiq: |
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| 58 | curr_spx_serror: |
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| 59 | lower_a64_sync: |
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| 60 | lower_a64_irq: |
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| 61 | lower_a64_fiq: |
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| 62 | lower_a64_serror: |
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| 63 | lower_a32_sync: |
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| 64 | lower_a32_irq: |
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| 65 | lower_a32_fiq: |
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| 66 | lower_a32_serror: |
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| 67 | mov x0, 2 |
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| 68 | adr x1, .LC3 |
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| 69 | mov x2, 26 |
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| 70 | bl FUNCTION (write) |
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| 71 | mov x0, 126 |
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| 72 | b FUNCTION (exit) /* Cannot return. */ |
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| 73 | .LC3: |
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| 74 | .string "Terminated by exception.\n" |
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| 75 | |
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| 76 | .macro ventry label |
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| 77 | .align 7 |
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| 78 | b \label |
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| 79 | .endm |
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| 80 | |
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| 81 | /* AArch64 Exception Model -- 3.5.5 Exception Vectors. */ |
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| 82 | |
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| 83 | .align 12 |
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| 84 | vectors: |
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| 85 | /* Current EL with SP0. */ |
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| 86 | ventry curr_sp0_sync /* Synchronous */ |
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| 87 | ventry curr_sp0_irq /* Irq/vIRQ */ |
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| 88 | ventry curr_sp0_fiq /* Fiq/vFIQ */ |
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| 89 | ventry curr_sp0_serror /* SError/VSError */ |
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| 90 | |
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| 91 | /* Current EL with SPx. */ |
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| 92 | ventry curr_spx_sync /* Synchronous */ |
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| 93 | ventry curr_spx_irq /* IRQ/vIRQ */ |
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| 94 | ventry curr_spx_fiq /* FIQ/vFIQ */ |
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| 95 | ventry curr_spx_serror /* SError/VSError */ |
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| 96 | |
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| 97 | /* Lower EL using AArch64. */ |
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| 98 | ventry lower_a64_sync /* Synchronous */ |
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| 99 | ventry lower_a64_irq /* IRQ/vIRQ */ |
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| 100 | ventry lower_a64_fiq /* FIQ/vFIQ */ |
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| 101 | ventry lower_a64_serror /* SError/VSError */ |
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| 102 | |
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| 103 | /* Lower EL using AArch32. */ |
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| 104 | ventry lower_a32_sync /* Synchronous */ |
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| 105 | ventry lower_a32_irq /* IRQ/vIRQ */ |
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| 106 | ventry lower_a32_fiq /* FIQ/vFIQ */ |
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| 107 | ventry lower_a32_serror /* SError/VSError */ |
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| 108 | |
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| 109 | |
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| 110 | .text |
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| 111 | .align 2 |
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| 112 | _flat_map: |
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| 113 | /* Page table setup (identity mapping). */ |
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| 114 | adrp x0, ttb |
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| 115 | add x0, x0, :lo12:ttb |
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| 116 | msr ttbr0_el3, x0 |
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| 117 | adr x1, . /* phys address */ |
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| 118 | bic x1, x1, #(1 << 30) - 1 /* 1GB block alignment */ |
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| 119 | add x2, x0, x1, lsr #(30 - 3) /* offset in level 1 page |
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| 120 | table */ |
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| 121 | mov x3, #0x401 /* page table attributes |
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| 122 | (AF, block) */ |
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| 123 | orr x1, x1, x3 |
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| 124 | mov x3, #(1 << 30) /* 1GB block */ |
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| 125 | str x1, [x2], #8 /* 1st GB */ |
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| 126 | add x1, x1, x3 |
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| 127 | str x1, [x2] /* 2nd GB */ |
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| 128 | |
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| 129 | /* Setup/enable the MMU. */ |
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| 130 | |
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| 131 | /* RES1, RES1, 40-bit PA, 39-bit VA, inner/outer cacheable WB */ |
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| 132 | ldr x0, =(1 << 31) | (1 << 23) | (2 << 16) | 25 | (3 << 10) | (3 << 8) |
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| 133 | msr tcr_el3, x0 |
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| 134 | |
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| 135 | mov x0, #0xee /* Inner/outer cacheable WB */ |
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| 136 | msr mair_el3, x0 |
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| 137 | isb |
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| 138 | |
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| 139 | mrs x0, sctlr_el3 |
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| 140 | ldr x1, =0x100d /* bits I(12) SA(3) C(2) M(0) */ |
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| 141 | bic x0, x0, #(1 << 1) /* clear bit A(1) */ |
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| 142 | bic x0, x0, #(1 << 19) /* clear WXN */ |
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| 143 | orr x0, x0, x1 /* set bits */ |
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| 144 | |
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| 145 | dsb sy |
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| 146 | msr sctlr_el3, x0 |
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| 147 | isb |
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| 148 | ret |
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| 149 | |
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| 150 | .data |
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| 151 | .align 12 |
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| 152 | ttb: |
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| 153 | .space 4096, 0 |
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| 154 | |
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| 155 | |
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| 156 | .text |
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| 157 | .align 2 |
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| 158 | .global FUNCTION (_cpu_init_hook) |
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| 159 | .type FUNCTION (_cpu_init_hook), %function |
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| 160 | FUNCTION (_cpu_init_hook): |
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| 161 | sub sp, sp, #16 |
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| 162 | str x30, [sp, xzr] |
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| 163 | bl _init_vectors |
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| 164 | bl _flat_map |
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| 165 | ldr x30, [sp, xzr] |
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| 166 | add sp, sp, #16 |
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| 167 | ret |
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| 168 | .size FUNCTION (_cpu_init_hook), .-FUNCTION (_cpu_init_hook) |
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