[444] | 1 | /* Copyright (c) 2005-2013 ARM Ltd. All rights reserved. |
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| 2 | |
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| 3 | Redistribution and use in source and binary forms, with or without |
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| 4 | modification, are permitted provided that the following conditions |
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| 5 | are met: |
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| 6 | 1. Redistributions of source code must retain the above copyright |
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| 7 | notice, this list of conditions and the following disclaimer. |
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| 8 | 2. Redistributions in binary form must reproduce the above copyright |
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| 9 | notice, this list of conditions and the following disclaimer in the |
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| 10 | documentation and/or other materials provided with the distribution. |
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| 11 | 3. The name of the company may not be used to endorse or promote |
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| 12 | products derived from this software without specific prior written |
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| 13 | permission. |
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| 14 | |
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| 15 | THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 16 | WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 17 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 18 | IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 19 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 20 | TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 21 | PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 22 | LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 23 | NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 24 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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| 25 | |
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| 26 | /* This file gives a basic initialisation of a Cortex-A series core. It is |
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| 27 | the bare minimum required to get Cortex-A core running with a semihosting |
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| 28 | interface. |
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| 29 | |
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| 30 | It sets up a basic 1:1 phsyical address to virtual address mapping; |
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| 31 | turns the MMU on; enables branch prediction; activates any integrated |
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| 32 | caches; enables the Advanced SIMD and VFP co-processors; and installs |
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| 33 | basic exception handlers. |
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| 34 | |
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| 35 | It does not handle peripherals, and assumes all memory is Normal. |
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| 36 | |
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| 37 | It does not change processor state from the startup privilege and security |
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| 38 | level. |
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| 39 | |
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| 40 | This has only been tested to work in ARM state. |
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| 41 | |
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| 42 | By default it assumes exception vectors are located from address 0. |
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| 43 | However, if this is not true they can be moved by defining the |
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| 44 | _rdimon_vector_base symbol. For example if you have HIVECS enabled you |
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| 45 | may pass --defsym _rdimon_vector_base=0xffff0000 on the linker command |
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| 46 | line. */ |
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| 47 | |
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| 48 | /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A |
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| 49 | has been defined since 4.2 onwards, which is when v7-a support was added |
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| 50 | and hence 'A' profile support was added in the compiler. Allow for this |
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| 51 | file to be built with older compilers. */ |
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| 52 | #if defined(__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') |
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| 53 | .syntax unified |
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| 54 | .arch armv7-a |
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| 55 | .arm |
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| 56 | |
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| 57 | @ CPU Initialisation |
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| 58 | .globl _rdimon_hw_init_hook |
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| 59 | .type _rdimon_hw_init_hook, %function |
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| 60 | |
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| 61 | _rdimon_hw_init_hook: |
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| 62 | @ Only run the code on CPU 0 - otherwise spin |
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| 63 | mrc 15, 0, r4, cr0, cr0, 5 @ Read MPIDR |
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| 64 | ands r4, r4, #15 |
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| 65 | spin: |
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| 66 | bne spin |
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| 67 | |
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| 68 | mov r10, lr @ Save LR for final return |
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| 69 | |
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| 70 | #ifdef __ARMEB__ |
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| 71 | @ Setup for Big Endian |
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| 72 | setend be |
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| 73 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 74 | orr r4, r4, #(1<<25) @ Switch to Big Endian (Set SCTLR.EE) |
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| 75 | mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR |
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| 76 | #else |
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| 77 | @ Setup for Little Endian |
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| 78 | setend le |
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| 79 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 80 | bic r4, r4, #(1<<25) @ Switch to LE (unset SCTLR.EE) |
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| 81 | mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR |
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| 82 | #endif |
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| 83 | |
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| 84 | bl is_a15_a7 |
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| 85 | |
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| 86 | @ For Cortex-A15 and Cortex-A7 only: |
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| 87 | @ Write zero into the ACTLR to turn everything on. |
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| 88 | itt eq |
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| 89 | moveq r4, #0 |
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| 90 | mcreq 15, 0, r4, c1, c0, 1 |
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| 91 | isb |
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| 92 | |
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| 93 | @ For Cortex-A15 and Cortex-A7 only: |
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| 94 | @ Set ACTLR:SMP bit before enabling the caches and MMU, |
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| 95 | @ or performing any cache and TLB maintenance operations. |
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| 96 | ittt eq |
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| 97 | mrceq 15, 0, r4, c1, c0, 1 @ Read ACTLR |
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| 98 | orreq r4, r4, #(1<<6) @ Enable ACTLR:SMP |
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| 99 | mcreq 15, 0, r4, c1, c0, 1 @ Write ACTLR |
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| 100 | isb |
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| 101 | |
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| 102 | @ Setup for exceptions being taken to Thumb/ARM state |
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| 103 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 104 | #if defined(__thumb__) |
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| 105 | orr r4, r4, #(1 << 30) @ Enable SCTLR.TE |
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| 106 | #else |
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| 107 | bic r4, r4, #(1 << 30) @ Disable SCTLR.TE |
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| 108 | #endif |
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| 109 | mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR |
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| 110 | |
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| 111 | bl __reset_caches |
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| 112 | |
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| 113 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 114 | orr r4, r4, #(1<<22) @ Enable unaligned mode |
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| 115 | bic r4, r4, #2 @ Disable alignment faults |
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| 116 | bic r4, r4, #1 @ Disable MMU |
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| 117 | mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR |
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| 118 | |
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| 119 | mov r4, #0 |
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| 120 | mcr 15, 0, r4, cr8, cr7, 0 @ Write TLBIALL - Invaliidate unified |
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| 121 | @ TLB |
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| 122 | @ Setup MMU Primary table P=V mapping. |
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| 123 | mvn r4, #0 |
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| 124 | mcr 15, 0, r4, cr3, cr0, 0 @ Write DACR |
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| 125 | |
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| 126 | mov r4, #0 @ Always use TTBR0, no LPAE |
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| 127 | mcr 15, 0, r4, cr2, cr0, 2 @ Write TTBCR |
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| 128 | adr r4, page_table_addr @ Load the base for vectors |
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| 129 | ldr r4, [r4] |
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| 130 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR |
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| 131 | tst r0, #0x80000000 @ bis[31] |
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| 132 | @ Set page table flags - there are two page table flag formats for the |
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| 133 | @ architecture. For systems without multiprocessor extensions we use 0x1 |
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| 134 | @ which is Inner cacheable/Outer non-cacheable. For systems with |
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| 135 | @ multiprocessor extensions we use 0x59 which is Inner/Outer write-back, |
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| 136 | @ no write-allocate, and cacheable. See the ARMARM-v7AR for more details. |
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| 137 | it ne |
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| 138 | addne r4, r4, #0x58 |
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| 139 | add r4, r4, #1 |
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| 140 | |
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| 141 | mcr 15, 0, r4, cr2, cr0, 0 @ Write TTBR0 |
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| 142 | |
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| 143 | mov r0, #34 @ 0x22 @ TR0 and TR1 - normal memory |
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| 144 | orr r0, r0, #(1 << 19) @ Shareable |
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| 145 | mcr 15, 0, r0, cr10, cr2, 0 @ Write PRRR |
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| 146 | movw r0, #0x33 |
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| 147 | movt r0, #0x33 |
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| 148 | mcr 15, 0, r0, cr10, cr2, 1 @ Write NMRR |
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| 149 | mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR |
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| 150 | bic r0, r0, #(1 << 28) @ Clear TRE bit |
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| 151 | mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR |
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| 152 | |
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| 153 | @ Now install the vector code - we move the Vector code from where it is |
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| 154 | @ in the image to be based at _rdimon_vector_base. We have to do this copy |
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| 155 | @ as the code is all PC-relative. We actually cheat and do a BX <reg> so |
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| 156 | @ that we are at a known address relatively quickly and have to move as |
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| 157 | @ little code as possible. |
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| 158 | mov r7, #(VectorCode_Limit - VectorCode) |
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| 159 | adr r5, VectorCode |
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| 160 | adr r6, vector_base_addr @ Load the base for vectors |
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| 161 | ldr r6, [r6] |
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| 162 | |
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| 163 | copy_loop: @ Do the copy |
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| 164 | ldr r4, [r5], #4 |
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| 165 | str r4, [r6], #4 |
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| 166 | subs r7, r7, #4 |
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| 167 | bne copy_loop |
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| 168 | |
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| 169 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 170 | bic r4, r4, #0x1000 @ Disable I Cache |
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| 171 | bic r4, r4, #4 @ Disable D Cache |
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| 172 | orr r4, r4, #1 @ Enable MMU |
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| 173 | bic r4, r4, #(1 << 28) @ Clear TRE bit |
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| 174 | mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR |
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| 175 | mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR |
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| 176 | orr r4, r4, #0x00f00000 @ Turn on VFP Co-procs |
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| 177 | bic r4, r4, #0x80000000 @ Clear ASEDIS bit |
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| 178 | mcr 15, 0, r4, cr1, cr0, 2 @ Write CPACR |
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| 179 | isb |
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| 180 | mov r4, #0 |
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| 181 | mcr 15, 0, r4, cr7, cr5, 4 @ Flush prefetch buffer |
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| 182 | mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR |
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| 183 | ubfx r4, r4, #20, #4 @ Extract bits [20, 23) |
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| 184 | cmp r4, #0xf @ If not all set then the CPU does not |
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| 185 | itt eq @ have FP or Advanced SIMD. |
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| 186 | moveq r4, #0x40000000 @ Enable FP and Advanced SIMD |
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| 187 | mcreq 10, 7, r4, cr8, cr0, 0 @ vmsr fpexc, r4 |
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| 188 | skip_vfp_enable: |
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| 189 | bl __enable_caches @ Turn caches on |
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| 190 | bx r10 @ Return to CRT startup routine |
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| 191 | |
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| 192 | @ This enable us to be more precise about which caches we want |
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| 193 | init_cpu_client_enable_dcache: |
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| 194 | init_cpu_client_enable_icache: |
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| 195 | mov r0, #1 |
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| 196 | bx lr |
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| 197 | |
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| 198 | vector_base_addr: |
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| 199 | .word _rdimon_vector_base |
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| 200 | .weak _rdimon_vector_base |
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| 201 | page_table_addr: |
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| 202 | .word page_tables |
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| 203 | |
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| 204 | @ Vector code - must be PIC and in ARM state. |
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| 205 | VectorCode: |
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| 206 | b vector_reset |
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| 207 | b vector_undef |
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| 208 | b vector_swi |
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| 209 | b vector_prefetch |
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| 210 | b vector_dataabt |
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| 211 | b vector_reserved |
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| 212 | b vector_irq |
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| 213 | b vector_fiq |
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| 214 | |
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| 215 | vector_reset: |
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| 216 | adr sp, vector_sp_base |
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| 217 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 218 | mov r4, #0 |
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| 219 | b vector_common |
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| 220 | vector_undef: |
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| 221 | adr sp, vector_sp_base |
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| 222 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 223 | mov r4, #1 |
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| 224 | b vector_common |
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| 225 | vector_swi: |
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| 226 | adr sp, vector_sp_base |
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| 227 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 228 | mov r4, #2 |
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| 229 | b vector_common |
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| 230 | vector_prefetch: |
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| 231 | adr sp, vector_sp_base |
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| 232 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 233 | mov r4, #3 |
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| 234 | b vector_common |
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| 235 | vector_dataabt: |
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| 236 | adr sp, vector_sp_base |
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| 237 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 238 | mov r4, #4 |
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| 239 | b vector_common |
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| 240 | vector_reserved: |
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| 241 | adr sp, vector_sp_base |
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| 242 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 243 | mov r4, #5 |
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| 244 | b vector_common |
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| 245 | vector_irq: |
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| 246 | adr sp, vector_sp_base |
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| 247 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 248 | mov r4, #6 |
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| 249 | b vector_common |
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| 250 | vector_fiq: |
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| 251 | adr sp, vector_sp_base |
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| 252 | push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
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| 253 | mov r4, #7 |
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| 254 | b vector_common |
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| 255 | vector_common: |
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| 256 | adr r1, vector_common_adr @ Find where we're going to |
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| 257 | ldr r1, [r1] |
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| 258 | bx r1 @ And branch there |
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| 259 | vector_common_adr: |
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| 260 | .word vector_common_2 @ Common handling code |
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| 261 | |
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| 262 | @ Vector stack |
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| 263 | .p2align 3 @ Align to 8 byte boundary boundary to |
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| 264 | @ keep ABI compatibility |
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| 265 | .fill 32, 4, 0 @ 32-entry stack is enough for vector |
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| 266 | @ handlers. |
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| 267 | vector_sp_base: |
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| 268 | VectorCode_Limit: |
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| 269 | @ End of PIC code for vectors |
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| 270 | |
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| 271 | @ Common Handling of vectors |
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| 272 | .type vector_common_2, %function |
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| 273 | vector_common_2: |
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| 274 | mrs r1, APSR |
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| 275 | mrs r2, SPSR |
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| 276 | push {r1, r2} @ Save PSRs |
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| 277 | |
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| 278 | @ Output the vector we have caught |
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| 279 | bl out_nl |
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| 280 | adr r0, which_vector |
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| 281 | bl out_string |
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| 282 | adr r0, vector_names |
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| 283 | mov r1, #11 |
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| 284 | mla r0, r4, r1, r0 |
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| 285 | bl out_string |
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| 286 | bl out_nl |
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| 287 | |
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| 288 | @ Dump the registers |
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| 289 | adrl r6, register_names |
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| 290 | mov r7, #0 |
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| 291 | dump_r_loop: |
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| 292 | mov r0, r6 |
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| 293 | bl out_string |
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| 294 | add r6, r6, #6 |
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| 295 | ldr r0, [sp, r7, lsl #2] |
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| 296 | bl out_word |
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| 297 | bl out_nl |
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| 298 | add r7, r7, #1 |
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| 299 | cmp r7, #16 |
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| 300 | blt dump_r_loop |
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| 301 | adr r0, end |
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| 302 | bl out_string |
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| 303 | |
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| 304 | @ And exit |
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| 305 | mov r0, #24 |
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| 306 | orr r1, r4, #0x20000 |
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| 307 | svc 0x00123456 |
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| 308 | |
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| 309 | @ Output the string in r0 |
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| 310 | out_string: |
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| 311 | push {lr} |
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| 312 | mov r1, r0 |
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| 313 | mov r0, #4 |
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| 314 | svc 0x00123456 |
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| 315 | pop {pc} |
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| 316 | |
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| 317 | @ Output a New-line |
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| 318 | out_nl: |
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| 319 | mov r0, #10 |
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| 320 | @ Fallthrough |
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| 321 | |
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| 322 | @ Output the character in r0 |
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| 323 | out_char: |
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| 324 | push {lr} |
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| 325 | strb r0, [sp, #-4]! |
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| 326 | mov r0, #3 |
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| 327 | mov r1, sp |
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| 328 | svc 0x00123456 |
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| 329 | add sp, sp, #4 |
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| 330 | pop {pc} |
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| 331 | |
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| 332 | @ Output the value of r0 as a hex-word |
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| 333 | out_word: |
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| 334 | push {r4, r5, r6, lr} |
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| 335 | mov r4, r0 |
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| 336 | mov r5, #28 |
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| 337 | adr r6, hexchars |
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| 338 | word_loop: |
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| 339 | lsr r0, r4, r5 |
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| 340 | and r0, r0, #15 |
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| 341 | ldrb r0, [r6, r0] |
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| 342 | bl out_char |
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| 343 | subs r5, r5, #4 |
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| 344 | bpl word_loop |
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| 345 | pop {r4, r5, r6, pc} |
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| 346 | |
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| 347 | hexchars: |
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| 348 | .ascii "0123456789abcdef" |
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| 349 | |
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| 350 | which_vector: |
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| 351 | .asciz "Hit vector:" |
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| 352 | end: |
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| 353 | .asciz "End.\n" |
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| 354 | |
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| 355 | vector_names: |
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| 356 | .asciz "reset " |
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| 357 | .asciz "undef " |
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| 358 | .asciz "swi " |
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| 359 | .asciz "prefetch " |
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| 360 | .asciz "data abort" |
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| 361 | .asciz "reserved " |
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| 362 | .asciz "irq " |
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| 363 | .asciz "fiq " |
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| 364 | |
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| 365 | register_names: |
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| 366 | .asciz "apsr " |
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| 367 | .asciz "spsr " |
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| 368 | .asciz "r0 " |
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| 369 | .asciz "r1 " |
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| 370 | .asciz "r2 " |
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| 371 | .asciz "r3 " |
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| 372 | .asciz "r4 " |
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| 373 | .asciz "r5 " |
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| 374 | .asciz "r6 " |
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| 375 | .asciz "r7 " |
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| 376 | .asciz "r8 " |
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| 377 | .asciz "r9 " |
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| 378 | .asciz "r10 " |
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| 379 | .asciz "r11 " |
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| 380 | .asciz "r12 " |
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| 381 | .asciz "r14 " |
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| 382 | |
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| 383 | .p2align 3 |
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| 384 | |
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| 385 | |
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| 386 | @ Enable the caches |
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| 387 | __enable_caches: |
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| 388 | mov r0, #0 |
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| 389 | mcr 15, 0, r0, cr8, cr7, 0 @ Invalidate all unified-TLB |
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| 390 | mov r0, #0 |
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| 391 | mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor |
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| 392 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 393 | orr r4, r4, #0x800 @ Enable branch predictor |
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| 394 | mcr 15, 0, r4, cr1, cr0, 0 @ Set SCTLR |
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| 395 | mov r5, lr @ Save LR as we're going to BL |
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| 396 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 397 | bl init_cpu_client_enable_icache |
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| 398 | cmp r0, #0 |
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| 399 | it ne |
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| 400 | orrne r4, r4, #0x1000 @ Enable I-Cache |
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| 401 | bl init_cpu_client_enable_dcache |
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| 402 | cmp r0, #0 |
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| 403 | it ne |
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| 404 | orrne r4, r4, #4 |
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| 405 | mcr 15, 0, r4, cr1, cr0, 0 @ Enable D-Cache |
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| 406 | bx r5 @ Return |
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| 407 | |
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| 408 | __reset_caches: |
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| 409 | mov ip, lr @ Save LR |
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| 410 | mov r0, #0 |
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| 411 | mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor |
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| 412 | mrc 15, 0, r6, cr1, cr0, 0 @ Read SCTLR |
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| 413 | mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR! |
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| 414 | bic r0, r0, #0x1000 @ Disable I cache |
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| 415 | mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR |
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| 416 | mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR |
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| 417 | tst r0, #3 @ Harvard Cache? |
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| 418 | mov r0, #0 |
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| 419 | it ne |
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| 420 | mcrne 15, 0, r0, cr7, cr5, 0 @ Invalidate Instruction Cache? |
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| 421 | |
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| 422 | mrc 15, 0, r1, cr1, cr0, 0 @ Read SCTLR (again!) |
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| 423 | orr r1, r1, #0x800 @ Enable branch predictor |
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| 424 | |
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| 425 | @ If we're not enabling caches we have |
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| 426 | @ no more work to do. |
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| 427 | bl init_cpu_client_enable_icache |
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| 428 | cmp r0, #0 |
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| 429 | it ne |
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| 430 | orrne r1, r1, #0x1000 @ Enable I-Cache now - |
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| 431 | @ We actually only do this if we have a |
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| 432 | @ Harvard style cache. |
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| 433 | it eq |
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| 434 | bleq init_cpu_client_enable_dcache |
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| 435 | itt eq |
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| 436 | cmpeq r0, #0 |
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| 437 | beq Finished1 |
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| 438 | |
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| 439 | mcr 15, 0, r1, cr1, cr0, 0 @ Write SCTLR (turn on Branch predictor & I-cache) |
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| 440 | |
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| 441 | mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR |
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| 442 | ands r3, r0, #0x7000000 |
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| 443 | lsr r3, r3, #23 @ Total cache levels << 1 |
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| 444 | beq Finished1 |
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| 445 | |
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| 446 | mov lr, #0 @ lr = cache level << 1 |
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| 447 | Loop11: |
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| 448 | mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR |
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| 449 | add r2, lr, lr, lsr #1 @ r2 holds cache 'set' position |
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| 450 | lsr r1, r0, r2 @ Bottom 3-bits are Ctype for this level |
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| 451 | and r1, r1, #7 @ Get those 3-bits alone |
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| 452 | cmp r1, #2 |
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| 453 | blt Skip1 @ No cache or only I-Cache at this level |
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| 454 | mcr 15, 2, lr, cr0, cr0, 0 @ Write CSSELR |
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| 455 | mov r1, #0 |
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| 456 | isb sy |
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| 457 | mrc 15, 1, r1, cr0, cr0, 0 @ Read CCSIDR |
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| 458 | and r2, r1, #7 @ Extract line length field |
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| 459 | add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes) |
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| 460 | movw r0, #0x3ff |
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| 461 | ands r0, r0, r1, lsr #3 @ r0 is the max number on the way size |
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| 462 | clz r4, r0 @ r4 is the bit position of the way size increment |
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| 463 | movw r5, #0x7fff |
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| 464 | ands r5, r5, r1, lsr #13 @ r5 is the max number of the index size (right aligned) |
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| 465 | Loop21: |
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| 466 | mov r7, r0 @ r7 working copy of max way size |
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| 467 | Loop31: |
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| 468 | orr r1, lr, r7, lsl r4 @ factor in way number and cache number |
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| 469 | orr r1, r1, r5, lsl r2 @ factor in set number |
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| 470 | tst r6, #4 @ D-Cache on? |
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| 471 | ite eq |
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| 472 | mcreq 15, 0, r1, cr7, cr6, 2 @ No - invalidate by set/way |
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| 473 | mcrne 15, 0, r1, cr7, cr14, 2 @ yes - clean + invalidate by set/way |
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| 474 | subs r7, r7, #1 @ Decrement way number |
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| 475 | bge Loop31 |
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| 476 | subs r5, r5, #1 @ Decrement set number |
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| 477 | bge Loop21 |
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| 478 | Skip1: |
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| 479 | add lr, lr, #2 @ increment cache number |
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| 480 | cmp r3, lr |
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| 481 | bgt Loop11 |
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| 482 | Finished1: |
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| 483 | @ Now we know the caches are clean we can: |
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| 484 | mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR |
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| 485 | bic r4, r4, #4 @ Disable D-Cache |
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| 486 | mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR |
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| 487 | mov r4, #0 |
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| 488 | mcr 15, 0, r4, cr7, cr5, 6 @ Write BPIALL |
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| 489 | |
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| 490 | bx ip @ Return |
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| 491 | |
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| 492 | @ Set Z if this is a Cortex-A15 or Cortex_A7 |
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| 493 | @ Other flags corrupted |
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| 494 | is_a15_a7: |
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| 495 | mrc 15, 0, r8, c0, c0, 0 |
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| 496 | movw r9, #0xfff0 |
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| 497 | movt r9, #0xff0f |
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| 498 | and r8, r8, r9 |
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| 499 | movw r9, #0xc0f0 |
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| 500 | movt r9, #0x410f |
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| 501 | cmp r8, r9 |
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| 502 | movw r9, #0xc070 |
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| 503 | movt r9, #0x410f |
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| 504 | it ne |
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| 505 | cmpne r8, r9 |
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| 506 | bx lr |
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| 507 | |
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| 508 | @ Descriptor type: Section |
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| 509 | @ Bufferable: True |
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| 510 | @ Cacheable: True |
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| 511 | @ Execute Never: False |
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| 512 | @ Domain: 0 |
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| 513 | @ Impl. Defined: 0 |
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| 514 | @ Access: 0/11 Full access |
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| 515 | @ TEX: 001 |
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| 516 | @ Shareable: False |
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| 517 | @ Not Global: False |
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| 518 | @ Supersection: False |
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| 519 | #define PT(X) \ |
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| 520 | .word X; |
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| 521 | #define PT2(X) \ |
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| 522 | PT(X) PT(X + 0x100000) PT(X + 0x200000) PT(X + 0x300000) |
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| 523 | #define PT3(X) \ |
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| 524 | PT2(X) PT2(X + 0x400000) PT2(X + 0x800000) PT2(X + 0xc00000) |
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| 525 | #define PT4(X) \ |
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| 526 | PT3(X) PT3(X + 0x1000000) PT3(X + 0x2000000) PT3(X + 0x3000000) |
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| 527 | #define PT5(X) \ |
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| 528 | PT4(X) PT4(X + 0x4000000) PT4(X + 0x8000000) PT4(X + 0xc000000) |
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| 529 | #define PT6(X) \ |
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| 530 | PT5(X) PT5(X + 0x10000000) PT5(X + 0x20000000) PT5(X + 0x30000000) |
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| 531 | #define PT7(X) \ |
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| 532 | PT6(X) PT6(X + 0x40000000) PT6(X + 0x80000000) PT6(X + 0xc0000000) |
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| 533 | |
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| 534 | .section page_tables_section, "aw", %progbits |
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| 535 | .p2align 14 |
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| 536 | page_tables: |
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| 537 | PT7(0x1c0e) |
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| 538 | |
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| 539 | #endif //#if defined(__ARM_ARCH_7A__) || __ARM_ARCH_PROFILE == 'A' |
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