| 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | /************************************************************************ |
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| 14 | * |
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| 15 | * cdefBF535.h |
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| 16 | * |
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| 17 | * (c) Copyright 2002-2005 Analog Devices, Inc. All rights reserved. |
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| 18 | * |
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| 19 | ************************************************************************/ |
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| 20 | |
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| 21 | #ifndef _CDEF_BF535_H |
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| 22 | #define _CDEF_BF535_H |
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| 23 | |
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| 24 | /* include all Core registers and bit definitions */ |
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| 25 | #if defined(__ADSPLPBLACKFIN__) |
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| 26 | #warning cdefBF535.h should only be included for 535 compatible chips. |
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| 27 | #endif |
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| 28 | #include <defBF535.h> |
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| 29 | |
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| 30 | /* include core specific register pointer definitions */ |
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| 31 | #include <cdefblackfin.h> |
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| 32 | |
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| 33 | #ifdef _MISRA_RULES |
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| 34 | #pragma diag(push) |
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| 35 | #pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant") |
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| 36 | #endif /* _MISRA_RULES */ |
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| 37 | |
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| 38 | #ifndef _PTR_TO_VOL_VOID_PTR |
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| 39 | #ifndef _USE_LEGACY_CDEF_BEHAVIOUR |
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| 40 | #define _PTR_TO_VOL_VOID_PTR (void * volatile *) |
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| 41 | #else |
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| 42 | #define _PTR_TO_VOL_VOID_PTR (volatile void **) |
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| 43 | #endif |
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| 44 | #endif |
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| 45 | |
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| 46 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ |
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| 47 | #define pPLL_CTL ((volatile unsigned long *)PLL_CTL) |
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| 48 | #define pPLL_STAT ((volatile unsigned short *)PLL_STAT) |
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| 49 | #define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) |
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| 50 | #define pSWRST ((volatile unsigned short *)SWRST) |
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| 51 | #define pSYSCR ((volatile unsigned short *)SYSCR) |
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| 52 | #define pPLL_IOCKR ((volatile unsigned short *)PLL_IOCKR) |
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| 53 | #define pPLL_IOCK ((volatile unsigned short *)PLL_IOCK) |
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| 54 | |
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| 55 | /* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */ |
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| 56 | #define pCHIPID ((volatile unsigned long *)CHIPID) |
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| 57 | |
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| 58 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ |
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| 59 | #define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) |
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| 60 | #define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) |
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| 61 | #define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) |
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| 62 | #define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) |
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| 63 | #define pSIC_ISR ((volatile unsigned long *)SIC_ISR) |
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| 64 | #define pSIC_IWR ((volatile unsigned long *)SIC_IWR) |
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| 65 | |
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| 66 | /* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ |
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| 67 | #define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) |
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| 68 | #define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) |
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| 69 | #define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) |
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| 70 | |
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| 71 | /* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ |
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| 72 | #define pRTC_STAT ((volatile unsigned long *)RTC_STAT) |
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| 73 | #define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) |
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| 74 | #define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) |
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| 75 | #define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) |
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| 76 | #define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) |
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| 77 | #define pRTC_FAST ((volatile unsigned short *)RTC_FAST) |
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| 78 | |
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| 79 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ |
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| 80 | #define pFIO_DIR ((volatile unsigned short *)FIO_DIR) |
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| 81 | #define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) |
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| 82 | #define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) |
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| 83 | #define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) |
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| 84 | #define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) |
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| 85 | #define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) |
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| 86 | #define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) |
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| 87 | #define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) |
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| 88 | #define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) |
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| 89 | #define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) |
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| 90 | |
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| 91 | /* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ |
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| 92 | #define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) |
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| 93 | #define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) |
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| 94 | #define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) |
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| 95 | |
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| 96 | /* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */ |
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| 97 | #define pUSBD_ID ((volatile unsigned short *)USBD_ID) |
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| 98 | #define pUSBD_FRM ((volatile unsigned short *)USBD_FRM) |
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| 99 | #define pUSBD_FRMAT ((volatile unsigned short *)USBD_FRMAT) |
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| 100 | #define pUSBD_EPBUF ((volatile unsigned short *)USBD_EPBUF) |
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| 101 | #define pUSBD_STAT ((volatile unsigned short *)USBD_STAT) |
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| 102 | #define pUSBD_CTRL ((volatile unsigned short *)USBD_CTRL) |
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| 103 | #define pUSBD_GINTR ((volatile unsigned short *)USBD_GINTR) |
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| 104 | #define pUSBD_GMASK ((volatile unsigned short *)USBD_GMASK) |
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| 105 | #define pUSBD_DMACFG ((volatile unsigned short *)USBD_DMACFG) |
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| 106 | #define pUSBD_DMABL ((volatile unsigned short *)USBD_DMABL) |
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| 107 | #define pUSBD_DMABH ((volatile unsigned short *)USBD_DMABH) |
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| 108 | #define pUSBD_DMACT ((volatile unsigned short *)USBD_DMACT) |
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| 109 | #define pUSBD_DMAIRQ ((volatile unsigned short *)USBD_DMAIRQ) |
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| 110 | #define pUSBD_INTR0 ((volatile unsigned short *)USBD_INTR0) |
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| 111 | #define pUSBD_MASK0 ((volatile unsigned short *)USBD_MASK0) |
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| 112 | #define pUSBD_EPCFG0 ((volatile unsigned short *)USBD_EPCFG0) |
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| 113 | #define pUSBD_EPADR0 ((volatile unsigned short *)USBD_EPADR0) |
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| 114 | #define pUSBD_EPLEN0 ((volatile unsigned short *)USBD_EPLEN0) |
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| 115 | #define pUSBD_INTR1 ((volatile unsigned short *)USBD_INTR1) |
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| 116 | #define pUSBD_MASK1 ((volatile unsigned short *)USBD_MASK1) |
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| 117 | #define pUSBD_EPCFG1 ((volatile unsigned short *)USBD_EPCFG1) |
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| 118 | #define pUSBD_EPADR1 ((volatile unsigned short *)USBD_EPADR1) |
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| 119 | #define pUSBD_EPLEN1 ((volatile unsigned short *)USBD_EPLEN1) |
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| 120 | #define pUSBD_INTR2 ((volatile unsigned short *)USBD_INTR2) |
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| 121 | #define pUSBD_MASK2 ((volatile unsigned short *)USBD_MASK2) |
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| 122 | #define pUSBD_EPCFG2 ((volatile unsigned short *)USBD_EPCFG2) |
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| 123 | #define pUSBD_EPADR2 ((volatile unsigned short *)USBD_EPADR2) |
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| 124 | #define pUSBD_EPLEN2 ((volatile unsigned short *)USBD_EPLEN2) |
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| 125 | #define pUSBD_INTR3 ((volatile unsigned short *)USBD_INTR3) |
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| 126 | #define pUSBD_MASK3 ((volatile unsigned short *)USBD_MASK3) |
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| 127 | #define pUSBD_EPCFG3 ((volatile unsigned short *)USBD_EPCFG3) |
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| 128 | #define pUSBD_EPADR3 ((volatile unsigned short *)USBD_EPADR3) |
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| 129 | #define pUSBD_EPLEN3 ((volatile unsigned short *)USBD_EPLEN3) |
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| 130 | #define pUSBD_INTR4 ((volatile unsigned short *)USBD_INTR4) |
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| 131 | #define pUSBD_MASK4 ((volatile unsigned short *)USBD_MASK4) |
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| 132 | #define pUSBD_EPCFG4 ((volatile unsigned short *)USBD_EPCFG4) |
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| 133 | #define pUSBD_EPADR4 ((volatile unsigned short *)USBD_EPADR4) |
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| 134 | #define pUSBD_EPLEN4 ((volatile unsigned short *)USBD_EPLEN4) |
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| 135 | #define pUSBD_INTR5 ((volatile unsigned short *)USBD_INTR5) |
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| 136 | #define pUSBD_MASK5 ((volatile unsigned short *)USBD_MASK5) |
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| 137 | #define pUSBD_EPCFG5 ((volatile unsigned short *)USBD_EPCFG5) |
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| 138 | #define pUSBD_EPADR5 ((volatile unsigned short *)USBD_EPADR5) |
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| 139 | #define pUSBD_EPLEN5 ((volatile unsigned short *)USBD_EPLEN5) |
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| 140 | #define pUSBD_INTR6 ((volatile unsigned short *)USBD_INTR6) |
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| 141 | #define pUSBD_MASK6 ((volatile unsigned short *)USBD_MASK6) |
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| 142 | #define pUSBD_EPCFG6 ((volatile unsigned short *)USBD_EPCFG6) |
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| 143 | #define pUSBD_EPADR6 ((volatile unsigned short *)USBD_EPADR6) |
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| 144 | #define pUSBD_EPLEN6 ((volatile unsigned short *)USBD_EPLEN6) |
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| 145 | #define pUSBD_INTR7 ((volatile unsigned short *)USBD_INTR7) |
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| 146 | #define pUSBD_MASK7 ((volatile unsigned short *)USBD_MASK7) |
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| 147 | #define pUSBD_EPCFG7 ((volatile unsigned short *)USBD_EPCFG7) |
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| 148 | #define pUSBD_EPADR7 ((volatile unsigned short *)USBD_EPADR7) |
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| 149 | #define pUSBD_EPLEN7 ((volatile unsigned short *)USBD_EPLEN7) |
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| 150 | |
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| 151 | /* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ |
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| 152 | #define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) |
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| 153 | #define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) |
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| 154 | #define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) |
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| 155 | #define pEBIU_SDBCTL ((volatile unsigned long *)EBIU_SDBCTL) |
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| 156 | |
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| 157 | /* Memory Map */ |
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| 158 | |
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| 159 | /* Core MMRs */ |
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| 160 | #define pCOREMMR_BASE ((volatile void *)COREMMR_BASE) |
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| 161 | |
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| 162 | /* System MMRs */ |
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| 163 | #define pSYSMMR_BASE ((volatile void *)SYSMMR_BASE) |
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| 164 | |
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| 165 | /* L1 cache/SRAM internal memory */ |
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| 166 | #define pL1_DATA_A ((void *)L1_DATA_A) |
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| 167 | #define pL1_DATA_B ((void *)L1_DATA_B) |
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| 168 | #define pL1_CODE ((void *)L1_CODE) |
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| 169 | #define pL1_SCRATCH ((void *)L1_SCRATCH) |
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| 170 | |
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| 171 | /* L2 SRAM external memory */ |
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| 172 | #define pL2_BASE ((void *)L2_BASE) |
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| 173 | |
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| 174 | /* PCI Spaces */ |
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| 175 | #define pPCI_CONFIG_SPACE_PORT ((volatile void *)PCI_CONFIG_SPACE_PORT) |
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| 176 | #define pPCI_CONFIG_BASE ((volatile void *)PCI_CONFIG_BASE) |
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| 177 | #define pPCI_IO_BASE ((volatile void *)PCI_IO_BASE) |
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| 178 | #define pPCI_MEM_BASE ((volatile void *)PCI_MEM_BASE) |
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| 179 | |
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| 180 | /* Async Memory Banks */ |
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| 181 | #define pASYNC_BANK3_BASE ((void *)ASYNC_BANK3_BASE) |
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| 182 | #define pASYNC_BANK2_BASE ((void *)ASYNC_BANK2_BASE) |
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| 183 | #define pASYNC_BANK1_BASE ((void *)ASYNC_BANK1_BASE) |
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| 184 | #define pASYNC_BANK0_BASE ((void *)ASYNC_BANK0_BASE) |
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| 185 | |
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| 186 | /* Sync DRAM Banks */ |
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| 187 | #define pSDRAM_BANK3_BASE ((void *)SDRAM_BANK3_BASE) |
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| 188 | #define pSDRAM_BANK2_BASE ((void *)SDRAM_BANK2_BASE) |
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| 189 | #define pSDRAM_BANK1_BASE ((void *)SDRAM_BANK1_BASE) |
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| 190 | #define pSDRAM_BANK0_BASE ((void *)SDRAM_BANK0_BASE) |
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| 191 | |
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| 192 | /* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */ |
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| 193 | #define pUART0_THR ((volatile unsigned short *)UART0_THR) |
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| 194 | #define pUART0_RBR ((volatile unsigned short *)UART0_RBR) |
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| 195 | #define pUART0_DLL ((volatile unsigned short *)UART0_DLL) |
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| 196 | #define pUART0_IER ((volatile unsigned short *)UART0_IER) |
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| 197 | #define pUART0_DLH ((volatile unsigned short *)UART0_DLH) |
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| 198 | #define pUART0_IIR ((volatile unsigned short *)UART0_IIR) |
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| 199 | #define pUART0_LCR ((volatile unsigned short *)UART0_LCR) |
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| 200 | #define pUART0_MCR ((volatile unsigned short *)UART0_MCR) |
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| 201 | #define pUART0_LSR ((volatile unsigned short *)UART0_LSR) |
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| 202 | #define pUART0_MSR ((volatile unsigned short *)UART0_MSR) |
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| 203 | #define pUART0_SCR ((volatile unsigned short *)UART0_SCR) |
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| 204 | #define pUART0_IRCR ((volatile unsigned short *)UART0_IRCR) |
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| 205 | #define pUART0_CURR_PTR_RX ((volatile unsigned short *)UART0_CURR_PTR_RX) |
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| 206 | #define pUART0_CONFIG_RX ((volatile unsigned short *)UART0_CONFIG_RX) |
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| 207 | #define pUART0_START_ADDR_HI_RX ((volatile unsigned short *)UART0_START_ADDR_HI_RX) |
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| 208 | #define pUART0_START_ADDR_LO_RX ((volatile unsigned short *)UART0_START_ADDR_LO_RX) |
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| 209 | #define pUART0_COUNT_RX ((volatile unsigned short *)UART0_COUNT_RX) |
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| 210 | #define pUART0_NEXT_DESCR_RX ((volatile unsigned short *)UART0_NEXT_DESCR_RX) |
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| 211 | #define pUART0_DESCR_RDY_RX ((volatile unsigned short *)UART0_DESCR_RDY_RX) |
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| 212 | #define pUART0_IRQSTAT_RX ((volatile unsigned short *)UART0_IRQSTAT_RX) |
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| 213 | #define pUART0_CURR_PTR_TX ((volatile unsigned short *)UART0_CURR_PTR_TX) |
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| 214 | #define pUART0_CONFIG_TX ((volatile unsigned short *)UART0_CONFIG_TX) |
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| 215 | #define pUART0_START_ADDR_HI_TX ((volatile unsigned short *)UART0_START_ADDR_HI_TX) |
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| 216 | #define pUART0_START_ADDR_LO_TX ((volatile unsigned short *)UART0_START_ADDR_LO_TX) |
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| 217 | #define pUART0_COUNT_TX ((volatile unsigned short *)UART0_COUNT_TX) |
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| 218 | #define pUART0_NEXT_DESCR_TX ((volatile unsigned short *)UART0_NEXT_DESCR_TX) |
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| 219 | #define pUART0_DESCR_RDY_TX ((volatile unsigned short *)UART0_DESCR_RDY_TX) |
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| 220 | #define pUART0_IRQSTAT_TX ((volatile unsigned short *)UART0_IRQSTAT_TX) |
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| 221 | |
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| 222 | /* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */ |
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| 223 | #define pUART1_THR ((volatile unsigned short *)UART1_THR) |
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| 224 | #define pUART1_RBR ((volatile unsigned short *)UART1_RBR) |
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| 225 | #define pUART1_DLL ((volatile unsigned short *)UART1_DLL) |
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| 226 | #define pUART1_IER ((volatile unsigned short *)UART1_IER) |
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| 227 | #define pUART1_DLH ((volatile unsigned short *)UART1_DLH) |
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| 228 | #define pUART1_IIR ((volatile unsigned short *)UART1_IIR) |
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| 229 | #define pUART1_LCR ((volatile unsigned short *)UART1_LCR) |
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| 230 | #define pUART1_MCR ((volatile unsigned short *)UART1_MCR) |
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| 231 | #define pUART1_LSR ((volatile unsigned short *)UART1_LSR) |
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| 232 | #define pUART1_MSR ((volatile unsigned short *)UART1_MSR) |
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| 233 | #define pUART1_SCR ((volatile unsigned short *)UART1_SCR) |
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| 234 | #define pUART1_CURR_PTR_RX ((volatile unsigned short *)UART1_CURR_PTR_RX) |
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| 235 | #define pUART1_CONFIG_RX ((volatile unsigned short *)UART1_CONFIG_RX) |
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| 236 | #define pUART1_START_ADDR_HI_RX ((volatile unsigned short *)UART1_START_ADDR_HI_RX) |
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| 237 | #define pUART1_START_ADDR_LO_RX ((volatile unsigned short *)UART1_START_ADDR_LO_RX) |
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| 238 | #define pUART1_COUNT_RX ((volatile unsigned short *)UART1_COUNT_RX) |
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| 239 | #define pUART1_NEXT_DESCR_RX ((volatile unsigned short *)UART1_NEXT_DESCR_RX) |
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| 240 | #define pUART1_DESCR_RDY_RX ((volatile unsigned short *)UART1_DESCR_RDY_RX) |
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| 241 | #define pUART1_IRQSTAT_RX ((volatile unsigned short *)UART1_IRQSTAT_RX) |
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| 242 | #define pUART1_CURR_PTR_TX ((volatile unsigned short *)UART1_CURR_PTR_TX) |
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| 243 | #define pUART1_CONFIG_TX ((volatile unsigned short *)UART1_CONFIG_TX) |
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| 244 | #define pUART1_START_ADDR_HI_TX ((volatile unsigned short *)UART1_START_ADDR_HI_TX) |
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| 245 | #define pUART1_START_ADDR_LO_TX ((volatile unsigned short *)UART1_START_ADDR_LO_TX) |
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| 246 | #define pUART1_COUNT_TX ((volatile unsigned short *)UART1_COUNT_TX) |
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| 247 | #define pUART1_NEXT_DESCR_TX ((volatile unsigned short *)UART1_NEXT_DESCR_TX) |
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| 248 | #define pUART1_DESCR_RDY_TX ((volatile unsigned short *)UART1_DESCR_RDY_TX) |
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| 249 | #define pUART1_IRQSTAT_TX ((volatile unsigned short *)UART1_IRQSTAT_TX) |
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| 250 | |
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| 251 | /* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */ |
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| 252 | #define pTIMER0_STATUS ((volatile unsigned short *)TIMER0_STATUS) |
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| 253 | #define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) |
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| 254 | #define pTIMER0_COUNTER_LO ((volatile unsigned short *)TIMER0_COUNTER_LO) |
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| 255 | #define pTIMER0_COUNTER_HI ((volatile unsigned short *)TIMER0_COUNTER_HI) |
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| 256 | #define pTIMER0_PERIOD_LO ((volatile unsigned short *)TIMER0_PERIOD_LO) |
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| 257 | #define pTIMER0_PERIOD_HI ((volatile unsigned short *)TIMER0_PERIOD_HI) |
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| 258 | #define pTIMER0_WIDTH_LO ((volatile unsigned short *)TIMER0_WIDTH_LO) |
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| 259 | #define pTIMER0_WIDTH_HI ((volatile unsigned short *)TIMER0_WIDTH_HI) |
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| 260 | #define pTIMER1_STATUS ((volatile unsigned short *)TIMER1_STATUS) |
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| 261 | #define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) |
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| 262 | #define pTIMER1_COUNTER_LO ((volatile unsigned short *)TIMER1_COUNTER_LO) |
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| 263 | #define pTIMER1_COUNTER_HI ((volatile unsigned short *)TIMER1_COUNTER_HI) |
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| 264 | #define pTIMER1_PERIOD_LO ((volatile unsigned short *)TIMER1_PERIOD_LO) |
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| 265 | #define pTIMER1_PERIOD_HI ((volatile unsigned short *)TIMER1_PERIOD_HI) |
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| 266 | #define pTIMER1_WIDTH_LO ((volatile unsigned short *)TIMER1_WIDTH_LO) |
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| 267 | #define pTIMER1_WIDTH_HI ((volatile unsigned short *)TIMER1_WIDTH_HI) |
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| 268 | #define pTIMER2_STATUS ((volatile unsigned short *)TIMER2_STATUS) |
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| 269 | #define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) |
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| 270 | #define pTIMER2_COUNTER_LO ((volatile unsigned short *)TIMER2_COUNTER_LO) |
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| 271 | #define pTIMER2_COUNTER_HI ((volatile unsigned short *)TIMER2_COUNTER_HI) |
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| 272 | #define pTIMER2_PERIOD_LO ((volatile unsigned short *)TIMER2_PERIOD_LO) |
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| 273 | #define pTIMER2_PERIOD_HI ((volatile unsigned short *)TIMER2_PERIOD_HI) |
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| 274 | #define pTIMER2_WIDTH_LO ((volatile unsigned short *)TIMER2_WIDTH_LO) |
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| 275 | #define pTIMER2_WIDTH_HI ((volatile unsigned short *)TIMER2_WIDTH_HI) |
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| 276 | |
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| 277 | /* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */ |
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| 278 | #define pSPORT0_TX_CONFIG ((volatile unsigned short *)SPORT0_TX_CONFIG) |
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| 279 | #define pSPORT0_RX_CONFIG ((volatile unsigned short *)SPORT0_RX_CONFIG) |
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| 280 | #define pSPORT0_TX ((volatile short *)SPORT0_TX) |
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| 281 | #define pSPORT0_RX ((volatile short *)SPORT0_RX) |
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| 282 | #define pSPORT0_TSCLKDIV ((volatile unsigned short *)SPORT0_TSCLKDIV) |
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| 283 | #define pSPORT0_RSCLKDIV ((volatile unsigned short *)SPORT0_RSCLKDIV) |
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| 284 | #define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) |
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| 285 | #define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) |
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| 286 | #define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) |
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| 287 | #define pSPORT0_MTCS0 ((volatile unsigned short *)SPORT0_MTCS0) |
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| 288 | #define pSPORT0_MTCS1 ((volatile unsigned short *)SPORT0_MTCS1) |
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| 289 | #define pSPORT0_MTCS2 ((volatile unsigned short *)SPORT0_MTCS2) |
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| 290 | #define pSPORT0_MTCS3 ((volatile unsigned short *)SPORT0_MTCS3) |
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| 291 | #define pSPORT0_MTCS4 ((volatile unsigned short *)SPORT0_MTCS4) |
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| 292 | #define pSPORT0_MTCS5 ((volatile unsigned short *)SPORT0_MTCS5) |
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| 293 | #define pSPORT0_MTCS6 ((volatile unsigned short *)SPORT0_MTCS6) |
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| 294 | #define pSPORT0_MTCS7 ((volatile unsigned short *)SPORT0_MTCS7) |
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| 295 | #define pSPORT0_MRCS0 ((volatile unsigned short *)SPORT0_MRCS0) |
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| 296 | #define pSPORT0_MRCS1 ((volatile unsigned short *)SPORT0_MRCS1) |
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| 297 | #define pSPORT0_MRCS2 ((volatile unsigned short *)SPORT0_MRCS2) |
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| 298 | #define pSPORT0_MRCS3 ((volatile unsigned short *)SPORT0_MRCS3) |
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| 299 | #define pSPORT0_MRCS4 ((volatile unsigned short *)SPORT0_MRCS4) |
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| 300 | #define pSPORT0_MRCS5 ((volatile unsigned short *)SPORT0_MRCS5) |
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| 301 | #define pSPORT0_MRCS6 ((volatile unsigned short *)SPORT0_MRCS6) |
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| 302 | #define pSPORT0_MRCS7 ((volatile unsigned short *)SPORT0_MRCS7) |
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| 303 | #define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) |
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| 304 | #define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) |
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| 305 | #define pSPORT0_CURR_PTR_RX ((volatile unsigned short *)SPORT0_CURR_PTR_RX) |
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| 306 | #define pSPORT0_CONFIG_DMA_RX ((volatile unsigned short *)SPORT0_CONFIG_DMA_RX) |
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| 307 | #define pSPORT0_START_ADDR_HI_RX ((volatile unsigned short *)SPORT0_START_ADDR_HI_RX) |
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| 308 | #define pSPORT0_START_ADDR_LO_RX ((volatile unsigned short *)SPORT0_START_ADDR_LO_RX) |
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| 309 | #define pSPORT0_COUNT_RX ((volatile unsigned short *)SPORT0_COUNT_RX) |
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| 310 | #define pSPORT0_NEXT_DESCR_RX ((volatile unsigned short *)SPORT0_NEXT_DESCR_RX) |
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| 311 | #define pSPORT0_DESCR_RDY_RX ((volatile unsigned short *)SPORT0_DESCR_RDY_RX) |
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| 312 | #define pSPORT0_IRQSTAT_RX ((volatile unsigned short *)SPORT0_IRQSTAT_RX) |
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| 313 | #define pSPORT0_CURR_PTR_TX ((volatile unsigned short *)SPORT0_CURR_PTR_TX) |
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| 314 | #define pSPORT0_CONFIG_DMA_TX ((volatile unsigned short *)SPORT0_CONFIG_DMA_TX) |
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| 315 | #define pSPORT0_START_ADDR_HI_TX ((volatile unsigned short *)SPORT0_START_ADDR_HI_TX) |
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| 316 | #define pSPORT0_START_ADDR_LO_TX ((volatile unsigned short *)SPORT0_START_ADDR_LO_TX) |
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| 317 | #define pSPORT0_COUNT_TX ((volatile unsigned short *)SPORT0_COUNT_TX) |
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| 318 | #define pSPORT0_NEXT_DESCR_TX ((volatile unsigned short *)SPORT0_NEXT_DESCR_TX) |
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| 319 | #define pSPORT0_DESCR_RDY_TX ((volatile unsigned short *)SPORT0_DESCR_RDY_TX) |
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| 320 | #define pSPORT0_IRQSTAT_TX ((volatile unsigned short *)SPORT0_IRQSTAT_TX) |
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| 321 | |
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| 322 | /* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */ |
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| 323 | #define pSPORT1_TX_CONFIG ((volatile unsigned short *)SPORT1_TX_CONFIG) |
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| 324 | #define pSPORT1_RX_CONFIG ((volatile unsigned short *)SPORT1_RX_CONFIG) |
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| 325 | #define pSPORT1_TX ((volatile short *)SPORT1_TX) |
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| 326 | #define pSPORT1_RX ((volatile short *)SPORT1_RX) |
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| 327 | #define pSPORT1_TSCLKDIV ((volatile unsigned short *)SPORT1_TSCLKDIV) |
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| 328 | #define pSPORT1_RSCLKDIV ((volatile unsigned short *)SPORT1_RSCLKDIV) |
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| 329 | #define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) |
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| 330 | #define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) |
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| 331 | #define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) |
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| 332 | #define pSPORT1_MTCS0 ((volatile unsigned short *)SPORT1_MTCS0) |
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| 333 | #define pSPORT1_MTCS1 ((volatile unsigned short *)SPORT1_MTCS1) |
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| 334 | #define pSPORT1_MTCS2 ((volatile unsigned short *)SPORT1_MTCS2) |
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| 335 | #define pSPORT1_MTCS3 ((volatile unsigned short *)SPORT1_MTCS3) |
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| 336 | #define pSPORT1_MTCS4 ((volatile unsigned short *)SPORT1_MTCS4) |
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| 337 | #define pSPORT1_MTCS5 ((volatile unsigned short *)SPORT1_MTCS5) |
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| 338 | #define pSPORT1_MTCS6 ((volatile unsigned short *)SPORT1_MTCS6) |
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| 339 | #define pSPORT1_MTCS7 ((volatile unsigned short *)SPORT1_MTCS7) |
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| 340 | #define pSPORT1_MRCS0 ((volatile unsigned short *)SPORT1_MRCS0) |
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| 341 | #define pSPORT1_MRCS1 ((volatile unsigned short *)SPORT1_MRCS1) |
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| 342 | #define pSPORT1_MRCS2 ((volatile unsigned short *)SPORT1_MRCS2) |
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| 343 | #define pSPORT1_MRCS3 ((volatile unsigned short *)SPORT1_MRCS3) |
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| 344 | #define pSPORT1_MRCS4 ((volatile unsigned short *)SPORT1_MRCS4) |
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| 345 | #define pSPORT1_MRCS5 ((volatile unsigned short *)SPORT1_MRCS5) |
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| 346 | #define pSPORT1_MRCS6 ((volatile unsigned short *)SPORT1_MRCS6) |
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| 347 | #define pSPORT1_MRCS7 ((volatile unsigned short *)SPORT1_MRCS7) |
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| 348 | #define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) |
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| 349 | #define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) |
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| 350 | #define pSPORT1_CURR_PTR_RX ((volatile unsigned short *)SPORT1_CURR_PTR_RX) |
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| 351 | #define pSPORT1_CONFIG_DMA_RX ((volatile unsigned short *)SPORT1_CONFIG_DMA_RX) |
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| 352 | #define pSPORT1_START_ADDR_HI_RX ((volatile unsigned short *)SPORT1_START_ADDR_HI_RX) |
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| 353 | #define pSPORT1_START_ADDR_LO_RX ((volatile unsigned short *)SPORT1_START_ADDR_LO_RX) |
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| 354 | #define pSPORT1_COUNT_RX ((volatile unsigned short *)SPORT1_COUNT_RX) |
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| 355 | #define pSPORT1_NEXT_DESCR_RX ((volatile unsigned short *)SPORT1_NEXT_DESCR_RX) |
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| 356 | #define pSPORT1_DESCR_RDY_RX ((volatile unsigned short *)SPORT1_DESCR_RDY_RX) |
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| 357 | #define pSPORT1_IRQSTAT_RX ((volatile unsigned short *)SPORT1_IRQSTAT_RX) |
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| 358 | #define pSPORT1_CURR_PTR_TX ((volatile unsigned short *)SPORT1_CURR_PTR_TX) |
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| 359 | #define pSPORT1_CONFIG_DMA_TX ((volatile unsigned short *)SPORT1_CONFIG_DMA_TX) |
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| 360 | #define pSPORT1_START_ADDR_HI_TX ((volatile unsigned short *)SPORT1_START_ADDR_HI_TX) |
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| 361 | #define pSPORT1_START_ADDR_LO_TX ((volatile unsigned short *)SPORT1_START_ADDR_LO_TX) |
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| 362 | #define pSPORT1_COUNT_TX ((volatile unsigned short *)SPORT1_COUNT_TX) |
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| 363 | #define pSPORT1_NEXT_DESCR_TX ((volatile unsigned short *)SPORT1_NEXT_DESCR_TX) |
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| 364 | #define pSPORT1_DESCR_RDY_TX ((volatile unsigned short *)SPORT1_DESCR_RDY_TX) |
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| 365 | #define pSPORT1_IRQSTAT_TX ((volatile unsigned short *)SPORT1_IRQSTAT_TX) |
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| 366 | |
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| 367 | /* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */ |
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| 368 | #define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL) |
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| 369 | #define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG) |
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| 370 | #define pSPI0_ST ((volatile unsigned short *)SPI0_ST) |
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| 371 | #define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR) |
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| 372 | #define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR) |
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| 373 | #define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD) |
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| 374 | #define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW) |
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| 375 | #define pSPI0_CURR_PTR ((volatile unsigned short *)SPI0_CURR_PTR) |
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| 376 | #define pSPI0_CONFIG ((volatile unsigned short *)SPI0_CONFIG) |
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| 377 | #define pSPI0_START_ADDR_HI ((volatile unsigned short *)SPI0_START_ADDR_HI) |
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| 378 | #define pSPI0_START_ADDR_LO ((volatile unsigned short *)SPI0_START_ADDR_LO) |
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| 379 | #define pSPI0_COUNT ((volatile unsigned short *)SPI0_COUNT) |
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| 380 | #define pSPI0_NEXT_DESCR ((volatile unsigned short *)SPI0_NEXT_DESCR) |
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| 381 | #define pSPI0_DESCR_RDY ((volatile unsigned short *)SPI0_DESCR_RDY) |
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| 382 | #define pSPI0_DMA_INT ((volatile unsigned short *)SPI0_DMA_INT) |
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| 383 | |
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| 384 | /* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */ |
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| 385 | #define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL) |
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| 386 | #define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG) |
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| 387 | #define pSPI1_ST ((volatile unsigned short *)SPI1_ST) |
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| 388 | #define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR) |
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| 389 | #define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR) |
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| 390 | #define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD) |
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| 391 | #define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW) |
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| 392 | #define pSPI1_CURR_PTR ((volatile unsigned short *)SPI1_CURR_PTR) |
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| 393 | #define pSPI1_CONFIG ((volatile unsigned short *)SPI1_CONFIG) |
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| 394 | #define pSPI1_START_ADDR_HI ((volatile unsigned short *)SPI1_START_ADDR_HI) |
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| 395 | #define pSPI1_START_ADDR_LO ((volatile unsigned short *)SPI1_START_ADDR_LO) |
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| 396 | #define pSPI1_COUNT ((volatile unsigned short *)SPI1_COUNT) |
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| 397 | #define pSPI1_NEXT_DESCR ((volatile unsigned short *)SPI1_NEXT_DESCR) |
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| 398 | #define pSPI1_DESCR_RDY ((volatile unsigned short *)SPI1_DESCR_RDY) |
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| 399 | #define pSPI1_DMA_INT ((volatile unsigned short *)SPI1_DMA_INT) |
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| 400 | |
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| 401 | /* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */ |
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| 402 | #define pMDD_DCP ((volatile unsigned short *)MDD_DCP) |
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| 403 | #define pMDD_DCFG ((volatile unsigned short *)MDD_DCFG) |
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| 404 | #define pMDD_DSAH ((volatile unsigned short *)MDD_DSAH) |
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| 405 | #define pMDD_DSAL ((volatile unsigned short *)MDD_DSAL) |
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| 406 | #define pMDD_DCT ((volatile unsigned short *)MDD_DCT) |
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| 407 | #define pMDD_DND ((volatile unsigned short *)MDD_DND) |
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| 408 | #define pMDD_DDR ((volatile unsigned short *)MDD_DDR) |
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| 409 | #define pMDD_DI ((volatile unsigned short *)MDD_DI) |
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| 410 | #define pMDS_DCP ((volatile unsigned short *)MDS_DCP) |
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| 411 | #define pMDS_DCFG ((volatile unsigned short *)MDS_DCFG) |
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| 412 | #define pMDS_DSAH ((volatile unsigned short *)MDS_DSAH) |
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| 413 | #define pMDS_DSAL ((volatile unsigned short *)MDS_DSAL) |
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| 414 | #define pMDS_DCT ((volatile unsigned short *)MDS_DCT) |
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| 415 | #define pMDS_DND ((volatile unsigned short *)MDS_DND) |
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| 416 | #define pMDS_DDR ((volatile unsigned short *)MDS_DDR) |
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| 417 | #define pMDS_DI ((volatile unsigned short *)MDS_DI) |
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| 418 | |
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| 419 | /* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */ |
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| 420 | #define pPCI_CTL ((volatile unsigned short *)PCI_CTL) |
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| 421 | #define pPCI_STAT ((volatile unsigned long *)PCI_STAT) |
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| 422 | #define pPCI_ICTL ((volatile unsigned long *)PCI_ICTL) |
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| 423 | #define pPCI_MBAP (_PTR_TO_VOL_VOID_PTR PCI_MBAP) |
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| 424 | #define pPCI_IBAP (_PTR_TO_VOL_VOID_PTR PCI_IBAP) |
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| 425 | #define pPCI_CBAP (_PTR_TO_VOL_VOID_PTR PCI_CBAP) |
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| 426 | #define pPCI_TMBAP (_PTR_TO_VOL_VOID_PTR PCI_TMBAP) |
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| 427 | #define pPCI_TIBAP (_PTR_TO_VOL_VOID_PTR PCI_TIBAP) |
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| 428 | |
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| 429 | /* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */ |
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| 430 | #define pPCI_DMBARM ((volatile unsigned long *)PCI_DMBARM) |
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| 431 | #define pPCI_DIBARM ((volatile unsigned long *)PCI_DIBARM) |
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| 432 | #define pPCI_CFG_DIC ((volatile unsigned long *)PCI_CFG_DIC) |
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| 433 | #define pPCI_CFG_VIC ((volatile unsigned long *)PCI_CFG_VIC) |
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| 434 | #define pPCI_CFG_STAT ((volatile unsigned long *)PCI_CFG_STAT) |
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| 435 | #define pPCI_CFG_CMD ((volatile unsigned long *)PCI_CFG_CMD) |
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| 436 | #define pPCI_CFG_CC ((volatile unsigned long *)PCI_CFG_CC) |
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| 437 | #define pPCI_CFG_RID ((volatile unsigned long *)PCI_CFG_RID) |
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| 438 | #define pPCI_CFG_BIST ((volatile unsigned long *)PCI_CFG_BIST) |
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| 439 | #define pPCI_CFG_HT ((volatile unsigned long *)PCI_CFG_HT) |
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| 440 | #define pPCI_CFG_MLT ((volatile unsigned long *)PCI_CFG_MLT) |
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| 441 | #define pPCI_CFG_CLS ((volatile unsigned long *)PCI_CFG_CLS) |
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| 442 | #define pPCI_CFG_MBAR ((volatile unsigned long *)PCI_CFG_MBAR) |
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| 443 | #define pPCI_CFG_IBAR ((volatile unsigned long *)PCI_CFG_IBAR) |
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| 444 | #define pPCI_CFG_SID ((volatile unsigned long *)PCI_CFG_SID) |
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| 445 | #define pPCI_CFG_SVID ((volatile unsigned long *)PCI_CFG_SVID) |
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| 446 | #define pPCI_CFG_MAXL ((volatile unsigned long *)PCI_CFG_MAXL) |
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| 447 | #define pPCI_CFG_MING ((volatile unsigned long *)PCI_CFG_MING) |
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| 448 | #define pPCI_CFG_IP ((volatile unsigned long *)PCI_CFG_IP) |
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| 449 | #define pPCI_CFG_IL ((volatile unsigned long *)PCI_CFG_IL) |
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| 450 | #define pPCI_HMCTL ((volatile unsigned long *)PCI_HMCTL) |
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| 451 | |
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| 452 | /* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ |
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| 453 | #define pDMA_DBP ((volatile unsigned short *)DMA_DBP) |
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| 454 | #define pDB_ACOMP (_PTR_TO_VOL_VOID_PTR DB_ACOMP) |
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| 455 | #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) |
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| 456 | |
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| 457 | #ifdef _MISRA_RULES |
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| 458 | #pragma diag(pop) |
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| 459 | #endif /* _MISRA_RULES */ |
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| 460 | |
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| 461 | #endif /* _CDEF_BF535_H */ |
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