| 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | /************************************************************************ |
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| 14 | * |
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| 15 | * cplb.h |
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| 16 | * |
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| 17 | * (c) Copyright 2002-2007 Analog Devices, Inc. All rights reserved. |
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| 18 | * |
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| 19 | ************************************************************************/ |
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| 20 | |
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| 21 | /* Defines necessary for cplb initialisation routines. */ |
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| 22 | |
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| 23 | #ifndef _CPLB_H |
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| 24 | #define _CPLB_H |
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| 25 | |
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| 26 | #include <sys/platform.h> |
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| 27 | |
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| 28 | #ifdef _MISRA_RULES |
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| 29 | #pragma diag(push) |
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| 30 | #pragma diag(suppress:misra_rule_19_4) |
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| 31 | #endif /* _MISRA_RULES */ |
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| 32 | |
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| 33 | #define CPLB_ENABLE_ICACHE_P 0 |
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| 34 | #define CPLB_ENABLE_DCACHE_P 1 |
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| 35 | #define CPLB_ENABLE_DCACHE2_P 2 |
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| 36 | #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ |
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| 37 | #define CPLB_ENABLE_ICPLBS_P 4 |
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| 38 | #define CPLB_ENABLE_DCPLBS_P 5 |
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| 39 | #define CPLB_SET_DCBS_P 6 |
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| 40 | #define CPLB_INVALIDATE_B_P 23 |
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| 41 | |
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| 42 | /* ___cplb_ctrl bitmasks */ |
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| 43 | #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) |
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| 44 | #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) |
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| 45 | #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) |
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| 46 | #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) |
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| 47 | #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) |
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| 48 | #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) |
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| 49 | #define CPLB_ENABLE_ANY_CPLBS \ |
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| 50 | ( CPLB_ENABLE_CPLBS | CPLB_ENABLE_ICPLBS | CPLB_ENABLE_DCPLBS ) |
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| 51 | #define CPLB_SET_DCBS (1<<CPLB_SET_DCBS_P) |
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| 52 | |
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| 53 | /* Bitmasks for dcache_invalidate routine parameters */ |
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| 54 | #define CPLB_INVALIDATE_A 0 |
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| 55 | #define CPLB_INVALIDATE_B (1<<CPLB_INVALIDATE_B_P) |
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| 56 | |
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| 57 | /* _cplb_mgr return values */ |
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| 58 | #define CPLB_RELOADED 0x0000 |
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| 59 | #define CPLB_NO_UNLOCKED 0x0001 |
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| 60 | #define CPLB_NO_ADDR_MATCH 0x0002 |
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| 61 | #define CPLB_PROT_VIOL 0x0003 |
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| 62 | #define CPLB_NO_ACTION 0x0004 |
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| 63 | |
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| 64 | /* CPLB configurations */ |
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| 65 | #define CPLB_DEF_CACHE_WT ( CPLB_L1_CHBL | CPLB_WT ) |
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| 66 | #define CPLB_DEF_CACHE_WB ( CPLB_L1_CHBL ) |
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| 67 | #define CPLB_CACHE_ENABLED ( CPLB_L1_CHBL | CPLB_DIRTY ) |
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| 68 | |
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| 69 | #define CPLB_DEF_CACHE ( CPLB_L1_CHBL | CPLB_WT ) |
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| 70 | #define CPLB_ALL_ACCESS ( CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR ) |
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| 71 | |
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| 72 | #define CPLB_I_PAGE_MGMT ( CPLB_LOCK | CPLB_VALID ) |
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| 73 | #define CPLB_D_PAGE_MGMT ( CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID ) |
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| 74 | #define CPLB_DNOCACHE ( CPLB_ALL_ACCESS | CPLB_VALID ) |
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| 75 | #define CPLB_DDOCACHE ( CPLB_DNOCACHE | CPLB_DEF_CACHE ) |
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| 76 | #define CPLB_INOCACHE ( CPLB_USER_RD | CPLB_VALID ) |
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| 77 | #define CPLB_IDOCACHE ( CPLB_INOCACHE | CPLB_L1_CHBL ) |
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| 78 | |
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| 79 | #define CPLB_DDOCACHE_WT ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WT ) |
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| 80 | #define CPLB_DDOCACHE_WB ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WB ) |
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| 81 | |
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| 82 | /* Event type parameter for replacement manager _cplb_mgr */ |
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| 83 | #define CPLB_EVT_ICPLB_MISS 0 |
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| 84 | #define CPLB_EVT_DCPLB_MISS 1 |
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| 85 | #define CPLB_EVT_DCPLB_WRITE 2 |
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| 86 | |
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| 87 | /* size of cplb tables */ |
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| 88 | #define __CPLB_TABLE_SIZE 16 |
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| 89 | |
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| 90 | #ifdef _MISRA_RULES |
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| 91 | #pragma diag(pop) |
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| 92 | #endif /* _MISRA_RULES */ |
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| 93 | |
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| 94 | #endif /* _CPLB_H */ |
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