| 1 | /* |
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| 2 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 3 | * and license this software and its documentation for any purpose, provided |
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| 4 | * that existing copyright notices are retained in all copies and that this |
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| 5 | * notice is included verbatim in any distributions. No written agreement, |
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| 6 | * license, or royalty fee is required for any of the authorized uses. |
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| 7 | * Modifications to this software may be copyrighted by their authors |
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| 8 | * and need not follow the licensing terms described here, provided that |
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| 9 | * the new terms are clearly indicated on the first page of each file where |
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| 10 | * they apply. |
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| 11 | */ |
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| 12 | |
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| 13 | /* |
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| 14 | ** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved. |
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| 15 | ** |
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| 16 | ************************************************************************************ |
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| 17 | ** |
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| 18 | ** This include file contains a list of macro "defines" to enable the programmer |
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| 19 | ** to use symbolic names for register-access and bit-manipulation. |
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| 20 | ** |
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| 21 | **/ |
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| 22 | #ifndef _DEF_BF514_H |
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| 23 | #define _DEF_BF514_H |
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| 24 | |
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| 25 | /* Include all Core registers and bit definitions */ |
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| 26 | #include <def_LPBlackfin.h> |
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| 27 | |
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| 28 | /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ |
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| 29 | |
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| 30 | /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ |
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| 31 | #include <defBF51x_base.h> |
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| 32 | |
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| 33 | #ifdef _MISRA_RULES |
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| 34 | #pragma diag(push) |
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| 35 | #pragma diag(suppress:misra_rule_19_4:"macros violate rule 19.4") |
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| 36 | #endif /* _MISRA_RULES */ |
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| 37 | |
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| 38 | /* The following are the #defines needed by ADSP-BF514 that are not in the common header */ |
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| 39 | |
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| 40 | /* RSI Registers */ |
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| 41 | |
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| 42 | #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ |
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| 43 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 44 | #define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */ |
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| 45 | #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ |
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| 46 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 47 | #define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */ |
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| 48 | #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ |
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| 49 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 50 | #define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */ |
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| 51 | #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ |
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| 52 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 53 | #define SDH_COMMAND RSI_COMMAND /* SDH Command */ |
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| 54 | #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ |
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| 55 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 56 | #define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */ |
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| 57 | #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ |
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| 58 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 59 | #define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */ |
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| 60 | #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ |
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| 61 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 62 | #define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */ |
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| 63 | #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ |
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| 64 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 65 | #define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */ |
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| 66 | #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ |
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| 67 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 68 | #define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */ |
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| 69 | #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ |
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| 70 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 71 | #define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */ |
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| 72 | #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ |
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| 73 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 74 | #define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */ |
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| 75 | #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ |
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| 76 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 77 | #define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */ |
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| 78 | #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ |
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| 79 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 80 | #define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */ |
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| 81 | #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ |
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| 82 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 83 | #define SDH_STATUS RSI_STATUS /* SDH Status */ |
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| 84 | #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ |
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| 85 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 86 | #define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */ |
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| 87 | #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ |
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| 88 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 89 | #define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */ |
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| 90 | #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ |
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| 91 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 92 | #define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */ |
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| 93 | #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ |
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| 94 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 95 | #define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */ |
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| 96 | #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ |
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| 97 | #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ |
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| 98 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 99 | #define SDH_FIFO RSI_FIFO /* SDH Data FIFO */ |
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| 100 | #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ |
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| 101 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 102 | #define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */ |
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| 103 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ |
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| 104 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 105 | #define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */ |
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| 106 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ |
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| 107 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 108 | #define SDH_CFG RSI_CONFIG /* SDH Configuration */ |
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| 109 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ |
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| 110 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 111 | #define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */ |
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| 112 | #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ |
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| 113 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 114 | #define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */ |
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| 115 | #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ |
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| 116 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 117 | #define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */ |
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| 118 | #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ |
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| 119 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 120 | #define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */ |
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| 121 | #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ |
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| 122 | /* legacy register name (below) provided for backwards code compatibility */ |
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| 123 | #define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */ |
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| 124 | /* RSI Registers */ |
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| 125 | |
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| 126 | |
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| 127 | |
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| 128 | /* ********************************************************** */ |
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| 129 | /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ |
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| 130 | /* and MULTI BIT READ MACROS */ |
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| 131 | /* ********************************************************** */ |
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| 132 | |
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| 133 | /* Bit masks for RSI_PWR_CONTROL */ |
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| 134 | #define PWR_ON 0x3 /* Power On */ |
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| 135 | #define RSI_CMD_OD 0x40 /* Open Drain Output */ |
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| 136 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 137 | #define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */ |
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| 138 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 139 | #define nSD_CMD_OD 0x0 |
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| 140 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 141 | #if 0 |
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| 142 | #define TBD 0x3c /* TBD */ |
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| 143 | #endif |
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| 144 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 145 | #define ROD_CTL 0x80 |
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| 146 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 147 | #define nROD_CTL 0x80 |
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| 148 | |
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| 149 | |
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| 150 | /* Bit masks for RSI_CLK_CONTROL */ |
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| 151 | #define CLKDIV 0xff /* MC_CLK Divisor */ |
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| 152 | #define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */ |
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| 153 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 154 | #define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */ |
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| 155 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 156 | #define nCLK_E 0x0 |
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| 157 | #define PWR_SV_EN 0x200 /* Power Save Enable */ |
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| 158 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 159 | #define PWR_SV_E PWR_SV_EN /* Power Save Enable */ |
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| 160 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 161 | #define nPWR_SV_E 0x0 |
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| 162 | #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ |
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| 163 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 164 | #define nCLKDIV_BYPASS 0x0 |
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| 165 | #define BUS_MODE 0x1800 /* Bus width selection */ |
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| 166 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 167 | #define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */ |
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| 168 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 169 | #define nWIDE_BUS 0x0 |
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| 170 | |
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| 171 | |
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| 172 | /* Bit masks for RSI_COMMAND */ |
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| 173 | #define CMD_IDX 0x3f /* Command Index */ |
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| 174 | #define CMD_RSP_EN 0x40 /* Response */ |
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| 175 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 176 | #define CMD_RSP CMD_RSP_EN /* Response */ |
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| 177 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 178 | #define nCMD_RSP 0x0 |
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| 179 | #define CMD_LRSP_EN 0x80 /* Long Response */ |
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| 180 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 181 | #define CMD_L_RSP CMD_LRSP_EN /* Long Response */ |
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| 182 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 183 | #define nCMD_L_RSP 0x0 |
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| 184 | #define CMD_INT_EN 0x100 /* Command Interrupt */ |
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| 185 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 186 | #define CMD_INT_E CMD_INT_EN /* Command Interrupt */ |
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| 187 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 188 | #define nCMD_INT_E 0x0 |
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| 189 | #define CMD_PEND_EN 0x200 /* Command Pending */ |
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| 190 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 191 | #define CMD_PEND_E CMD_PEND_EN /* Command Pending */ |
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| 192 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 193 | #define nCMD_PEND_E 0x0 |
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| 194 | #define CMD_EN 0x400 /* Command Enable */ |
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| 195 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 196 | #define CMD_E CMD_EN /* Command Enable */ |
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| 197 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 198 | #define nCMD_E 0x0 |
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| 199 | |
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| 200 | |
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| 201 | /* Bit masks for RSI_RESP_CMD */ |
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| 202 | #define RESP_CMD 0x3f /* Response Command */ |
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| 203 | |
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| 204 | /* Bit masks for RSI_DATA_LGTH */ |
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| 205 | #define DATA_LENGTH 0xffff /* Data Length */ |
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| 206 | |
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| 207 | |
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| 208 | /* Bit masks for RSI_DATA_CONTROL */ |
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| 209 | #define DATA_EN 0x1 /* Data Transfer Enable */ |
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| 210 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 211 | #define DTX_E DATA_EN /* Data Transfer Enable */ |
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| 212 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 213 | #define nDTX_E 0x0 |
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| 214 | #define DATA_DIR 0x2 /* Data Transfer Direction */ |
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| 215 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 216 | #define DTX_DIR DATA_DIR /* Data Transfer Direction */ |
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| 217 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 218 | #define nDTX_DIR 0x0 |
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| 219 | #define DATA_MODE 0x4 /* Data Transfer Mode */ |
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| 220 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 221 | #define DTX_MODE DATA_MODE /* Data Transfer Mode */ |
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| 222 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 223 | #define nDTX_MODE 0x0 |
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| 224 | #define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */ |
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| 225 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 226 | #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ |
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| 227 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 228 | #define nDTX_DMA_E 0x0 |
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| 229 | #define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */ |
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| 230 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 231 | #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ |
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| 232 | #define CEATA_EN 0x100 /* CE-ATA operation mode enable */ |
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| 233 | #define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */ |
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| 234 | |
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| 235 | /* Bit masks for RSI_DATA_CNT */ |
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| 236 | #define DATA_COUNT 0xffff /* Data Count */ |
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| 237 | |
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| 238 | /* Bit masks for RSI_STATUS */ |
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| 239 | #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ |
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| 240 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 241 | #define nCMD_CRC_FAIL 0x0 |
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| 242 | #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ |
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| 243 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 244 | #define nDAT_CRC_FAIL 0x0 |
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| 245 | #define CMD_TIMEOUT 0x4 /* CMD Time Out */ |
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| 246 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 247 | #define nCMD_TIMEOUT 0x0 |
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| 248 | #define DAT_TIMEOUT 0x8 /* Data Time Out */ |
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| 249 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 250 | #define nDAT_TIMEOUT 0x0 |
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| 251 | #define TX_UNDERRUN 0x10 /* Transmit Underrun */ |
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| 252 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 253 | #define nTX_UNDERRUN 0x0 |
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| 254 | #define RX_OVERRUN 0x20 /* Receive Overrun */ |
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| 255 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 256 | #define nRX_OVERRUN 0x0 |
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| 257 | #define CMD_RESP_END 0x40 /* CMD Response End */ |
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| 258 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 259 | #define nCMD_RESP_END 0x0 |
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| 260 | #define CMD_SENT 0x80 /* CMD Sent */ |
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| 261 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 262 | #define nCMD_SENT 0x0 |
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| 263 | #define DAT_END 0x100 /* Data End */ |
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| 264 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 265 | #define nDAT_END 0x0 |
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| 266 | #define START_BIT_ERR 0x200 /* Start Bit Error */ |
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| 267 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 268 | #define nSTART_BIT_ERR 0x0 |
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| 269 | #define DAT_BLK_END 0x400 /* Data Block End */ |
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| 270 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 271 | #define nDAT_BLK_END 0x0 |
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| 272 | #define CMD_ACT 0x800 /* CMD Active */ |
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| 273 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 274 | #define nCMD_ACT 0x0 |
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| 275 | #define TX_ACT 0x1000 /* Transmit Active */ |
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| 276 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 277 | #define nTX_ACT 0x0 |
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| 278 | #define RX_ACT 0x2000 /* Receive Active */ |
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| 279 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 280 | #define nRX_ACT 0x0 |
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| 281 | #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ |
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| 282 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 283 | #define nTX_FIFO_STAT 0x0 |
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| 284 | #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ |
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| 285 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 286 | #define nRX_FIFO_STAT 0x0 |
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| 287 | #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ |
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| 288 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 289 | #define nTX_FIFO_FULL 0x0 |
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| 290 | #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ |
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| 291 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 292 | #define nRX_FIFO_FULL 0x0 |
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| 293 | #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ |
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| 294 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 295 | #define nTX_FIFO_ZERO 0x0 |
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| 296 | #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ |
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| 297 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 298 | #define nRX_DAT_ZERO 0x0 |
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| 299 | #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ |
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| 300 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 301 | #define nTX_DAT_RDY 0x0 |
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| 302 | #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ |
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| 303 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 304 | #define nRX_FIFO_RDY 0x0 |
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| 305 | |
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| 306 | /* Bit masks for RSI_STATCL */ |
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| 307 | #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ |
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| 308 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 309 | #define nCMD_CRC_FAIL_STAT 0x0 |
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| 310 | #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ |
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| 311 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 312 | #define nDAT_CRC_FAIL_STAT 0x0 |
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| 313 | #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ |
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| 314 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 315 | #define nCMD_TIMEOUT_STAT 0x0 |
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| 316 | #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ |
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| 317 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 318 | #define nDAT_TIMEOUT_STAT 0x0 |
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| 319 | #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ |
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| 320 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 321 | #define nTX_UNDERRUN_STAT 0x0 |
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| 322 | #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ |
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| 323 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 324 | #define nRX_OVERRUN_STAT 0x0 |
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| 325 | #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ |
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| 326 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 327 | #define nCMD_RESP_END_STAT 0x0 |
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| 328 | #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ |
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| 329 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 330 | #define nCMD_SENT_STAT 0x0 |
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| 331 | #define DAT_END_STAT 0x100 /* Data End Status */ |
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| 332 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 333 | #define nDAT_END_STAT 0x0 |
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| 334 | #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ |
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| 335 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 336 | #define nSTART_BIT_ERR_STAT 0x0 |
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| 337 | #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ |
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| 338 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 339 | #define nDAT_BLK_END_STAT 0x0 |
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| 340 | |
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| 341 | /* Bit masks for RSI_MASKx */ |
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| 342 | #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ |
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| 343 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 344 | #define nCMD_CRC_FAIL_MASK 0x0 |
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| 345 | #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ |
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| 346 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 347 | #define nDAT_CRC_FAIL_MASK 0x0 |
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| 348 | #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ |
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| 349 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 350 | #define nCMD_TIMEOUT_MASK 0x0 |
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| 351 | #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ |
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| 352 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 353 | #define nDAT_TIMEOUT_MASK 0x0 |
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| 354 | #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ |
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| 355 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 356 | #define nTX_UNDERRUN_MASK 0x0 |
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| 357 | #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ |
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| 358 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 359 | #define nRX_OVERRUN_MASK 0x0 |
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| 360 | #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ |
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| 361 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 362 | #define nCMD_RESP_END_MASK 0x0 |
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| 363 | #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ |
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| 364 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 365 | #define nCMD_SENT_MASK 0x0 |
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| 366 | #define DAT_END_MASK 0x100 /* Data End Mask */ |
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| 367 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 368 | #define nDAT_END_MASK 0x0 |
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| 369 | #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ |
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| 370 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 371 | #define nSTART_BIT_ERR_MASK 0x0 |
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| 372 | #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ |
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| 373 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 374 | #define nDAT_BLK_END_MASK 0x0 |
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| 375 | #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ |
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| 376 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 377 | #define nCMD_ACT_MASK 0x0 |
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| 378 | #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ |
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| 379 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 380 | #define nTX_ACT_MASK 0x0 |
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| 381 | #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ |
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| 382 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 383 | #define nRX_ACT_MASK 0x0 |
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| 384 | #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ |
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| 385 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 386 | #define nTX_FIFO_STAT_MASK 0x0 |
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| 387 | #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ |
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| 388 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 389 | #define nRX_FIFO_STAT_MASK 0x0 |
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| 390 | #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ |
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| 391 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 392 | #define nTX_FIFO_FULL_MASK 0x0 |
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| 393 | #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ |
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| 394 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 395 | #define nRX_FIFO_FULL_MASK 0x0 |
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| 396 | #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ |
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| 397 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 398 | #define nTX_FIFO_ZERO_MASK 0x0 |
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| 399 | #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ |
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| 400 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 401 | #define nRX_DAT_ZERO_MASK 0x0 |
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| 402 | #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ |
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| 403 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 404 | #define nTX_DAT_RDY_MASK 0x0 |
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| 405 | #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ |
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| 406 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 407 | #define nRX_FIFO_RDY_MASK 0x0 |
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| 408 | |
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| 409 | /* Bit masks for RSI_FIFO_CNT */ |
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| 410 | #define FIFO_COUNT 0x7fff /* FIFO Count */ |
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| 411 | |
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| 412 | /* Bit masks for RSI_CEATA_CONTROL */ |
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| 413 | #define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */ |
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| 414 | |
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| 415 | /* Bit masks for RSI_ESTAT */ |
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| 416 | #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ |
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| 417 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 418 | #define nSDIO_INT_DET 0x0 |
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| 419 | #define SD_CARD_DET 0x10 /* SD Card Detect */ |
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| 420 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 421 | #define nSD_CARD_DET 0x0 |
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| 422 | #define CEATA_INT_DET 0x20 |
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| 423 | |
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| 424 | /* Bit masks for RSI_EMASK */ |
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| 425 | #define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */ |
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| 426 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 427 | #define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */ |
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| 428 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 429 | #define nSDIO_MSK 0x0 |
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| 430 | #define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */ |
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| 431 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 432 | #define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */ |
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| 433 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 434 | #define nSCD_MSK 0x0 |
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| 435 | #define CEATA_INT_DET_MASK 0x20 |
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| 436 | |
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| 437 | |
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| 438 | /* Bit masks for RSI_CFG */ |
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| 439 | /* Left in for backwards compatibility */ |
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| 440 | #define RSI_CLK_EN 0x1 |
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| 441 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 442 | #define CLKS_EN RSI_CLK_EN /* Clocks Enable */ |
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| 443 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 444 | #define nCLKS_EN 0x0 |
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| 445 | #define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */ |
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| 446 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 447 | #define SD4E SDIO4_EN /* SDIO 4-Bit Enable */ |
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| 448 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 449 | #define nSD4E 0x0 |
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| 450 | #define MW_EN 0x8 /* Moving Window Enable */ |
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| 451 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 452 | #define MWE MW_EN /* Moving Window Enable */ |
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| 453 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 454 | #define nMWE 0x0 |
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| 455 | #define RSI_RST 0x10 /* SDMMC Reset */ |
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| 456 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 457 | #define SD_RST RSI_RST /* SDMMC Reset */ |
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| 458 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 459 | #define nSD_RST 0x0 |
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| 460 | #define PU_DAT 0x20 /* Pull-up SD_DAT */ |
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| 461 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 462 | #define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */ |
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| 463 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 464 | #define nPUP_SDDAT 0x0 |
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| 465 | #define PU_DAT3 0x40 /* Pull-up SD_DAT3 */ |
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| 466 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 467 | #define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */ |
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| 468 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 469 | #define nPUP_SDDAT3 0x0 |
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| 470 | #define PD_DAT3 0x80 /* Pull-down SD_DAT3 */ |
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| 471 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 472 | #define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */ |
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| 473 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 474 | #define nPD_SDDAT3 0x0 |
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| 475 | |
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| 476 | |
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| 477 | /* Bit masks for RSI_RD_WAIT_EN */ |
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| 478 | #define SDIO_RWR 0x1 /* Read Wait Request */ |
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| 479 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 480 | #define RWR SDIO_RWR /* Read Wait Request */ |
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| 481 | /* legacy bit mask (below) provided for backwards code compatibility */ |
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| 482 | #define nRWR 0x0 |
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| 483 | |
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| 484 | /* Bit masks for RSI_PIDx */ |
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| 485 | #define RSI_PID 0xff /* RSI Peripheral ID */ |
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| 486 | #ifdef _MISRA_RULES |
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| 487 | #pragma diag(pop) |
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| 488 | #endif /* _MISRA_RULES */ |
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| 489 | |
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| 490 | #endif /* _DEF_BF514_H */ |
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